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Elphel
x393
Commits
dedb0313
Commit
dedb0313
authored
Jun 24, 2016
by
Oleg Dzhimiev
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1.install imgsrv to /www/pages 2.default bitstream path=/tmp/
parent
0c04eb6a
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5
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+7
-4
install.sh
install.sh
+5
-0
hargs
py393/hargs
+0
-1
startup14
py393/startup14
+0
-1
startup5
py393/startup5
+0
-1
x393_utils.py
py393/x393_utils.py
+2
-1
No files found.
install.sh
View file @
dedb0313
...
...
@@ -11,6 +11,11 @@ install -d -v $1/usr/local/verilog/
install
-d
-v
$1
/usr/local/bin/
install
-v
-m
0755
$SCRIPTPATH
/py393/
*
.py
$1
/usr/local/bin/
install
-d
-v
$1
/www/pages/
install
-v
-m
0755
$SCRIPTPATH
/py393/imgsrv.py
$1
/www/pages/
#unistall
rm
$1
/usr/local/bin/imgsrv.py
install
-v
-m
0644
$SCRIPTPATH
/
*
.bit
$1
/usr/local/verilog/
install
-v
-m
0644
$SCRIPTPATH
/system_defines.vh
$1
/usr/local/verilog/
...
...
py393/hargs
View file @
dedb0313
...
...
@@ -3,5 +3,4 @@
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c copy /usr/local/bin/imgsrv.py /www/pages
-i
\ No newline at end of file
py393/startup14
View file @
dedb0313
...
...
@@ -3,7 +3,6 @@
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c copy /usr/local/bin/imgsrv.py /www/pages
-c setupSensorsPower "HISPI"
-c measure_all "*DI"
-c setup_all_sensors True None 0xf
...
...
py393/startup5
View file @
dedb0313
...
...
@@ -3,7 +3,6 @@
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c copy /usr/local/bin/imgsrv.py /www/pages
-c setupSensorsPower "PAR12"
-c measure_all "*DI"
-c setup_all_sensors True None 0xf
...
...
py393/x393_utils.py
View file @
dedb0313
...
...
@@ -39,7 +39,8 @@ from time import sleep
import
vrlg
# global parameters
import
x393_axi_control_status
import
shutil
DEFAULT_BITFILE
=
"/usr/local/verilog/x393.bit"
#DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
DEFAULT_BITFILE
=
"/tmp/x393.bit"
FPGA_RST_CTRL
=
0xf8000240
FPGA0_THR_CTRL
=
0xf8000178
FPGA_LVL_SHFTR
=
0xf8000900
# 0xf: all enabled, 0x0 - disable all
...
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