more debugging (d3f2d87c) · Commits · Elphel / x393

dsp/dsp_ma_preadd.v

+4 −5

Original line number	Original line	Diff line number	Diff line
	@@ -42,8 +42,7 @@ module dsp_ma_preadd #(
	parameter B_WIDTH = 18,		parameter B_WIDTH = 18,
	parameter A_WIDTH = 25,		parameter A_WIDTH = 25,
	parameter P_WIDTH = 48,		parameter P_WIDTH = 48,
	parameter A_INPUT = "DIRECT", // other: "CASCADE"		parameter BREG = 1) // means number in series, so "2" always reads the second
	parameter B_INPUT = "DIRECT") // other: "CASCADE"
	(		(
	input clk,		input clk,
	input rst,		input rst,
	@@ -89,10 +88,10 @@ module dsp_ma_preadd #(
	.ALUMODEREG (1),		.ALUMODEREG (1),
	.AREG (1), // 2), // (1) - means number in series, so "2" always reads the second		.AREG (1), // 2), // (1) - means number in series, so "2" always reads the second
	.AUTORESET_PATDET ("NO_RESET"),		.AUTORESET_PATDET ("NO_RESET"),
	.A_INPUT (A_INPUT), // "DIRECT", "CASCADE"		.A_INPUT ("DIRECT"), // "DIRECT", "CASCADE"
	.BCASCREG (1),		.BCASCREG (1),
	.BREG (1), // (2), // (1) - means number in series, so "2" always reads the second		.BREG (BREG), // (2), // (1) - means number in series, so "2" always reads the second
	.B_INPUT (B_INPUT), // "DIRECT"),		.B_INPUT ("DIRECT"), // "DIRECT"),
	.CARRYINREG (1),		.CARRYINREG (1),
	.CARRYINSELREG (1),		.CARRYINSELREG (1),
	.CREG (0), //(1),		.CREG (0), //(1),

dsp/dsp_ma_preadd_c_dbg.v

0 → 100644

+260 −0

Original line number	Original line	Diff line number	Diff line
			/*!
			* dsp_ma_preadd_c
			* @file dsp_ma_preadd.v
			* @date 2016-06-05
			* @author Andrey Filippov
			*
			* @brief DSP with multi-input multiplier and accumulator with pre-adder
			* and post-adder
			*
			* @copyright Copyright (c) 2016 Elphel, Inc.
			*
			* <b>License:</b>
			*
			* dsp_ma_preadd.v is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* dsp_ma_preadd.v is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*
			* Additional permission under GNU GPL version 3 section 7:
			* If you modify this Program, or any covered work, by linking or combining it
			* with independent modules provided by the FPGA vendor only (this permission
			* does not extend to any 3-rd party modules, "soft cores" or macros) under
			* different license terms solely for the purpose of generating binary "bitstream"
			* files and/or simulating the code, the copyright holders of this Program give
			* you the right to distribute the covered work without those independent modules
			* as long as the source code for them is available from the FPGA vendor free of
			* charge, and there is no dependence on any encrypted modules for simulating of
			* the combined code. This permission applies to you if the distributed code
			* contains all the components and scripts required to completely simulate it
			* with at least one of the Free Software programs.
			*/
			`timescale 1ns/1ps
			//`define INSTANTIATE_DSP48E1
			//`undef INSTANTIATE_DSP48E1
			module dsp_ma_preadd_c_dbg #(
			parameter B_WIDTH = 18,
			parameter A_WIDTH = 25,
			parameter P_WIDTH = 48)
			(
			input clk,
			input rst,
			input signed [B_WIDTH-1:0] bin,
			input ceb1, // load b1 register
			input ceb2, // load b2 register
			input selb, // 0 - select b1, 1 - select b2
			input signed [A_WIDTH-1:0] ain,
			input cea1, // clock enable a1 reg
			input cea2, // clock enable a2 reg
			input signed [A_WIDTH-1:0] din,
			input ced, // enable d-reg
			input signed [P_WIDTH-1:0] cin, // c - input
			input cec, // enable c-reg
			input cead, // enable ad register (after pre-adder)
			input sela, // 0 - select a1, 1 - select a2
			input en_a, // 1 - enable a input (0 - zero) ~inmode[1]
			input en_d, // 1 - enable d input (0 - zero) ~inmode[2]
			input sub_a, // 0 - pre-add (D+A), 1 - pre-subtract (D-A)
			input neg_m, // 1 - negate multiplier result
			input accum, // 0 - use multiplier result, 1 add to accumulator
			input post_add, // 0 - use multiplier or add to accumulator, 1 - add C and multiplier
			output signed [P_WIDTH-1:0] pout
			);
			`ifdef INSTANTIATE_DSP48E1
			initial begin
			$display("dsp_ma_preadd_c_dbg, using DSP48E1");
			end

			wire [4:0] inmode = {~selb,
			sub_a,
			en_d,
			~en_a,
			~sela};
			wire [3:0] alumode = {2'b0,
			neg_m,
			neg_m};
			wire [6:0] opmode = {1'b0,
			accum \| post_add,
			post_add,
			2'b01,
			2'b01};

			DSP48E1 #(
			.ACASCREG (1),
			.ADREG (1),
			.ALUMODEREG (1),
			.AREG (1), // 2), // (1) - means number in series, so "2" always reads the second
			.AUTORESET_PATDET ("NO_RESET"),
			.A_INPUT ("DIRECT"),
			.BCASCREG (1),
			.BREG (1), // (2), // (1) - means number in series, so "2" always reads the second
			.B_INPUT ("DIRECT"),
			.CARRYINREG (1),
			.CARRYINSELREG (1),
			.CREG (1), //(0),
			.DREG (1),
			.INMODEREG (1),
			.IS_ALUMODE_INVERTED (4'b0),
			.IS_CARRYIN_INVERTED (1'b0),
			.IS_CLK_INVERTED (1'b0),
			.IS_INMODE_INVERTED (5'b0),
			.IS_OPMODE_INVERTED (7'b0),
			.MASK (48'hffffffffffff),
			.MREG (1),
			.OPMODEREG (1),
			.PATTERN (48'h000000000000),
			.PREG (1),
			.SEL_MASK ("MASK"),
			.SEL_PATTERN ("PATTERN"),
			.USE_DPORT ("TRUE"), //("FALSE"),
			.USE_MULT ("MULTIPLY"),
			.USE_PATTERN_DETECT ("NO_PATDET"),
			.USE_SIMD ("ONE48")
			) DSP48E1_i (
			.ACOUT (), // output[29:0]
			.BCOUT (), // output[17:0]
			.CARRYCASCOUT (), // output
			.CARRYOUT (), // output[3:0]
			.MULTSIGNOUT (), // output
			.OVERFLOW (), // output
			.P (pout), // output[47:0]
			.PATTERNBDETECT (), // output
			.PATTERNDETECT (), // output
			.PCOUT (), // output[47:0]
			.UNDERFLOW (), // output
			.A ({{30-A_WIDTH{ain[A_WIDTH-1]}}, ain}), // input[29:0]
			.ACIN (30'b0), // input[29:0]
			.ALUMODE (alumode), // input[3:0]
			.B (bin), // input[17:0]
			.BCIN (18'b0), // input[17:0]
			.C (cin), // input[47:0]
			.CARRYCASCIN (1'b0), // input
			.CARRYIN (1'b0), // input
			.CARRYINSEL (3'h0), // input[2:0] // later modify?
			.CEA1 (cea1), // input
			.CEA2 (cea2), // input
			.CEAD (cead), // input
			.CEALUMODE (1'b1), // input
			.CEB1 (ceb1), // input
			.CEB2 (ceb2), // input
			.CEC (cec), // input
			.CECARRYIN (1'b0), // input
			.CECTRL (1'b1), // input
			.CED (ced), // input
			.CEINMODE (1'b1), // input
			.CEM (1'b1), // input
			.CEP (1'b1), // input
			.CLK (clk), // input
			.D (din), // input[24:0]
			.INMODE (inmode), // input[4:0]
			.MULTSIGNIN (1'b0), // input
			.OPMODE (opmode), // input[6:0]
			.PCIN (48'b0), // input[47:0]
			.RSTA (rst), // input
			.RSTALLCARRYIN (rst), // input
			.RSTALUMODE (rst), // input
			.RSTB (rst), // input
			.RSTC (rst), // input
			.RSTCTRL (rst), // input
			.RSTD (rst), // input
			.RSTINMODE (rst), // input
			.RSTM (rst), // input
			.RSTP (rst) // input
			);

			`else
			initial begin
			$display("dsp_ma_preadd_c, not using DSP48E1");
			end

			// Will try to make it infer DSP48e1
			reg signed [B_WIDTH-1:0] b1_reg;
			reg signed [B_WIDTH-1:0] b2_reg;
			reg signed [A_WIDTH-1:0] a1_reg;
			reg signed [A_WIDTH-1:0] a2_reg;
			reg signed [A_WIDTH-1:0] d_reg;
			reg signed [P_WIDTH-1:0] c_reg;
			reg signed [A_WIDTH-1:0] ad_reg;
			reg signed [P_WIDTH-1:0] m_reg;
			reg signed [P_WIDTH-1:0] p_reg;
			wire signed [A_WIDTH+B_WIDTH-1:0] m_wire;
			wire signed [B_WIDTH-1:0] b_wire;
			wire signed [A_WIDTH-1:0] a_wire;
			wire signed [A_WIDTH-1:0] d_wire;
			reg selb_r;
			reg sela_r;
			reg en_a_r;
			reg en_d_r;
			reg sub_a_r;
			reg neg_m_r;
			reg accum_r;
			reg post_add_r;
			wire signed [P_WIDTH-1:0] m_reg_pm;
			wire signed [P_WIDTH-1:0] p_reg_cond;
			/*
			input signed [P_WIDTH-1:0] cin, // c - input
			input cec, // enable c-reg
			input post_add, // 0 - use multiplier or add to accumulator, 1 - add C and multiplier

			*/

			assign pout = p_reg;
			assign b_wire = selb_r ? b2_reg : b1_reg;
			assign a_wire = en_a_r ? (sela_r ? a2_reg : a1_reg) : {A_WIDTH{1'b0}};
			// assign d_wire = en_d_r ? (sub_a_r ? -d_reg : d_reg) : {A_WIDTH{1'b0}};
			assign d_wire = en_d_r ? d_reg : {A_WIDTH{1'b0}};
			assign m_wire = ad_reg * b_wire;

			assign m_reg_pm = neg_m_r ? - m_reg : m_reg;
			// assign p_reg_cond = accum_r ? p_reg : 0;
			assign p_reg_cond = post_add_r? c_reg: (accum_r ? p_reg : 0);

			always @ (posedge clk) begin
			if (rst) b1_reg <= 0;
			else if (ceb1) b1_reg <= bin;

			if (rst) b2_reg <= 0;
			else if (ceb2) b2_reg <= bin;

			if (rst) a1_reg <= 0;
			else if (cea1) a1_reg <= ain;

			if (rst) a2_reg <= 0;
			else if (cea2) a2_reg <= ain;

			if (rst) d_reg <= 0;
			else if (ced) d_reg <= din;

			if (rst) c_reg <= 0;
			else if (cec) c_reg <= cin;

			if (rst) ad_reg <= 0;
			else if (cead) ad_reg <= sub_a_r? (d_wire - a_wire): (d_wire + a_wire);

			neg_m_r <= neg_m;
			accum_r <= accum;
			post_add_r <= post_add;

			selb_r <= selb;
			sela_r <= sela;
			en_a_r <= en_a;
			en_d_r <= en_d;
			sub_a_r <= sub_a;

			m_reg <= {{P_WIDTH - A_WIDTH - B_WIDTH{m_wire[A_WIDTH+B_WIDTH-1]}}, m_wire};

			p_reg <= p_reg_cond + m_reg_pm;

			end
			`endif

			endmodule

dsp/mclt16x16.v

+42 −21

Original line number	Original line	Diff line number	Diff line
	@@ -76,11 +76,19 @@ module mclt16x16#(
	output dv, //!< output data valid		output dv, //!< output data valid
	output signed [OUT_WIDTH - 1 : 0] dout //!<frequency domain data output		output signed [OUT_WIDTH - 1 : 0] dout //!<frequency domain data output
	);		);
			localparam DTT_OUT_DELAY = 191; // start output to sin/cos rotator, ~=3/4 of 256
			localparam DTT_IN_DELAY = 195; // fune tune? ~= 3/4 of 256

			// maybe use small FIFO memory?
			reg [SHIFT_WIDTH-1:0] x_shft_r; // registered at start
			reg [SHIFT_WIDTH-1:0] y_shft_r; // registered at start
			reg [SHIFT_WIDTH-1:0] x_shft_r2; // use for the window calculation
			reg [SHIFT_WIDTH-1:0] y_shft_r2; // use for the window calculation
			reg [SHIFT_WIDTH-1:0] x_shft_r3; // registered @ start_dtt
			reg [SHIFT_WIDTH-1:0] y_shft_r3; // registered @ start_dtt
			reg [SHIFT_WIDTH-1:0] x_shft_r4; // registered @ dtt_start_first_fill
			reg [SHIFT_WIDTH-1:0] y_shft_r4; // registered @ dtt_start_first_fill

	reg [SHIFT_WIDTH-1:0] x_shft_r;
	reg [SHIFT_WIDTH-1:0] y_shft_r;
	reg [SHIFT_WIDTH-1:0] x_shft_r2;
	reg [SHIFT_WIDTH-1:0] y_shft_r2;
	reg [3:0] bayer_r;		reg [3:0] bayer_r;
	reg [3:0] bayer_d; // same latency as mpix_a_w		reg [3:0] bayer_d; // same latency as mpix_a_w
	reg [7:0] in_cntr; // input counter		reg [7:0] in_cntr; // input counter
	@@ -139,7 +147,7 @@ module mclt16x16#(
	wire var_last; // next cycle the data_xx_r will have data (in_busy[14], ...)		wire var_last; // next cycle the data_xx_r will have data (in_busy[14], ...)

	// reading/converting DTT		// reading/converting DTT
	wire start_dtt = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256		reg start_dtt; // = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256
	reg [7:0] dtt_r_cntr; //		reg [7:0] dtt_r_cntr; //
	reg dtt_r_page;		reg dtt_r_page;
	reg dtt_r_re;		reg dtt_r_re;
	@@ -166,13 +174,21 @@ module mclt16x16#(
	bayer_r <= bayer;		bayer_r <= bayer;
	end		end
	start_r <= {start_r[0], start};		start_r <= {start_r[0], start};
	// if (in_busy[2]) begin // same latency as mpix_a_w
	if (start_r[1]) begin // same latency as mpix_a_w		if (start_r[1]) begin // same latency as mpix_a_w
	x_shft_r2 <= x_shft_r;		x_shft_r2 <= x_shft_r; // use for the window
	y_shft_r2 <= y_shft_r;		y_shft_r2 <= y_shft_r;
	end		end

	/// if (in_busy[2]) bayer_d <= bayer_r;		if (start_dtt) begin
			x_shft_r3 <= x_shft_r2;
			y_shft_r3 <= y_shft_r2;
			end

			if (dtt_start_first_fill) begin
			x_shft_r4 <= x_shft_r3;
			y_shft_r4 <= y_shft_r3;
			end

	if (in_busy[1]) bayer_d <= bayer_r;		if (in_busy[1]) bayer_d <= bayer_r;

	if (rst) in_busy <= 0;		if (rst) in_busy <= 0;
	@@ -190,11 +206,7 @@ module mclt16x16#(
	if (in_busy[9]) pix_wnd_r <= mpixel_d_r * window_r; // 1 MSB is extra		if (in_busy[9]) pix_wnd_r <= mpixel_d_r * window_r; // 1 MSB is extra

	// pix_wnd_r2 - positive with 2 extra zeros, max value 0x3fff60		// pix_wnd_r2 - positive with 2 extra zeros, max value 0x3fff60
	/// if (in_busy[10]) pix_wnd_r2 <= {2'b00,pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]};
	if (in_busy[10]) begin		if (in_busy[10]) begin
	/// if (in_busy[9]) begin
	/// pix_wnd_r2 <= {2'b0,pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]};
	// pix_wnd_r2_old <= {{2{pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2]}},pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]};
	pix_wnd_r2 <= {{2{pix_wnd_r2_w[DTT_IN_WIDTH-3]}},pix_wnd_r2_w};		pix_wnd_r2 <= {{2{pix_wnd_r2_w[DTT_IN_WIDTH-3]}},pix_wnd_r2_w};
	mpix_use_r <= mpix_use_d;		mpix_use_r <= mpix_use_d;
	var_first_r <= var_first_d;		var_first_r <= var_first_d;
	@@ -222,6 +234,9 @@ module mclt16x16#(
	if (!in_busy[16]) dtt_in_cntr <= 0;		if (!in_busy[16]) dtt_in_cntr <= 0;
	else dtt_in_cntr <= dtt_in_cntr + 1;		else dtt_in_cntr <= dtt_in_cntr + 1;

			start_dtt <= dtt_in_cntr == DTT_IN_DELAY;


	if (rst) dtt_in_page <= 0;		if (rst) dtt_in_page <= 0;
	else if (&dtt_in_cntr) dtt_in_page <= dtt_in_page + 1;		else if (&dtt_in_cntr) dtt_in_page <= dtt_in_page + 1;

	@@ -435,15 +450,17 @@ D11 - negate for mode 3 (SS)
	reg [4:0] dtt_out_ram_cntr;		reg [4:0] dtt_out_ram_cntr;
	reg [4:0] dtt_out_ram_wah;		reg [4:0] dtt_out_ram_wah;
	wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout		wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
			reg dtt_start_first_fill;
	reg dtt_start_out; // start read out to sin/cos rotator		reg dtt_start_out; // start read out to sin/cos rotator

	// frequency domain, high address bit - page, 2 next - mode, 6 LSBs - transposed FD data (vertical first)		// frequency domain, high address bit - page, 2 next - mode, 6 LSBs - transposed FD data (vertical first)
	wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};		wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};

	localparam DTT_OUT_DELAY = 192; // start output to sin/cos rotator, ~=3/4 of 256
	reg [7:0] dtt_dly_cntr;		reg [7:0] dtt_dly_cntr;
	reg [8:0] dtt_rd_cntr; // counter for dtt readout to rotator		reg [8:0] dtt_rd_cntr; // counter for dtt readout to rotator
	wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[1:0],dtt_rd_cntr[7:2]}; // page, mode, frequency		// wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[1:0],dtt_rd_cntr[7:2]}; // page, mode, frequency
			wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency
	reg [2:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid		reg [2:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid
	wire [35:0] dtt_rd_data_w; // high bits are not used		wire [35:0] dtt_rd_data_w; // high bits are not used
	// data to be input to phase rotator		// data to be input to phase rotator
	@@ -457,10 +474,14 @@ D11 - negate for mode 3 (SS)
	else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;		else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;
	dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;		dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;

			dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;

	if (rst) dtt_dly_cntr <= 0;		if (rst) dtt_dly_cntr <= 0;
	else if (dtt_start_fill & dtt_first_quad_out) dtt_dly_cntr <= DTT_OUT_DELAY;		else if (dtt_start_first_fill) dtt_dly_cntr <= DTT_OUT_DELAY;
	else if (\|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1;		else if (\|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1;



	dtt_start_out <= dtt_dly_cntr == 1;		dtt_start_out <= dtt_dly_cntr == 1;

	if (rst) dtt_rd_regen_dv[0] <= 0;		if (rst) dtt_rd_regen_dv[0] <= 0;
	@@ -534,8 +555,8 @@ D11 - negate for mode 3 (SS)
	.rst (rst), // input		.rst (rst), // input
	.start (dtt_start_out), // input		.start (dtt_start_out), // input
	// are these shift OK? Will need to be valis only @ dtt_start_out		// are these shift OK? Will need to be valis only @ dtt_start_out
	.shift_h (x_shft_r2), // input[6:0] signed		.shift_h (x_shft_r4), // input[6:0] signed
	.shift_v (y_shft_r2), // input[6:0] signed		.shift_v (y_shft_r4), // input[6:0] signed
	.fd_din (dtt_rd_data), // input[24:0] signed. Expected latency = 3 from start		.fd_din (dtt_rd_data), // input[24:0] signed. Expected latency = 3 from start
	.fd_out (dout), // output[24:0] reg signed		.fd_out (dout), // output[24:0] reg signed
	.pre_first_out (pre_first_out), // output reg		.pre_first_out (pre_first_out), // output reg

dsp/mclt_test_01.tf

+11 −4

Original line number	Original line	Diff line number	Diff line
	@@ -95,12 +95,14 @@ module mclt_test_01 ();

	reg [DTT_IN_WIDTH - 1:0] java_dtt_in0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task		reg [DTT_IN_WIDTH - 1:0] java_dtt_in0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task

	reg [WND_WIDTH - 1:0] tiles_wnd[0:1023];		reg [WND_WIDTH - 1:0] tiles_wnd[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
	reg [DTT_IN_WIDTH - 1:0] java_dtt_in[0:1023];		reg [DTT_IN_WIDTH - 1:0] java_dtt_in[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task

	reg [DTT_IN_WIDTH - 1:0] java_dtt_out0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task		reg [DTT_IN_WIDTH - 1:0] java_dtt_out0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
	reg [DTT_IN_WIDTH - 1:0] java_dtt_out[0:1023];		reg [DTT_IN_WIDTH - 1:0] java_dtt_out[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task

			reg [DTT_IN_WIDTH - 1:0] java_dtt_rot0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
			reg [DTT_IN_WIDTH - 1:0] java_dtt_rot[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
	integer i, n, n_out;		integer i, n, n_out;
	initial begin		initial begin
	$readmemh("input_data/clt_wnd_signs.dat", java_wnd_signs);		$readmemh("input_data/clt_wnd_signs.dat", java_wnd_signs);
	@@ -129,6 +131,10 @@ module mclt_test_01 ();
	java_dtt_out['h000 + i] = java_dtt_out0[i];		java_dtt_out['h000 + i] = java_dtt_out0[i];
	end		end

			$readmemh("input_data/clt_dtt_rot_00_2_x1489_y951.dat",java_dtt_rot0);
			for (i=0; i<256; i=i+1) begin
			java_dtt_rot['h000 + i] = java_dtt_rot0[i];
			end

	$readmemh("input_data/tile_02.dat",tile_shift);		$readmemh("input_data/tile_02.dat",tile_shift);
	shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0];		shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0];
	@@ -360,7 +366,8 @@ module mclt_test_01 ();

	integer n6, cntr6, diff6, diff6a; // SuppressThisWarning VEditor : assigned in $readmem() system task		integer n6, cntr6, diff6, diff6a; // SuppressThisWarning VEditor : assigned in $readmem() system task
	wire [DTT_IN_WIDTH-1:0] data_dtt_out = mclt16x16_i.dtt_rd_data;		wire [DTT_IN_WIDTH-1:0] data_dtt_out = mclt16x16_i.dtt_rd_data;
	wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[1:0],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];		// wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[1:0],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];
			wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[0],cntr6[1],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];
	initial begin		initial begin
	while (RST) @(negedge CLK);		while (RST) @(negedge CLK);
	for (n6 = 0; n6 < 4; n6 = n6+1) begin		for (n6 = 0; n6 < 4; n6 = n6+1) begin

dsp/phase_rotator.v

+33 −26

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