Loading README.md 0 → 100644 +8 −0 Original line number Diff line number Diff line eddr3 ===== ddr3 subproject for Elphel 393 camera This subproject is started to create a DDR3 memory controller for Elphel camera that does not depend on any non-documented features of Xilinx Zynq and can be simulated by Free Software tools (Icarus Verilog + GTKWave) without use of any encrypted modules. Everything in plain Verilog and constraints. Loading
README.md 0 → 100644 +8 −0 Original line number Diff line number Diff line eddr3 ===== ddr3 subproject for Elphel 393 camera This subproject is started to create a DDR3 memory controller for Elphel camera that does not depend on any non-documented features of Xilinx Zynq and can be simulated by Free Software tools (Icarus Verilog + GTKWave) without use of any encrypted modules. Everything in plain Verilog and constraints.
