simulating cmprs_afi_mux (cd341af8) · Commits · Elphel / x393

axi/cmprs_afi_mux.v

+59 −12

Original line number	Diff line number	Diff line
		@@ -23,11 +23,33 @@
		module cmprs_afi_mux#(
		parameter CMPRS_AFIMUX_ADDR= 'h140, //TODO: assign valid address
		parameter CMPRS_AFIMUX_MASK= 'h7f0,
		parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel)
		parameter CMPRS_AFIMUX_EN= 'h0, // enables (global and per-channel)
		/*
		used 10 bits, in each pair [0] - value, [1] - set (0 - nop). [7:0] - per-channel control, [9:8] - common enable/disable (independent)
		*/
		parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets
		/*
		bits [3:0] - persistent per-channel reset (0 - run, 1 - reset)
		*/
		parameter CMPRS_AFIMUX_MODE= 'h2, // per-channel select - which register to return as status
		/*
		mode == 0 - show EOF pointer, internal
		mode == 1 - show EOF pointer, confirmed
		mode == 2 - show current pointer, internal
		mode == 3 - show current pointer, confirmed
		each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), bit[3] - not used
		*/
		parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7
		/*
		4 consecutive locations, per-channel status control
		*/
		parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf
		/*
		27-bit "chunk" addresses and lengths. 1 chunk = 32 bytes, so 27 bit covers all 2^32 adderss range
		8 .. 11 - per-channel start adddresses,
		12 .. 15 - per-channel buffer lengths (will roll over to start address)
		(0..3 - start addresses, 4..7 - lengths)
		*/

		parameter CMPRS_AFIMUX_STATUS_REG_ADDR= 'h20, //Uses 4 locations TODO: assign valid address
		parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
		@@ -147,6 +169,7 @@ module cmprs_afi_mux#(
		reg [3:0] fifo_flush_d; // fifo_flush* delayed by 1 clk (to detect rising edge
		reg [3:0] eof_stb; // single-cycle pulse after fifo_flush is asserted
		// reg [1:0] w64_cnt; // count 64-bit words in a chunk
		// adjusted counters used for channel arbitration
		reg [35:0] counts_corr0; // registers to hold corrected (decremented currently processed ones if any) fifo count values, MSB - needs flush
		reg [17:0] counts_corr1; // first arbitration level winning values
		reg [8:0] counts_corr2; // second arbitration level winning values
		@@ -166,6 +189,8 @@ module cmprs_afi_mux#(
		reg [3:0] busy; // TODO: adjust number of bits. During continuous run busy is deasseted for 1 clock cycle
		wire done_burst_w; // de-asset busy
		wire pre_busy_w;
		reg first_busy; // cycle after pre_busy_w
		reg [3:0] pend_last; // waiting for last chunk
		reg last_burst_in_frame;
		// reg [1:0] wlen32; // 2 high bits of burst len (LSB are always 2'b11)

		@@ -235,17 +260,30 @@ module cmprs_afi_mux#(
		sa_len_d <= cmd_data[26:0];
		sa_len_wa <= cmd_a[2:0];
		end
		if (cmd_we_en_w) en_mclk <= cmd_data[9:0];
		if (cmd_we_rst_w) rst_mclk <= cmd_data[3:0];
		if (mrst) en_mclk <= 0;
		else if (cmd_we_en_w) en_mclk <= cmd_data[9:0];

		if (mrst) rst_mclk <= ~0;
		else if (cmd_we_rst_w) rst_mclk <= cmd_data[3:0];
		end

		always @ (posedge hclk) begin
		reset_pointers <= (en && !en_d)? 4'hf : (en_rst ? rst_mclk : 4'h0);
		if (en_we && en_mclk[1]) en_chn[0] <= en_mclk[0];
		if (en_we && en_mclk[3]) en_chn[1] <= en_mclk[2];
		if (en_we && en_mclk[5]) en_chn[2] <= en_mclk[4];
		if (en_we && en_mclk[7]) en_chn[3] <= en_mclk[6];
		if (en_we && en_mclk[9]) en <= en_mclk[8];
		reset_pointers <= ((en && !en_d) \|\| hrst)? 4'hf : (en_rst ? rst_mclk : 4'h0);
		if (hrst) en_chn[0] <= 0;
		else if (en_we && en_mclk[1]) en_chn[0] <= en_mclk[0];

		if (hrst) en_chn[1] <= 0;
		else if (en_we && en_mclk[3]) en_chn[1] <= en_mclk[2];

		if (hrst) en_chn[2] <= 0;
		else if (en_we && en_mclk[5]) en_chn[2] <= en_mclk[4];

		if (hrst) en_chn[3] <= 0;
		else if (en_we && en_mclk[7]) en_chn[3] <= en_mclk[6];

		if (hrst) en <= 0;
		else if (en_we && en_mclk[9]) en <= en_mclk[8];

		end


		@@ -323,8 +361,17 @@ module cmprs_afi_mux#(
		//ready_to_start need_to_bother
		//done_burst
		if (!en) busy <= 0;
		else if (pre_busy_w) busy <= {busy[2:0],1'b1};
		else if (done_burst_w) busy <= 0; // {busy[2:0],1'b0};
		// else if (pre_busy_w) busy <= {busy[2:0],1'b1};
		// else if (done_burst_w) busy <= 0; // {busy[2:0],1'b0};
		else busy <= {busy[2:0], pre_busy_w \| (busy[0] & ~done_burst_w)};

		if (!en) first_busy <= 0;
		else first_busy <= pre_busy_w;

		if (!en) pend_last <= 0;
		else pend_last <= eof_stb \| (pend_last & ~({4{first_busy & last_burst_in_frame}} & fifo_ren ));

		//pend_last

		if (!en) wleft <= 0;
		else if (pre_busy_w) wleft <= {(\|counts_corr2[7:2])? 2'b11 : left_to_eof[winner2 * 8 +: 2], 2'b11};
		@@ -346,7 +393,7 @@ module cmprs_afi_mux#(

		if (pre_busy_w) begin
		cur_chn <= winner2;
		last_burst_in_frame <= last_chunk_w[winner2];
		last_burst_in_frame <= last_chunk_w[winner2] && pend_last[winner2];
		end

		wlast <= done_burst_w; // when wleft==4'h1

axi/cmprs_afi_mux_ptr.v

+2 −2

Original line number	Diff line number	Diff line
		@@ -55,7 +55,7 @@ module cmprs_afi_mux_ptr(
		reg [26:0] chunk_ptr_inc; // incremented by 1..4 chunk pointer
		reg [27:0] chunk_ptr_rovr; // incremented chunk pointer, decremented by length (MSB - sign)
		reg en_d; //enable delayed by 1 cycle
		wire [ 2:0] sa_len_ra; // start/len read address
		wire [ 2:0] sa_len_ra; // start/len read address (0..3 - start addresses, 4..7 - lengths)


		assign ptr_resetting = resetting[0];

axi/cmprs_afi_mux_status.v

+3 −3

Original line number	Diff line number	Diff line
		@@ -48,8 +48,8 @@ module cmprs_afi_mux_status #(
		output reg [3:0] chunk_ptr_ra, // full pointer address - {eof,wresp,chn[1:0]}
		input [CMPRS_AFIMUX_WIDTH-1:0] chunk_ptr_rd // pointer data
		);
		localparam MODE_IDTH = 15;
		reg [MODE_IDTH-1:0] mode_data_mclk; // some bits unused
		localparam MODE_WIDTH = 15;
		reg [MODE_WIDTH-1:0] mode_data_mclk; // some bits unused
		wire mode_we_hclk;
		reg [7:0] mode_hclk;
		reg [1:0] index;
		@@ -69,7 +69,7 @@ module cmprs_afi_mux_status #(

		assign stb_w = en && (cntr==0);
		always @ (posedge mclk) begin
		if (mode_we) mode_data_mclk <= cmd_data[MODE_IDTH-1:0];
		if (mode_we) mode_data_mclk <= cmd_data[MODE_WIDTH-1:0];
		end

		always @ (posedge hclk) begin

simulation_modules/simul_axi_hp_wr.v

+5 −5

Original line number	Diff line number	Diff line
		@@ -232,26 +232,26 @@ Alex
		if (start_write_burst_w) begin
		if (awid_out != wid_out) begin
		$display ("%m: at time %t ERROR: awid=%h, awid=%h",$time,awid_out,wid_out);
		$stop;
		// $stop;
		end

		if (awsize_out != 2'h3) begin
		$display ("%m: at time %t ERROR: awsize_out=%h, currently only 'h3 (8 bytes) is valid",$time,awsize_out);
		$stop;
		// $stop;
		end
		end
		if (awvalid && awready) begin
		if (((awlock ^ VALID_AWLOCK) & VALID_AWLOCK_MASK) != 0) begin
		$display ("%m: at time %t ERROR: awlock = %h, valid %h with mask %h",$time, awlock, VALID_AWLOCK, VALID_AWLOCK_MASK);
		$stop;
		// $stop;
		end
		if (((awcache ^ VALID_AWCACHE) & VALID_AWCACHE_MASK) != 0) begin
		$display ("%m: at time %t ERROR: awcache = %h, valid %h with mask %h",$time, awcache, VALID_AWCACHE, VALID_AWCACHE_MASK);
		$stop;
		// $stop;
		end
		if (((awprot ^ VALID_AWPROT) & VALID_AWPROT_MASK) != 0) begin
		$display ("%m: at time %t ERROR: awprot = %h, valid %h with mask %h",$time, awprot, VALID_AWPROT, VALID_AWPROT_MASK);
		$stop;
		// $stop;
		end
		end
		end

x393_testbench02.tf

+247 −5

Original line number	Diff line number	Diff line
		@@ -274,12 +274,29 @@ assign #10 gpio_pins[9] = gpio_pins[8];

		assign HCLK = x393_i.ps7_i.SAXIHP0ACLK; // shortcut name

		// afi loopback
		wire [31:0] afi1_sim_wr_address; // output[31:0] SuppressThisWarning VEditor - not used - just view
		wire [ 5:0] afi1_sim_wid; // output[5:0] SuppressThisWarning VEditor - not used - just view
		wire afi1_sim_wr_valid; // output
		wire afi1_sim_wr_ready; // input
		// reg afi1_sim_wr_ready; // input
		wire [63:0] afi1_sim_wr_data; // output[63:0] SuppressThisWarning VEditor - not used - just view
		wire [ 7:0] afi1_sim_wr_stb; // output[7:0] SuppressThisWarning VEditor - not used - just view
		wire [ 3:0] afi1_sim_bresp_latency; // input[3:0]
		// reg [ 3:0] afi1_sim_bresp_latency; // input[3:0]
		wire [ 2:0] afi1_sim_wr_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
		wire [ 3:0] afi1_sim_wr_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view


		// afi loopback (membridge)
		assign #1 afi_sim_rd_data= afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1, 2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
		assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
		assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
		assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
		assign #1 afi_sim_bresp_latency=4'h5;
		// afi1 (compressor) loopback
		assign #1 afi1_sim_wr_ready = afi1_sim_wr_valid;
		assign #1 afi1_sim_bresp_latency=4'h5;


		// SAXI_GP0 - histograms to system memory
		wire SAXI_GP0_CLK;
		@@ -304,9 +321,12 @@ assign #10 gpio_pins[9] = gpio_pins[8];
		reg [31:0] PS_REG_ADDR;
		reg PS_REG_WR;
		reg PS_REG_RD;
		reg PS_REG_WR1;
		reg PS_REG_RD1;
		reg [31:0] PS_REG_DIN;
		wire [31:0] PS_REG_DOUT;
		reg [31:0] PS_RDATA; // SuppressThisWarning VEditor - not used - just view
		wire [31:0] PS_REG_DOUT1;
		/*
		reg [31:0] afi_reg_addr;
		reg afi_reg_wr;
		@@ -319,10 +339,15 @@ assign #10 gpio_pins[9] = gpio_pins[8];
		PS_REG_ADDR <= 'bx;
		PS_REG_WR <= 0;
		PS_REG_RD <= 0;
		PS_REG_WR1 <= 0;
		PS_REG_RD1 <= 0;
		PS_REG_DIN <= 'bx;
		PS_RDATA <= 'bx;
		end
		always @ (posedge HCLK) if (PS_REG_RD) PS_RDATA <= PS_REG_DOUT;
		always @ (posedge HCLK) begin
		if (PS_REG_RD) PS_RDATA <= PS_REG_DOUT;
		else if (PS_REG_RD1) PS_RDATA <= PS_REG_DOUT1;
		end

		reg [639:0] TEST_TITLE;
		// Simulation signals
		@@ -1522,6 +1547,52 @@ simul_axi_hp_wr #(
		.reg_din (PS_REG_DIN), // input[31:0]
		.reg_dout (PS_REG_DOUT) // output[31:0]
		);
		// afi1 - from compressor
		simul_axi_hp_wr #(
		.HP_PORT(1)
		) simul_axi_hp1_wr_i (
		.rst (RST), // input
		.aclk (x393_i.ps7_i.SAXIHP1ACLK), // input
		.aresetn (), // output
		.awaddr (x393_i.ps7_i.SAXIHP1AWADDR), // input[31:0]
		.awvalid (x393_i.ps7_i.SAXIHP1AWVALID), // input
		.awready (x393_i.ps7_i.SAXIHP1AWREADY), // output
		.awid (x393_i.ps7_i.SAXIHP1AWID), // input[5:0]
		.awlock (x393_i.ps7_i.SAXIHP1AWLOCK), // input[1:0]
		.awcache (x393_i.ps7_i.SAXIHP1AWCACHE), // input[3:0]
		.awprot (x393_i.ps7_i.SAXIHP1AWPROT), // input[2:0]
		.awlen (x393_i.ps7_i.SAXIHP1AWLEN), // input[3:0]
		.awsize (x393_i.ps7_i.SAXIHP1AWSIZE), // input[2:0]
		.awburst (x393_i.ps7_i.SAXIHP1AWBURST), // input[1:0]
		.awqos (x393_i.ps7_i.SAXIHP1AWQOS), // input[3:0]
		.wdata (x393_i.ps7_i.SAXIHP1WDATA), // input[63:0]
		.wvalid (x393_i.ps7_i.SAXIHP1WVALID), // input
		.wready (x393_i.ps7_i.SAXIHP1WREADY), // output
		.wid (x393_i.ps7_i.SAXIHP1WID), // input[5:0]
		.wlast (x393_i.ps7_i.SAXIHP1WLAST), // input
		.wstrb (x393_i.ps7_i.SAXIHP1WSTRB), // input[7:0]
		.bvalid (x393_i.ps7_i.SAXIHP1BVALID), // output
		.bready (x393_i.ps7_i.SAXIHP1BREADY), // input
		.bid (x393_i.ps7_i.SAXIHP1BID), // output[5:0]
		.bresp (x393_i.ps7_i.SAXIHP1BRESP), // output[1:0]
		.wcount (x393_i.ps7_i.SAXIHP1WCOUNT), // output[7:0]
		.wacount (x393_i.ps7_i.SAXIHP1WACOUNT), // output[5:0]
		.wrissuecap1en (x393_i.ps7_i.SAXIHP1WRISSUECAP1EN), // input
		.sim_wr_address (afi1_sim_wr_address), // output[31:0]
		.sim_wid (afi1_sim_wid), // output[5:0]
		.sim_wr_valid (afi1_sim_wr_valid), // output
		.sim_wr_ready (afi1_sim_wr_ready), // input
		.sim_wr_data (afi1_sim_wr_data), // output[63:0]
		.sim_wr_stb (afi1_sim_wr_stb), // output[7:0]
		.sim_bresp_latency(afi1_sim_bresp_latency), // input[3:0]
		.sim_wr_cap (afi1_sim_wr_cap), // output[2:0]
		.sim_wr_qos (afi1_sim_wr_qos), // output[3:0]
		.reg_addr (PS_REG_ADDR), // input[31:0]
		.reg_wr (PS_REG_WR1), // input
		.reg_rd (PS_REG_RD1), // input
		.reg_din (PS_REG_DIN), // input[31:0]
		.reg_dout (PS_REG_DOUT1) // output[31:0]
		);

		// SAXI_GP0 - histograms to system memory
		simul_saxi_gp_wr simul_saxi_gp0_wr_i (
		@@ -1803,6 +1874,10 @@ task setup_sensor_channel;
		reg [31:0] last_buf_frame;
		reg [31:0] camsync_delay;
		reg [ 3:0] sensor_mask;

		reg [26:0] afi_cmprs0_sa;
		reg [26:0] afi_cmprs0_len;

		// Setting up a single sensor channel 0, sunchannel 0
		//
		begin
		@@ -1818,6 +1893,9 @@ task setup_sensor_channel;
		external_timestamp = EXTERNAL_TIMESTAMP;
		last_buf_frame = LAST_BUF_FRAME;
		sensor_mask = 1 << num_sensor;

		afi_cmprs0_sa = 'h10000000 >> 5;
		afi_cmprs0_len = 'h10000 >> 5;
		// program_curves(
		// num_sensor, // input [1:0] num_sensor;
		// 0); // input [1:0] sub_channel;
		@@ -2086,6 +2164,59 @@ task write_cmd_frame_sequencer;
		// just temporarily - enable channel immediately
		enable_memcntrl_en_dis(4'hc + {2'b0,num_sensor}, 1);

		TEST_TITLE = "PROGRAM AFI_MUX";
		$display("===================== TEST_%s =========================",TEST_TITLE);

		afi_mux_program_status (
		0, // input [0:0] port_afi; // number of AFI port (0 - afi 1, 1 - afi2) // configuration controlled by the code. currently
		// both AFI are used: ch0 - cmprs_afi_mux_1.0, ch1 - cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_2.0, ch3 - cmprs_afi_mux_2
		// May be chenged to ch0 - cmprs_afi_mux_1.0, ch1 -cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_1.2, ch3 - cmprs_afi_mux_1.3
		num_sensor, // input [1:0] chn_afi;
		3, // input [1:0] mode;
		0); // input [5:0] seq_num;
		// reset all channels
		afi_mux_reset(
		0, // input [0:0] port_afi;
		4'hf); // input [3:0] rst_chn;
		// release resets
		afi_mux_reset(
		0, // input [0:0] port_afi;
		0); // input [3:0] rst_chn;

		// set report mode (pointer type) - per status
		afi_mux_mode_chn (
		0, //input [0:0] port_afi; // number of AFI port.3
		num_sensor, // input [1:0] chn; // channel number to set mode for
		/*
		mode == 0 - show EOF pointer, internal
		mode == 1 - show EOF pointer, confirmed
		mode == 2 - show current pointer, internal
		mode == 3 - show current pointer, confirmed
		each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), bit[3] - not used
		*/
		0); // input [1:0] mode;

		afi_mux_chn_start_length (
		0, // input [0:0] port_afi; // number of AFI port
		num_sensor, // input [ 1:0] chn; // channel number to set mode for
		afi_cmprs0_sa, // input [26:0] sa; // start address in 32-byte chunks
		afi_cmprs0_len); // input [26:0] length; // channel buffer length in 32-byte chunks

		// enable channel 0 and the whole afi_mux module

		afi_mux_enable_chn (
		0, // input [0:0] port_afi; // number of AFI port
		num_sensor, // input [1:0] en_chn; // channel number to enable/disable;
		1); // input en;

		afi_mux_enable (
		0, // input [0:0] port_afi; // number of AFI port
		1); // input en;



		TEST_TITLE = "GAMMA_CTL";
		$display("===================== TEST_%s =========================",TEST_TITLE);
		set_sensor_gamma_ctl (// doing last to enable sesnor data when everything else is set up
		@@ -2104,7 +2235,6 @@ task write_cmd_frame_sequencer;
		// just temporarily - enable channel immediately
		// enable_memcntrl_en_dis(4'hc + {2'b0,num_sensor}, 1);


		end
		endtask

		@@ -2332,7 +2462,7 @@ task program_status_sensor_io;
		input [5:0] seq_num;
		begin
		program_status (SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC + SENSIO_RADDR,
		SENSI2C_STATUS,
		SENSIO_STATUS,
		mode,
		seq_num);
		end
		@@ -3185,6 +3315,118 @@ function [31 : 0] func_compressor_color_saturation;
		end
		endfunction

		// axi_hp channels for the compressed image data
		task afi_mux_program_status;
		input [0:0] port_afi; // number of AFI port (0 - afi 1, 1 - afi2) // configuration controlled by the code. currently
		// both AFI are used: ch0 - cmprs_afi_mux_1.0, ch1 - cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_2.0, ch3 - cmprs_afi_mux_2
		// May be chenged to ch0 - cmprs_afi_mux_1.0, ch1 -cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_1.2, ch3 - cmprs_afi_mux_1.3
		input [1:0] chn_afi;
		input [1:0] mode;
		input [5:0] seq_num;
		reg [29:0] reg_addr;
		begin
		reg_addr = CMPRS_GROUP_ADDR + (port_afi ? CMPRS_AFIMUX_RADDR1 : CMPRS_AFIMUX_RADDR0) + chn_afi;
		program_status (reg_addr,
		CMPRS_AFIMUX_STATUS_CNTRL,
		mode,
		seq_num);
		end
		endtask

		task afi_mux_reset;
		input [0:0] port_afi; // number of AFI port (0 - afi 1, 1 - afi2) // configuration controlled by the code. currently
		// both AFI are used: ch0 - cmprs_afi_mux_1.0, ch1 - cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_2.0, ch3 - cmprs_afi_mux_2
		// May be chenged to ch0 - cmprs_afi_mux_1.0, ch1 -cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_1.2, ch3 - cmprs_afi_mux_1.3
		input [3:0] rst_chn;
		reg [29:0] reg_addr;
		begin
		reg_addr = CMPRS_GROUP_ADDR + (port_afi ? CMPRS_AFIMUX_RADDR1 : CMPRS_AFIMUX_RADDR0) + CMPRS_AFIMUX_RST;
		write_contol_register(reg_addr, {28'b0,rst_chn});
		end
		endtask

		task afi_mux_enable_chn;
		input [0:0] port_afi; // number of AFI port (0 - afi 1, 1 - afi2) // configuration controlled by the code. currently
		// both AFI are used: ch0 - cmprs_afi_mux_1.0, ch1 - cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_2.0, ch3 - cmprs_afi_mux_2
		// May be chenged to ch0 - cmprs_afi_mux_1.0, ch1 -cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_1.2, ch3 - cmprs_afi_mux_1.3
		input [1:0] en_chn; // channel number to enable/disable;
		input en;
		reg [29:0] reg_addr;
		reg [31:0] data;
		begin
		reg_addr = CMPRS_GROUP_ADDR + (port_afi ? CMPRS_AFIMUX_RADDR1 : CMPRS_AFIMUX_RADDR0) + CMPRS_AFIMUX_EN;
		data = 0;
		data[2 * en_chn +: 2] = {1'b1,en};
		write_contol_register(reg_addr,data);
		end
		endtask

		task afi_mux_enable;
		input [0:0] port_afi; // number of AFI port (0 - afi 1, 1 - afi2) // configuration controlled by the code. currently
		// both AFI are used: ch0 - cmprs_afi_mux_1.0, ch1 - cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_2.0, ch3 - cmprs_afi_mux_2
		// May be chenged to ch0 - cmprs_afi_mux_1.0, ch1 -cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_1.2, ch3 - cmprs_afi_mux_1.3
		input en;
		reg [29:0] reg_addr;
		reg [31:0] data;
		begin
		reg_addr = CMPRS_GROUP_ADDR + (port_afi ? CMPRS_AFIMUX_RADDR1 : CMPRS_AFIMUX_RADDR0) + CMPRS_AFIMUX_EN;
		data = 0;
		data[2 * 4 +: 2] = {1'b1,en};
		write_contol_register(reg_addr,data);
		end
		endtask

		task afi_mux_mode_chn;
		input [0:0] port_afi; // number of AFI port (0 - afi 1, 1 - afi2) // configuration controlled by the code. currently
		// both AFI are used: ch0 - cmprs_afi_mux_1.0, ch1 - cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_2.0, ch3 - cmprs_afi_mux_2
		// May be chenged to ch0 - cmprs_afi_mux_1.0, ch1 -cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_1.2, ch3 - cmprs_afi_mux_1.3
		input [1:0] mode;
		input [1:0] chn; // channel number to set mode for
		reg [29:0] reg_addr;
		/*
		mode == 0 - show EOF pointer, internal
		mode == 1 - show EOF pointer, confirmed
		mode == 2 - show current pointer, internal
		mode == 3 - show current pointer, confirmed
		each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), bit[3] - not used
		*/

		reg [31:0] data;
		begin
		reg_addr = CMPRS_GROUP_ADDR + (port_afi ? CMPRS_AFIMUX_RADDR1 : CMPRS_AFIMUX_RADDR0) + CMPRS_AFIMUX_MODE;
		data = 0;
		data[4 * chn +: 4] = {2'b01, mode};
		write_contol_register(reg_addr,data);
		end
		endtask

		task afi_mux_chn_start_length;
		input [0:0] port_afi; // number of AFI port (0 - afi 1, 1 - afi2) // configuration controlled by the code. currently
		// both AFI are used: ch0 - cmprs_afi_mux_1.0, ch1 - cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_2.0, ch3 - cmprs_afi_mux_2
		// May be chenged to ch0 - cmprs_afi_mux_1.0, ch1 -cmprs_afi_mux_1.1,
		// ch2 - cmprs_afi_mux_1.2, ch3 - cmprs_afi_mux_1.3
		input [ 1:0] chn; // channel number to set mode for
		input [26:0] sa; // start address in 32-byte chunks
		input [26:0] length; // channel buffer length in 32-byte chunks

		reg [29:0] reg_addr;
		begin
		reg_addr = CMPRS_GROUP_ADDR + (port_afi ? CMPRS_AFIMUX_RADDR1 : CMPRS_AFIMUX_RADDR0) + CMPRS_AFIMUX_SA_LEN + chn;
		write_contol_register(reg_addr , {5'b0, sa});
		write_contol_register(reg_addr+4, {5'b0, length});
		end
		endtask

		`include "includes/tasks_tests_memory.vh" // SuppressThisWarning VEditor - may be unused
		`include "includes/x393_tasks_afi.vh" // SuppressThisWarning VEditor - may be unused

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