Commit ca6e4334 authored by Andrey Filippov's avatar Andrey Filippov
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typo

parent abaada40
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@@ -12,5 +12,5 @@ Run ./INIT_PROJECT in the top directory to copy initial .project and .pydevproje
Simulation of this project requires some files from the Xilinx proprietary _unisims_ library (list of dependencies
Simulation of this project requires some files from the Xilinx proprietary _unisims_ library (list of dependencies
is in this [blog post](http://blog.elphel.com/2016/03/free-fpga-reimplement-the-primitives-models/)).
is in this [blog post](http://blog.elphel.com/2016/03/free-fpga-reimplement-the-primitives-models/)).
[VDT plugin](https://github.com/Elphel/vdt-plugin) README file describes steps needed after installation of Xilinx software
[VDT plugin](https://github.com/Elphel/vdt-plugin) README file describes steps needed after installation of Xilinx software
(unisims library is not distributed separatly). 
(unisims library is not distributed separately).