MCLT window generators - with(128:1)/without(4:1) multiplier, ROM data

#!/usr/bin/env python

# -*- coding: utf-8 -*-

from __future__ import print_function

from __future__ import division

# Copyright (C) 2017, Elphel.inc.

# Helper module create AHCI registers type/default data

# This program is free software: you can redistribute it and/or modify

# it under the terms of the GNU General Public License as published by

# the Free Software Foundation, either version 3 of the License, or

# (at your option) any later version.

#

# This program is distributed in the hope that it will be useful,

# but WITHOUT ANY WARRANTY; without even the implied warranty of

# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

# GNU General Public License for more details.

#

# You should have received a copy of the GNU General Public License

# along with this program.  If not, see <http://www.gnu.org/licenses/>.

#

'''

Calculate ROM for half-sine 1d window for lapped transform.

Created for 8x8 (16x16 overlapped) with 128:1 super resolution, so instead of :

   sin(1*pi/32), sin(3*pi/32),..., sin(15*pi/32) for each of the rows and columns

there are:   

   sin(1*pi/2048), sin(2*pi/2048),..., sin(32*pi/2048) for each of the rows and columns

that requires 1024x18bits ROM. no need to have sin(0*pi/2048) as it is 0

'''

__author__ = "Andrey Filippov"

__copyright__ = "Copyright 2017, Elphel, Inc."

__license__ = "GPL"

__version__ = "3.0+"

__maintainer__ = "Andrey Filippov"

__email__ = "andrey@elphel.com"

__status__ = "Development"

import sys

import math

import os

import datetime

mclt_wnd_rom_path=  '../includes/mclt_wnd_mul.vh'

def create_with_parity (init_data,   # numeric data (may be less than full array

                        num_bits,    # number of bits in item, valid:  1,2,4,8,9,16,18,32,36,64,72

                        full_bram):  # true if ramb36, false - ramb18

    d = num_bits

    num_bits8 = 1;

    while d > 1:

        d >>= 1

        num_bits8 <<= 1

    bsize = (0x4000,0x8000)[full_bram]

    bdata = [0  for i in range(bsize)]

    sb = 0

    for item in init_data:

        for bt in range (num_bits8):

            bdata[sb+bt] = (item >> bt) & 1;

        sb += num_bits8

    data = []

    for i in range (len(bdata)//256):

        d = 0;

        for b in range(255, -1,-1):

            d = (d<<1) +  bdata[256*i+b]

        data.append(d)

    data_p = []

    num_bits_p = num_bits8 >> 3

    sb = 0

    print ("num_bits=",num_bits)

    print ("num_bits8=",num_bits8)

    print ("num_bits_p=",num_bits_p)

    if num_bits_p:    

        pbsize = bsize >> 3    

        pbdata = [0  for i in range(pbsize)]

        for item in init_data:

            for bt in range (num_bits_p):

                pbdata[sb+bt] = (item >> (bt+num_bits8)) & 1;

            sb += num_bits_p

        for i in range (len(pbdata)//256):

            d = 0;

            for b in range(255, -1,-1):

                d = (d<<1) +  pbdata[256*i+b]

            data_p.append(d)

    return {'data':data,'data_p':data_p}

def print_params(data,

                 out_file_name,

                 comment=""): # text to add to the file header

    with open(out_file_name,"w") as out_file:

        print ("// Created with "+sys.argv[0], file=out_file)

        if comment:

            print (comment, file=out_file)

        for i, v in enumerate(data['data']):

            if v:

                print (", .INIT_%02X (256'h%064X)"%(i,v), file=out_file)

    #    if (include_parity):

        for i, v in enumerate(data['data_p']):

            if v:

                print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)

def create_wnd_1d (N=1024, bits=18): # N=32, bits=18, all data is positive

    rom = []

    sin = []

    for i in range(N):

        rom.append(int(round(math.sin(math.pi*(i+1)/(2*N))* ((1 << bits) - 1)))) # loosing 1 count

    return rom                        

print_params(

    create_with_parity(create_wnd_1d (N=1024, bits=18), 18, False),

    os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path)),

    "// MCLT 1d 16 count window with 128:1 super resolution data")

print ("MCLT 1d 16 count window with 128:1 super resolution data is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path))))

#!/usr/bin/env python

# -*- coding: utf-8 -*-

from __future__ import print_function

from __future__ import division

# Copyright (C) 2017, Elphel.inc.

# Helper module create AHCI registers type/default data

# This program is free software: you can redistribute it and/or modify

# it under the terms of the GNU General Public License as published by

# the Free Software Foundation, either version 3 of the License, or

# (at your option) any later version.

#

# This program is distributed in the hope that it will be useful,

# but WITHOUT ANY WARRANTY; without even the implied warranty of

# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

# GNU General Public License for more details.

#

# You should have received a copy of the GNU General Public License

# along with this program.  If not, see <http://www.gnu.org/licenses/>.

#

'''

Calculate ROM for half-sine 2d window for lapped transform.

Only one quadrant is stored.

created for 8x8 (16x16 overlapped) with 4:1 super resolution, so instead of :

   sin(1*pi/32), sin(3*pi/32),..., sin(15*pi/32) for each of the rows and columns

there are:   

   sin(1*pi/64), sin(2*pi/64),..., sin(32*pi/64) for each of the rows and columns

that requires 32x32x18bits ROM. no need to have sin(0*pi/64) as it is 0

'''

__author__ = "Andrey Filippov"

__copyright__ = "Copyright 2017, Elphel, Inc."

__license__ = "GPL"

__version__ = "3.0+"

__maintainer__ = "Andrey Filippov"

__email__ = "andrey@elphel.com"

__status__ = "Development"

import sys

import math

import os

import datetime

mclt_wnd_rom_path=  '../includes/mclt_wnd_sres4.vh'

def create_with_parity (init_data,   # numeric data (may be less than full array

                        num_bits,    # number of bits in item, valid:  1,2,4,8,9,16,18,32,36,64,72

                        full_bram):  # true if ramb36, false - ramb18

    d = num_bits

    num_bits8 = 1;

    while d > 1:

        d >>= 1

        num_bits8 <<= 1

    bsize = (0x4000,0x8000)[full_bram]

    bdata = [0  for i in range(bsize)]

    sb = 0

    for item in init_data:

        for bt in range (num_bits8):

            bdata[sb+bt] = (item >> bt) & 1;

        sb += num_bits8

    data = []

    for i in range (len(bdata)//256):

        d = 0;

        for b in range(255, -1,-1):

            d = (d<<1) +  bdata[256*i+b]

        data.append(d)

    data_p = []

    num_bits_p = num_bits8 >> 3

    sb = 0

    print ("num_bits=",num_bits)

    print ("num_bits8=",num_bits8)

    print ("num_bits_p=",num_bits_p)

    if num_bits_p:    

        pbsize = bsize >> 3    

        pbdata = [0  for i in range(pbsize)]

        for item in init_data:

            for bt in range (num_bits_p):

                pbdata[sb+bt] = (item >> (bt+num_bits8)) & 1;

            sb += num_bits_p

        for i in range (len(pbdata)//256):

            d = 0;

            for b in range(255, -1,-1):

                d = (d<<1) +  pbdata[256*i+b]

            data_p.append(d)

    return {'data':data,'data_p':data_p}

def print_params(data,

                 out_file_name,

                 comment=""): # text to add to the file header

    with open(out_file_name,"w") as out_file:

        print ("// Created with "+sys.argv[0], file=out_file)

        if comment:

            print (comment, file=out_file)

        for i, v in enumerate(data['data']):

            if v:

                print (", .INIT_%02X (256'h%064X)"%(i,v), file=out_file)

    #    if (include_parity):

        for i, v in enumerate(data['data_p']):

            if v:

                print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)

def create_wnd_2d (N=32, bits=18): # N=32, bits=18, all data is positive

    rom = []

    sin = []

    for i in range(N):

        sin.append(math.sin(math.pi*(i+1)/(2*N)))

    for i in range(N):

        for j in range(N):

            rom.append(int(round(sin[i] * sin[j] * ((1 << bits) - 1)))) # loosing 1 count

    return rom                        

print_params(

    create_with_parity(create_wnd_2d (N=32, bits=18), 18, False),

    os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path)),

    "// MCLT 16x16  window with 4:1 super resolution data")

print ("MCLT 16x16  window with 4:1 super resolution data is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path))))

/*!

 * <b>Module:</b> mclt_wnd_mul

 * @file mclt_wnd_mul.v

 * @date 2017-12-06  

 * @author eyesis

 *     

 * @brief MCLT window with MPY (128:1 superresolution)

 *

 * @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .

 *

 * <b>License </b>

 *

 * mclt_wnd_mul.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 * mclt_wnd_mul.v is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *

 * Additional permission under GNU GPL version 3 section 7:

 * If you modify this Program, or any covered work, by linking or combining it

 * with independent modules provided by the FPGA vendor only (this permission

 * does not extend to any 3-rd party modules, "soft cores" or macros) under

 * different license terms solely for the purpose of generating binary "bitstream"

 * files and/or simulating the code, the copyright holders of this Program give

 * you the right to distribute the covered work without those independent modules

 * as long as the source code for them is available from the FPGA vendor free of

 * charge, and there is no dependence on any encrypted modules for simulating of

 * the combined code. This permission applies to you if the distributed code

 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

`timescale 1ns/1ps

// Latency = 5

module  mclt_wnd_mul#(

    parameter SHIFT_WIDTH =  8,  // bits in shift (1 bit - integer, 7 bits - fractional

    parameter COORD_WIDTH = 10,  // bits in full coordinate 10 for 18K RAM 

    parameter OUT_WIDTH =   18   // bits in window value (positive) 

)(

    input                          clk,   //!< system clock, posedge

    input                          en,    //!< re (both re and ren - just for power)

    input                    [3:0] x_in,  //!< tile pixel X

    input                    [3:0] y_in,  //!< tile pixel Y

    input        [SHIFT_WIDTH-1:0] x_shft,  //!< tile pixel X

    input        [SHIFT_WIDTH-1:0] y_shft,  //!< tile pixel Y

    output       [OUT_WIDTH - 1 : 0] wnd_out            

);

    wire [COORD_WIDTH - 1 : 0] x_full;

    wire [COORD_WIDTH - 1 : 0] y_full;

    wire                       x_zero;

    wire                       y_zero;

    reg                  [1:0] zero; // x_zero | y_zero;

    reg                  [2:0] regen; //

    wire   [OUT_WIDTH - 1 : 0] wnd_out_x;            

    wire   [OUT_WIDTH - 1 : 0] wnd_out_y;            

    reg  [2*OUT_WIDTH - 1 : 0] wnd_out_r;

    assign wnd_out = wnd_out_r[2 * OUT_WIDTH - 1: OUT_WIDTH];

    always @ (posedge clk) begin

        regen <= {regen[1:0],en};

        zero <= {1'b0, x_zero | y_zero};

        wnd_out_r <= wnd_out_x * wnd_out_y;

    end

    mclt_full_shift #(

        .COORD_WIDTH(COORD_WIDTH),

        .SHIFT_WIDTH(SHIFT_WIDTH)

    ) mclt_full_shift_x_i (

        .clk       (clk),    // input

        .coord     (x_in),   // input[3:0] 

        .shift     (x_shft), // input[2:0] signed 

        .coord_out (x_full), // output[4:0] reg 

        .zero      (x_zero) // output reg 

    );

    mclt_full_shift #(

        .COORD_WIDTH(COORD_WIDTH),

        .SHIFT_WIDTH(SHIFT_WIDTH)

    ) mclt_full_shift_y_i (

        .clk       (clk),    // input

        .coord     (y_in),   // input[3:0] 

        .shift     (y_shft), // input[2:0] signed 

        .coord_out (y_full), // output[4:0] reg 

        .zero      (y_zero) // output reg 

    );

     ram18tpr_var_w_var_r #(

        .REGISTERS_A(1),

        .REGISTERS_B(1),

        .LOG2WIDTH_A(4),

        .LOG2WIDTH_B(4)

`ifdef PRELOAD_BRAMS

    `include "mclt_wnd_mul.vh"

`endif

    ) i_wnd_rom (

        .clk_a     (clk),       // input

        .addr_a    (x_full),    // input[9:0] 

        .en_a      (regen[1]),  // input

        .regen_a   (regen[2]),  // input

        .we_a      (1'b0),      // input

        .rrst_a    (1'b0),      // input

        .regrst_a  (zero[1]),   // input

        .data_out_a(wnd_out_x), // output[17:0] 

        .data_in_a (18'b0),     // input[17:0] 

        .clk_b     (clk),       // input

        .addr_b    (y_full),    // input[9:0] 

        .en_b      (regen[1]),  // input

        .regen_b   (regen[2]),  // input

        .we_b      (1'b0),      // input

        .rrst_b    (1'b0),      // input

        .regrst_b  (zero[1]),   // input

        .data_out_b(wnd_out_y), // output[17:0] 

        .data_in_b (18'b0)      // input[17:0] 

    );

endmodule

/*!

 * <b>Module:</b> mclt_wnd_sres4

 * @file mclt_wnd_sres4.v

 * @date 2017-12-06  

 * @author eyesis

 *     

 * @brief MCLT window w/o MPY (4:1 superresolution)

 *

 * @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .

 *

 * <b>License </b>

 *

 * mclt_wnd_sres4.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 * mclt_wnd_sres4.v is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *

 * Additional permission under GNU GPL version 3 section 7:

 * If you modify this Program, or any covered work, by linking or combining it

 * with independent modules provided by the FPGA vendor only (this permission

 * does not extend to any 3-rd party modules, "soft cores" or macros) under

 * different license terms solely for the purpose of generating binary "bitstream"

 * files and/or simulating the code, the copyright holders of this Program give

 * you the right to distribute the covered work without those independent modules

 * as long as the source code for them is available from the FPGA vendor free of

 * charge, and there is no dependence on any encrypted modules for simulating of

 * the combined code. This permission applies to you if the distributed code

 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

`timescale 1ns/1ps

// Latency = 4

module  mclt_wnd_sres4#(

    parameter SHIFT_WIDTH =  3,  // bits in shift (1 bit - integer, 2 bits - fractional

    parameter COORD_WIDTH =  5,  // bits in full coordinate 10/2 for 18K RAM 

    parameter OUT_WIDTH =   18   // bits in window value (positive) 

)(

    input                          clk,   //!< system clock, posedge

    input                          en,    //!< re (both re and ren - just for power)

    input                    [3:0] x_in,  //!< tile pixel X

    input                    [3:0] y_in,  //!< tile pixel Y

    input        [SHIFT_WIDTH-1:0] x_shft,  //!< tile pixel X

    input        [SHIFT_WIDTH-1:0] y_shft,  //!< tile pixel Y

    output     [OUT_WIDTH - 1 : 0] wnd_out            

);

    wire [COORD_WIDTH - 1 : 0] x_full;

    wire [COORD_WIDTH - 1 : 0] y_full;

    wire                       x_zero;

    wire                       y_zero;

    reg                  [1:0] zero; // x_zero | y_zero;

    reg                  [2:0] regen; // 

    always @ (posedge clk) begin

        regen <= {regen[1:0],en};

        zero <= {1'b0, x_zero | y_zero};

    end

    mclt_full_shift #(

        .COORD_WIDTH(COORD_WIDTH),

        .SHIFT_WIDTH(SHIFT_WIDTH)

    ) mclt_full_shift_x_i (

        .clk       (clk),    // input

        .coord     (x_in),   // input[3:0] 

        .shift     (x_shft), // input[2:0] signed 

        .coord_out (x_full), // output[4:0] reg 

        .zero      (x_zero) // output reg 

    );

    mclt_full_shift #(

        .COORD_WIDTH(COORD_WIDTH),

        .SHIFT_WIDTH(SHIFT_WIDTH)

    ) mclt_full_shift_y_i (

        .clk       (clk),    // input

        .coord     (y_in),   // input[3:0] 

        .shift     (y_shft), // input[2:0] signed 

        .coord_out (y_full), // output[4:0] reg 

        .zero      (y_zero) // output reg 

    );

    ram18pr_var_w_var_r #(

        .REGISTERS(1),

        .LOG2WIDTH_WR(4),

        .LOG2WIDTH_RD(4),

        .DUMMY(0)

`ifdef PRELOAD_BRAMS

    `include "mclt_wnd_sres4.vh"

`endif

    ) i_wnd_rom (

        .rclk     (clk),             // input

        .raddr    ({y_full,x_full}), // input[9:0] 

        .ren      (regen[1]),        // input

        .regen    (regen[2]),        // input

        .rrst     (1'b0),            // input

        .regrst   (zero[1]),         // input

        .data_out (wnd_out),         // output[17:0] 

        .wclk     (1'b0),            // input

        .waddr    (10'b0),           // input[9:0] 

        .we       (1'b0),            // input

        .web      (4'hf),            // input[3:0] 

        .data_in  (18'b0)            // input[17:0] 

    );

endmodule

// Created with ./create_wnd_mul_rom.py

// MCLT 1d 16 count window with 128:1 super resolution data

, .INIT_00 (256'h1921178F15FD146B12D911470FB50E230C910AFF096D07DB064804B603240192)

, .INIT_01 (256'h323F30AD2F1B2D8A2BF82A6628D4274325B1241F228D20FB1F691DD71C451AB3)

, .INIT_02 (256'h4B5449C3483246A14510437F41ED405C3ECB3D393BA83A17388536F4356233D0)

, .INIT_03 (256'h645F62CE613E5FAE5E1D5C8D5AFC596C57DB564A54BA5329519850074E764CE5)

, .INIT_04 (256'h7D597BCA7A3B78AB771C758D73FD726E70DE6F4E6DBF6C2F6A9F690F677F65EF)

, .INIT_05 (256'h964094B39325919790098E7A8CEC8B5E89CF884186B285248395820680777EE8)

, .INIT_06 (256'hAF10AD84ABF8AA6BA8DFA752A5C5A439A2ACA11E9F919E049C779AE9995C97CE)

, .INIT_07 (256'hC7C6C63BC4B1C326C19BC010BE85BCFABB6FB9E3B858B6CCB540B3B5B229B09D)

, .INIT_08 (256'hE05CDED3DD4BDBC2DA39D8B0D727D59ED415D28BD102CF78CDEECC64CADAC950)

, .INIT_09 (256'hF8D0F749F5C3F43DF2B6F12FEFA8EE21EC9AEB13E98CE804E67CE4F4E36CE1E4)

, .INIT_0A (256'h111D0F990E150C910B0D09890805068004FB037601F1006CFEE7FD61FBDBFA56)

, .INIT_0B (256'h294027BF263E24BD233B21BA20381EB61D341BB21A2F18AD172A15A7142412A0)

, .INIT_0C (256'h41353FB83E393CBB3B3D39BE383F36C0354133C1324230C22F422DC22C412AC1)

, .INIT_0D (256'h58F9577F56045489530D519250164E9A4D1E4BA14A2548A8472B45AE443142B3)

, .INIT_0E (256'h70886F116D996C216AA9693167B9664064C8634E61D5605C5EE25D685BEE5A74)

, .INIT_0F (256'h87DE866A84F68382820E80997F247DAF7C3A7AC5794F77D9766374EC737671FF)

, .INIT_10 (256'h9EF79D879C179AA7993797C6965594E493729201908F8F1C8DAA8C378AC48951)

, .INIT_11 (256'hB5D1B465B2F9B18DB020AEB4AD47ABDAAA6CA8FEA790A622A4B4A345A1D6A067)

, .INIT_12 (256'hCC66CAFFC998C830C6C8C55FC3F6C28DC124BFBBBE51BCE7BB7DBA12B8A7B73C)

, .INIT_13 (256'hE2B5E153DFEFDE8CDD28DBC5DA60D8FCD797D632D4CDD367D201D09BCF34CDCE)

, .INIT_14 (256'hF8BAF75CF5FDF49FF340F1E1F081EF21EDC1EC61EB00E99FE83EE6DCE57AE418)

, .INIT_15 (256'h0E700D170BBE0A64090A07B0065504FA039F024300E8FF8BFE2FFCD2FB75FA18)

, .INIT_16 (256'h23D62282212E1FD91E841D2F1BDA1A84192E17D71680152913D2127A11220FC9)

, .INIT_17 (256'h38E73798364934FA33AB325B310B2FBA2E692D182BC62A74292227D0267D2529)

, .INIT_18 (256'h4DA04C574B0E49C4487A473045E5449A434F420340B73F6A3E1E3CD03B833A35)

, .INIT_19 (256'h61FE60BB5F785E345CF05BAB5A66592157DB5695554E540752C0517950314EE9)

, .INIT_1A (256'h75FF74C17384724671086FC96E8A6D4A6C0A6ACA698A6849670765C664846341)

, .INIT_1B (256'h899E8867872F85F784BF8387824E81147FDB7EA07D667C2B7AF079B47878773B)

, .INIT_1C (256'h9CD99BA89A779945981496E195AF947B9348921490E08FAB8E768D418C0B8AD4)

, .INIT_1D (256'hAFACAE82AD58AC2DAB01A9D6A8A9A77DA650A522A3F4A2C6A197A0689F399E09)

, .INIT_1E (256'hC216C0F3BFCFBEABBD86BC61BB3BBA15B8EFB7C8B6A1B579B451B328B200B0D6)

, .INIT_1F (256'hD413D2F7D1DAD0BCCF9ECE80CD61CC42CB22CA02C8E2C7C1C6A0C57EC45CC339)

, .INIT_20 (256'hE5A0E48BE375E25EE148E030DF19DE00DCE8DBCFDAB5D99BD881D766D64BD52F)

, .INIT_21 (256'hF6BBF5ADF49EF38FF27FF16FF05FEF4EEE3CED2AEC18EB05E9F2E8DEE7CAE6B5)

, .INIT_22 (256'h0761065A0553044B0343023A01310027FF1DFE12FD07FBFCFAF0F9E3F8D6F7C9)

, .INIT_23 (256'h178F169015901490138F128E118C108A0F870E840D810C7C0B780A73096D0867)

, .INIT_24 (256'h2743264C2554245B23622268216E20741F791E7D1D811C851B881A8A198D188E)

, .INIT_25 (256'h367B358B349B33AA32B931C730D52FE22EEF2DFB2D072C122B1D2A282931283B)

, .INIT_26 (256'h4534444C4364427B419240A83FBE3ED33DE83CFC3C103B233A3539483859376B)

, .INIT_27 (256'h536C528C51AC50CB4FEA4F094E264D444C604B7D4A9849B448CE47E84702461B)

, .INIT_28 (256'h612060495F715E995DC05CE65C0C5B325A57597B589F57C356E55608552A544B)

, .INIT_29 (256'h6E506D816CB16BE16B106A3F696E689B67C966F66622654E647963A462CE61F7)

, .INIT_2A (256'h7AF77A31796A78A277DA77117648757F74B473EA731E7253718670B96FEC6F1E)

, .INIT_2B (256'h87158658859984DA841B835B829A81D9811880557F937ED07E0C7D477C837BBD)

, .INIT_2C (256'h92A891F3913E90888FD18F1A8E628DA98CF18C378B7D8AC28A07894C889087D3)

, .INIT_2D (256'h9DAE9D029C559BA89AFA9A4C999D98ED983D978D96DB962A957794C49411935D)

, .INIT_2E (256'hA826A782A6DFA63AA595A4F0A44AA3A3A2FCA254A1ACA103A05A9FB09F059E5A)

, .INIT_2F (256'hB20DB172B0D8B03CAFA0AF04AE67ADC9AD2BAC8DABEDAB4DAAADAA0CA96AA8C8)

, .INIT_30 (256'hBB62BAD1BA3FB9ADB91AB887B7F3B75EB6C9B634B59EB507B470B3D8B33FB2A6)

, .INIT_31 (256'hC423C39BC313C28AC201C177C0ECC061BFD5BF48BEBBBE2EBDA0BD11BC82BBF2)

, .INIT_32 (256'hCC50CBD2CB53CAD3CA53C9D2C951C8CFC84CC7C9C746C6C1C63CC5B7C531C4AA)

, .INIT_33 (256'hD3E7D372D2FDD286D210D198D120D0A8D02FCFB5CF3ACEC0CE44CDC8CD4BCCCE)

, .INIT_34 (256'hDAE7DA7CDA0FD9A3D935D8C7D859D7EAD77AD70AD699D627D5B5D543D4CFD45C)

, .INIT_35 (256'hE14FE0EDE08AE027DFC3DF5FDEFADE94DE2EDDC7DD60DCF8DC8FDC26DBBCDB52)

, .INIT_36 (256'hE71DE6C5E66CE612E5B8E55DE502E4A6E449E3ECE38EE330E2D1E271E211E1B0)

, .INIT_37 (256'hEC52EC03EBB4EB64EB13EAC2EA70EA1EE9CBE977E923E8CEE879E823E7CCE775)

, .INIT_38 (256'hF0ECF0A7F061F01BEFD4EF8CEF44EEFCEEB2EE68EE1EEDD3ED87ED3BECEEECA0)

, .INIT_39 (256'hF4EAF4AEF472F436F3F9F3BBF37DF33EF2FEF2BEF27DF23CF1FAF1B7F174F130)

, .INIT_3A (256'hF84CF81AF7E8F7B5F782F74EF719F6E4F6AEF678F641F609F5D1F598F55EF524)

, .INIT_3B (256'hFB11FAE9FAC1FA98FA6EFA44FA19F9EEF9C2F995F968F93AF90CF8DCF8ADF87C)

, .INIT_3C (256'hFD39FD1BFCFCFCDDFCBDFC9DFC7CFC5BFC38FC16FBF2FBCEFBA9FB84FB5EFB38)

, .INIT_3D (256'hFEC3FEAFFE9BFE85FE6FFE59FE42FE2AFE12FDF9FDDFFDC5FDAAFD8FFD73FD56)

, .INIT_3E (256'hFFB0FFA6FF9BFF90FF84FF77FF6AFF5CFF4DFF3EFF2FFF1EFF0DFEFCFEE9FED7)

, .INIT_3F (256'hFFFFFFFFFFFEFFFCFFFAFFF7FFF4FFF0FFEBFFE6FFE0FFDAFFD3FFCBFFC3FFBA)

, .INITP_01 (256'h5555555555555555555555555555555555555555555555000000000000000000)

, .INITP_02 (256'hAAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555555)

, .INITP_03 (256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA)

, .INITP_04 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAA)

, .INITP_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)

, .INITP_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)

, .INITP_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)