Loading .project +11 −11 Original line number Diff line number Diff line Loading @@ -62,52 +62,52 @@ <link> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160328235916328.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160328235916328.log</location> </link> <link> <name>vivado_logs/VivadoTimingReportSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160328235916328.log</location> </link> <link> <name>vivado_state/x393-opt-phys.dcp</name> Loading @@ -127,7 +127,7 @@ <link> <name>vivado_state/x393-synth.dcp</name> <type>1</type> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160327153927194.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160328235916328.dcp</location> </link> </linkedResources> </projectDescription> .settings/com.elphel.vdt.VivadoSynthesis.prefs +1 −1 Original line number Diff line number Diff line Loading @@ -7,7 +7,7 @@ VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.x VivadoSynthesis_122_SkipSnapshotSynth=true VivadoSynthesis_123_ResetProject=true VivadoSynthesis_123_SkipSnapshotSynth=true VivadoSynthesis_124_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@-> VivadoSynthesis_124_ConstraintsFiles=x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@-> VivadoSynthesis_127_verbose=true VivadoSynthesis_81_parser_mode=1 VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@-> Loading fpga_version.vh +2 −1 Original line number Diff line number Diff line Loading @@ -32,7 +32,8 @@ * with at least one of the Free Software programs. *******************************************************************************/ parameter FPGA_VERSION = 32'h0393007d; // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc // parameter FPGA_VERSION = 32'h0393007d; // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers. Timing met // parameter FPGA_VERSION = 32'h0393007c; // fixed cmdseqmux - reporting interrupt status and mask correctly // parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff // parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK Loading x393.bit (5.7 MiB) File changed.No diff preview for this file type. View original file View changed file x393_placement.tcl 0 → 100644 +304 −0 Original line number Diff line number Diff line ################################################################################# # Filename: x393_placement.tcl # Date:2016-03-28 # Author: Andrey Filippov # Description: Placementg constraints (selected by HISPI parameter in system_devines.vh) # # Copyright (c) 2016 Elphel, Inc. # x393_placement.tcl is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation, either version 3 of the License, or # (at your option) any later version. # # x393_placement.tcl is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program. If not, see <http://www.gnu.org/licenses/> . # # Additional permission under GNU GPL version 3 section 7: # If you modify this Program, or any covered work, by linking or combining it # with independent modules provided by the FPGA vendor only (this permission # does not extend to any 3-rd party modules, "soft cores" or macros) under # different license terms solely for the purpose of generating binary "bitstream" # files and/or simulating the code, the copyright holders of this Program give # you the right to distribute the covered work without those independent modules # as long as the source code for them is available from the FPGA vendor free of # charge, and there is no dependence on any encrypted modules for simulating of # the combined code. This permission applies to you if the distributed code # contains all the components and scripts required to completely simulate it # with at least one of the Free Software programs. ################################################################################# cd ~/vdt/x393 set infile [open "system_defines.vh" r] set HISPI 0 while { [gets $infile line] >= 0 } { if { [regexp {(.*)`define(\s*)HISPI} $line matched prematch] } { if {[regexp "//" $prematch] != 0} { continue } set HISPI 1 break } } close $infile if { $HISPI} { puts "using HISPI sensors" } else { puts "using parallel sensors" } # Global constraints set_property INTERNAL_VREF 0.750 [get_iobanks 34] set_property DCI_CASCADE 34 [get_iobanks 35] set_property INTERNAL_VREF 0.750 [get_iobanks 35] set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] # Disabling some of the DRC checks: #http://forums.xilinx.com/t5/7-Series-FPGAs/MMCM-reference-clock-muxing/td-p/550622 set_property is_enabled false [get_drc_checks REQP-119] #Input Buffer Connections .. has no loads. An input buffer must drive an internal load. set_property is_enabled false [get_drc_checks BUFC-1] #DSP Buffering: set_property is_enabled false [get_drc_checks DPIP-1] set_property is_enabled false [get_drc_checks DPOP-1] #MMCME2_ADV connectivity violation set_property is_enabled false [get_drc_checks REQP-1577] #Synchronous clocking for BRAM (mult_saxi_wr_inbuf_i/ram_var_w_var_r_i/ram_i/RAMB36E1_i) in SDP mode ... set_property is_enabled false [get_drc_checks REQP-165] #Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS. set_property is_enabled false [get_drc_checks REQP-14] set_property PACKAGE_PIN J4 [get_ports {SDRST}] set_property PACKAGE_PIN K3 [get_ports {SDCLK}] set_property PACKAGE_PIN K2 [get_ports {SDNCLK}] set_property PACKAGE_PIN N3 [get_ports {SDA[0]}] set_property PACKAGE_PIN H2 [get_ports {SDA[1]}] set_property PACKAGE_PIN M2 [get_ports {SDA[2]}] set_property PACKAGE_PIN P5 [get_ports {SDA[3]}] set_property PACKAGE_PIN H1 [get_ports {SDA[4]}] set_property PACKAGE_PIN M3 [get_ports {SDA[5]}] set_property PACKAGE_PIN J1 [get_ports {SDA[6]}] set_property PACKAGE_PIN P4 [get_ports {SDA[7]}] set_property PACKAGE_PIN K1 [get_ports {SDA[8]}] set_property PACKAGE_PIN P3 [get_ports {SDA[9]}] set_property PACKAGE_PIN F2 [get_ports {SDA[10]}] set_property PACKAGE_PIN H3 [get_ports {SDA[11]}] set_property PACKAGE_PIN G3 [get_ports {SDA[12]}] set_property PACKAGE_PIN N2 [get_ports {SDA[13]}] set_property PACKAGE_PIN J3 [get_ports {SDA[14]}] set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}] set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}] set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}] set_property PACKAGE_PIN G4 [get_ports {SDWE}] set_property PACKAGE_PIN L2 [get_ports {SDRAS}] set_property PACKAGE_PIN L1 [get_ports {SDCAS}] set_property PACKAGE_PIN E1 [get_ports {SDCKE}] set_property PACKAGE_PIN M7 [get_ports {SDODT}] set_property PACKAGE_PIN K6 [get_ports {SDD[0]}] set_property PACKAGE_PIN L4 [get_ports {SDD[1]}] set_property PACKAGE_PIN K7 [get_ports {SDD[2]}] set_property PACKAGE_PIN K4 [get_ports {SDD[3]}] set_property PACKAGE_PIN L6 [get_ports {SDD[4]}] set_property PACKAGE_PIN M4 [get_ports {SDD[5]}] set_property PACKAGE_PIN L7 [get_ports {SDD[6]}] set_property PACKAGE_PIN N5 [get_ports {SDD[7]}] set_property PACKAGE_PIN H5 [get_ports {SDD[8]}] set_property PACKAGE_PIN J6 [get_ports {SDD[9]}] set_property PACKAGE_PIN G5 [get_ports {SDD[10]}] set_property PACKAGE_PIN H6 [get_ports {SDD[11]}] set_property PACKAGE_PIN F5 [get_ports {SDD[12]}] set_property PACKAGE_PIN F7 [get_ports {SDD[13]}] set_property PACKAGE_PIN F4 [get_ports {SDD[14]}] set_property PACKAGE_PIN F6 [get_ports {SDD[15]}] set_property PACKAGE_PIN N7 [get_ports {DQSL}] set_property PACKAGE_PIN N6 [get_ports {NDQSL}] set_property PACKAGE_PIN H7 [get_ports {DQSU}] set_property PACKAGE_PIN G7 [get_ports {NDQSU}] set_property PACKAGE_PIN L5 [get_ports {SDDML}] set_property PACKAGE_PIN J5 [get_ports {SDDMU}] #not yet used, just for debugging set_property PACKAGE_PIN M5 [get_ports {memclk}] # ======== GPIO pins =============== # inout [GPIO_N-1:0] gpio_pins, set_property PACKAGE_PIN B4 [get_ports {gpio_pins[0]}] set_property PACKAGE_PIN A4 [get_ports {gpio_pins[1]}] set_property PACKAGE_PIN A2 [get_ports {gpio_pins[2]}] set_property PACKAGE_PIN A1 [get_ports {gpio_pins[3]}] set_property PACKAGE_PIN C3 [get_ports {gpio_pins[4]}] set_property PACKAGE_PIN D3 [get_ports {gpio_pins[5]}] set_property PACKAGE_PIN D1 [get_ports {gpio_pins[6]}] set_property PACKAGE_PIN C1 [get_ports {gpio_pins[7]}] set_property PACKAGE_PIN C2 [get_ports {gpio_pins[8]}] set_property PACKAGE_PIN B2 [get_ports {gpio_pins[9]}] # =========Differential clock inputs ========== # input ffclk0p, // Y12 # input ffclk0n, // Y11 # input ffclk1p, // W14 # input ffclk1n // W13 set_property PACKAGE_PIN Y12 [get_ports {ffclk0p}] set_property PACKAGE_PIN Y11 [get_ports {ffclk0n}] set_property PACKAGE_PIN W14 [get_ports {ffclk1p}] set_property PACKAGE_PIN W13 [get_ports {ffclk1n}] # ================= Sensor port 0 ================= set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}] set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}] set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}] set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}] set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}] set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}] set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}] set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}] if { $HISPI } { set_property PACKAGE_PIN AB9 [get_ports {sns1_dp74[4]}] set_property PACKAGE_PIN AB8 [get_ports {sns1_dn74[4]}] set_property PACKAGE_PIN AB13 [get_ports {sns1_dp74[5]}] set_property PACKAGE_PIN AB12 [get_ports {sns1_dn74[5]}] set_property PACKAGE_PIN AA12 [get_ports {sns1_dp74[6]}] set_property PACKAGE_PIN AA11 [get_ports {sns1_dn74[6]}] set_property PACKAGE_PIN W11 [get_ports {sns1_dp74[7]}] set_property PACKAGE_PIN W10 [get_ports {sns1_dn74[7]}] } else { set_property PACKAGE_PIN AB9 [get_ports {sns1_dp[4]}] set_property PACKAGE_PIN AB8 [get_ports {sns1_dn[4]}] set_property PACKAGE_PIN AB13 [get_ports {sns1_dp[5]}] set_property PACKAGE_PIN AB12 [get_ports {sns1_dn[5]}] set_property PACKAGE_PIN AA12 [get_ports {sns1_dp[6]}] set_property PACKAGE_PIN AA11 [get_ports {sns1_dn[6]}] set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}] set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}] } set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}] set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}] set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}] set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}] set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}] set_property PACKAGE_PIN U8 [get_ports {sns1_pg}] # ================= Sensor port 1 ================= set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}] set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}] set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}] set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}] set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}] set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}] set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}] set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}] if { $HISPI } { set_property PACKAGE_PIN AA17 [get_ports {sns2_dp74[4]}] set_property PACKAGE_PIN AB17 [get_ports {sns2_dn74[4]}] set_property PACKAGE_PIN AA15 [get_ports {sns2_dp74[5]}] set_property PACKAGE_PIN AB15 [get_ports {sns2_dn74[5]}] set_property PACKAGE_PIN AA14 [get_ports {sns2_dp74[6]}] set_property PACKAGE_PIN AB14 [get_ports {sns2_dn74[6]}] set_property PACKAGE_PIN Y14 [get_ports {sns2_dp74[7]}] set_property PACKAGE_PIN Y13 [get_ports {sns2_dn74[7]}] } else { set_property PACKAGE_PIN AA17 [get_ports {sns2_dp[4]}] set_property PACKAGE_PIN AB17 [get_ports {sns2_dn[4]}] set_property PACKAGE_PIN AA15 [get_ports {sns2_dp[5]}] set_property PACKAGE_PIN AB15 [get_ports {sns2_dn[5]}] set_property PACKAGE_PIN AA14 [get_ports {sns2_dp[6]}] set_property PACKAGE_PIN AB14 [get_ports {sns2_dn[6]}] set_property PACKAGE_PIN Y14 [get_ports {sns2_dp[7]}] set_property PACKAGE_PIN Y13 [get_ports {sns2_dn[7]}] } set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}] set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}] set_property PACKAGE_PIN T12 [get_ports {sns2_scl}] set_property PACKAGE_PIN U12 [get_ports {sns2_sda}] set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}] set_property PACKAGE_PIN W16 [get_ports {sns2_pg}] # ================= Sensor port 2 ================= set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}] set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}] set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}] set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}] set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}] set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}] set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}] set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}] if { $HISPI } { set_property PACKAGE_PIN N21 [get_ports {sns3_dp74[4]}] set_property PACKAGE_PIN N22 [get_ports {sns3_dn74[4]}] set_property PACKAGE_PIN R22 [get_ports {sns3_dp74[5]}] set_property PACKAGE_PIN T22 [get_ports {sns3_dn74[5]}] set_property PACKAGE_PIN P21 [get_ports {sns3_dp74[6]}] set_property PACKAGE_PIN R21 [get_ports {sns3_dn74[6]}] set_property PACKAGE_PIN T20 [get_ports {sns3_dp74[7]}] set_property PACKAGE_PIN U20 [get_ports {sns3_dn74[7]}] } else { set_property PACKAGE_PIN N21 [get_ports {sns3_dp[4]}] set_property PACKAGE_PIN N22 [get_ports {sns3_dn[4]}] set_property PACKAGE_PIN R22 [get_ports {sns3_dp[5]}] set_property PACKAGE_PIN T22 [get_ports {sns3_dn[5]}] set_property PACKAGE_PIN P21 [get_ports {sns3_dp[6]}] set_property PACKAGE_PIN R21 [get_ports {sns3_dn[6]}] set_property PACKAGE_PIN T20 [get_ports {sns3_dp[7]}] set_property PACKAGE_PIN U20 [get_ports {sns3_dn[7]}] } set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}] set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}] set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}] set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}] set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}] set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}] # ================= Sensor port 3 ================= set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}] set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}] set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}] set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}] set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}] set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}] set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}] set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}] if { $HISPI } { set_property PACKAGE_PIN P18 [get_ports {sns4_dp74[4]}] set_property PACKAGE_PIN P19 [get_ports {sns4_dn74[4]}] set_property PACKAGE_PIN N17 [get_ports {sns4_dp74[5]}] set_property PACKAGE_PIN N18 [get_ports {sns4_dn74[5]}] set_property PACKAGE_PIN N20 [get_ports {sns4_dp74[6]}] set_property PACKAGE_PIN P20 [get_ports {sns4_dn74[6]}] set_property PACKAGE_PIN R17 [get_ports {sns4_dp74[7]}] set_property PACKAGE_PIN R18 [get_ports {sns4_dn74[7]}] } else { set_property PACKAGE_PIN P18 [get_ports {sns4_dp[4]}] set_property PACKAGE_PIN P19 [get_ports {sns4_dn[4]}] set_property PACKAGE_PIN N17 [get_ports {sns4_dp[5]}] set_property PACKAGE_PIN N18 [get_ports {sns4_dn[5]}] set_property PACKAGE_PIN N20 [get_ports {sns4_dp[6]}] set_property PACKAGE_PIN P20 [get_ports {sns4_dn[6]}] set_property PACKAGE_PIN R17 [get_ports {sns4_dp[7]}] set_property PACKAGE_PIN R18 [get_ports {sns4_dn[7]}] } set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}] set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}] set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}] set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}] set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}] set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}] # ===================== SATA ====================== # bind gtx reference clock set_property PACKAGE_PIN U6 [get_ports EXTCLK_P] set_property PACKAGE_PIN U5 [get_ports EXTCLK_N] # bind sata inputs/outputs set_property PACKAGE_PIN AA5 [get_ports RXN] set_property PACKAGE_PIN AA6 [get_ports RXP] set_property PACKAGE_PIN AB3 [get_ports TXN] set_property PACKAGE_PIN AB4 [get_ports TXP] Loading
.project +11 −11 Original line number Diff line number Diff line Loading @@ -62,52 +62,52 @@ <link> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160328235916328.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160329000509294.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160328235916328.log</location> </link> <link> <name>vivado_logs/VivadoTimingReportSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160327153927194.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160328235916328.log</location> </link> <link> <name>vivado_state/x393-opt-phys.dcp</name> Loading @@ -127,7 +127,7 @@ <link> <name>vivado_state/x393-synth.dcp</name> <type>1</type> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160327153927194.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160328235916328.dcp</location> </link> </linkedResources> </projectDescription>
.settings/com.elphel.vdt.VivadoSynthesis.prefs +1 −1 Original line number Diff line number Diff line Loading @@ -7,7 +7,7 @@ VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.x VivadoSynthesis_122_SkipSnapshotSynth=true VivadoSynthesis_123_ResetProject=true VivadoSynthesis_123_SkipSnapshotSynth=true VivadoSynthesis_124_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@-> VivadoSynthesis_124_ConstraintsFiles=x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@-> VivadoSynthesis_127_verbose=true VivadoSynthesis_81_parser_mode=1 VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@-> Loading
fpga_version.vh +2 −1 Original line number Diff line number Diff line Loading @@ -32,7 +32,8 @@ * with at least one of the Free Software programs. *******************************************************************************/ parameter FPGA_VERSION = 32'h0393007d; // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc // parameter FPGA_VERSION = 32'h0393007d; // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers. Timing met // parameter FPGA_VERSION = 32'h0393007c; // fixed cmdseqmux - reporting interrupt status and mask correctly // parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff // parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK Loading
x393.bit (5.7 MiB) File changed.No diff preview for this file type. View original file View changed file
x393_placement.tcl 0 → 100644 +304 −0 Original line number Diff line number Diff line ################################################################################# # Filename: x393_placement.tcl # Date:2016-03-28 # Author: Andrey Filippov # Description: Placementg constraints (selected by HISPI parameter in system_devines.vh) # # Copyright (c) 2016 Elphel, Inc. # x393_placement.tcl is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation, either version 3 of the License, or # (at your option) any later version. # # x393_placement.tcl is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program. If not, see <http://www.gnu.org/licenses/> . # # Additional permission under GNU GPL version 3 section 7: # If you modify this Program, or any covered work, by linking or combining it # with independent modules provided by the FPGA vendor only (this permission # does not extend to any 3-rd party modules, "soft cores" or macros) under # different license terms solely for the purpose of generating binary "bitstream" # files and/or simulating the code, the copyright holders of this Program give # you the right to distribute the covered work without those independent modules # as long as the source code for them is available from the FPGA vendor free of # charge, and there is no dependence on any encrypted modules for simulating of # the combined code. This permission applies to you if the distributed code # contains all the components and scripts required to completely simulate it # with at least one of the Free Software programs. ################################################################################# cd ~/vdt/x393 set infile [open "system_defines.vh" r] set HISPI 0 while { [gets $infile line] >= 0 } { if { [regexp {(.*)`define(\s*)HISPI} $line matched prematch] } { if {[regexp "//" $prematch] != 0} { continue } set HISPI 1 break } } close $infile if { $HISPI} { puts "using HISPI sensors" } else { puts "using parallel sensors" } # Global constraints set_property INTERNAL_VREF 0.750 [get_iobanks 34] set_property DCI_CASCADE 34 [get_iobanks 35] set_property INTERNAL_VREF 0.750 [get_iobanks 35] set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] # Disabling some of the DRC checks: #http://forums.xilinx.com/t5/7-Series-FPGAs/MMCM-reference-clock-muxing/td-p/550622 set_property is_enabled false [get_drc_checks REQP-119] #Input Buffer Connections .. has no loads. An input buffer must drive an internal load. set_property is_enabled false [get_drc_checks BUFC-1] #DSP Buffering: set_property is_enabled false [get_drc_checks DPIP-1] set_property is_enabled false [get_drc_checks DPOP-1] #MMCME2_ADV connectivity violation set_property is_enabled false [get_drc_checks REQP-1577] #Synchronous clocking for BRAM (mult_saxi_wr_inbuf_i/ram_var_w_var_r_i/ram_i/RAMB36E1_i) in SDP mode ... set_property is_enabled false [get_drc_checks REQP-165] #Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS. set_property is_enabled false [get_drc_checks REQP-14] set_property PACKAGE_PIN J4 [get_ports {SDRST}] set_property PACKAGE_PIN K3 [get_ports {SDCLK}] set_property PACKAGE_PIN K2 [get_ports {SDNCLK}] set_property PACKAGE_PIN N3 [get_ports {SDA[0]}] set_property PACKAGE_PIN H2 [get_ports {SDA[1]}] set_property PACKAGE_PIN M2 [get_ports {SDA[2]}] set_property PACKAGE_PIN P5 [get_ports {SDA[3]}] set_property PACKAGE_PIN H1 [get_ports {SDA[4]}] set_property PACKAGE_PIN M3 [get_ports {SDA[5]}] set_property PACKAGE_PIN J1 [get_ports {SDA[6]}] set_property PACKAGE_PIN P4 [get_ports {SDA[7]}] set_property PACKAGE_PIN K1 [get_ports {SDA[8]}] set_property PACKAGE_PIN P3 [get_ports {SDA[9]}] set_property PACKAGE_PIN F2 [get_ports {SDA[10]}] set_property PACKAGE_PIN H3 [get_ports {SDA[11]}] set_property PACKAGE_PIN G3 [get_ports {SDA[12]}] set_property PACKAGE_PIN N2 [get_ports {SDA[13]}] set_property PACKAGE_PIN J3 [get_ports {SDA[14]}] set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}] set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}] set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}] set_property PACKAGE_PIN G4 [get_ports {SDWE}] set_property PACKAGE_PIN L2 [get_ports {SDRAS}] set_property PACKAGE_PIN L1 [get_ports {SDCAS}] set_property PACKAGE_PIN E1 [get_ports {SDCKE}] set_property PACKAGE_PIN M7 [get_ports {SDODT}] set_property PACKAGE_PIN K6 [get_ports {SDD[0]}] set_property PACKAGE_PIN L4 [get_ports {SDD[1]}] set_property PACKAGE_PIN K7 [get_ports {SDD[2]}] set_property PACKAGE_PIN K4 [get_ports {SDD[3]}] set_property PACKAGE_PIN L6 [get_ports {SDD[4]}] set_property PACKAGE_PIN M4 [get_ports {SDD[5]}] set_property PACKAGE_PIN L7 [get_ports {SDD[6]}] set_property PACKAGE_PIN N5 [get_ports {SDD[7]}] set_property PACKAGE_PIN H5 [get_ports {SDD[8]}] set_property PACKAGE_PIN J6 [get_ports {SDD[9]}] set_property PACKAGE_PIN G5 [get_ports {SDD[10]}] set_property PACKAGE_PIN H6 [get_ports {SDD[11]}] set_property PACKAGE_PIN F5 [get_ports {SDD[12]}] set_property PACKAGE_PIN F7 [get_ports {SDD[13]}] set_property PACKAGE_PIN F4 [get_ports {SDD[14]}] set_property PACKAGE_PIN F6 [get_ports {SDD[15]}] set_property PACKAGE_PIN N7 [get_ports {DQSL}] set_property PACKAGE_PIN N6 [get_ports {NDQSL}] set_property PACKAGE_PIN H7 [get_ports {DQSU}] set_property PACKAGE_PIN G7 [get_ports {NDQSU}] set_property PACKAGE_PIN L5 [get_ports {SDDML}] set_property PACKAGE_PIN J5 [get_ports {SDDMU}] #not yet used, just for debugging set_property PACKAGE_PIN M5 [get_ports {memclk}] # ======== GPIO pins =============== # inout [GPIO_N-1:0] gpio_pins, set_property PACKAGE_PIN B4 [get_ports {gpio_pins[0]}] set_property PACKAGE_PIN A4 [get_ports {gpio_pins[1]}] set_property PACKAGE_PIN A2 [get_ports {gpio_pins[2]}] set_property PACKAGE_PIN A1 [get_ports {gpio_pins[3]}] set_property PACKAGE_PIN C3 [get_ports {gpio_pins[4]}] set_property PACKAGE_PIN D3 [get_ports {gpio_pins[5]}] set_property PACKAGE_PIN D1 [get_ports {gpio_pins[6]}] set_property PACKAGE_PIN C1 [get_ports {gpio_pins[7]}] set_property PACKAGE_PIN C2 [get_ports {gpio_pins[8]}] set_property PACKAGE_PIN B2 [get_ports {gpio_pins[9]}] # =========Differential clock inputs ========== # input ffclk0p, // Y12 # input ffclk0n, // Y11 # input ffclk1p, // W14 # input ffclk1n // W13 set_property PACKAGE_PIN Y12 [get_ports {ffclk0p}] set_property PACKAGE_PIN Y11 [get_ports {ffclk0n}] set_property PACKAGE_PIN W14 [get_ports {ffclk1p}] set_property PACKAGE_PIN W13 [get_ports {ffclk1n}] # ================= Sensor port 0 ================= set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}] set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}] set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}] set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}] set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}] set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}] set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}] set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}] if { $HISPI } { set_property PACKAGE_PIN AB9 [get_ports {sns1_dp74[4]}] set_property PACKAGE_PIN AB8 [get_ports {sns1_dn74[4]}] set_property PACKAGE_PIN AB13 [get_ports {sns1_dp74[5]}] set_property PACKAGE_PIN AB12 [get_ports {sns1_dn74[5]}] set_property PACKAGE_PIN AA12 [get_ports {sns1_dp74[6]}] set_property PACKAGE_PIN AA11 [get_ports {sns1_dn74[6]}] set_property PACKAGE_PIN W11 [get_ports {sns1_dp74[7]}] set_property PACKAGE_PIN W10 [get_ports {sns1_dn74[7]}] } else { set_property PACKAGE_PIN AB9 [get_ports {sns1_dp[4]}] set_property PACKAGE_PIN AB8 [get_ports {sns1_dn[4]}] set_property PACKAGE_PIN AB13 [get_ports {sns1_dp[5]}] set_property PACKAGE_PIN AB12 [get_ports {sns1_dn[5]}] set_property PACKAGE_PIN AA12 [get_ports {sns1_dp[6]}] set_property PACKAGE_PIN AA11 [get_ports {sns1_dn[6]}] set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}] set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}] } set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}] set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}] set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}] set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}] set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}] set_property PACKAGE_PIN U8 [get_ports {sns1_pg}] # ================= Sensor port 1 ================= set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}] set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}] set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}] set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}] set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}] set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}] set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}] set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}] if { $HISPI } { set_property PACKAGE_PIN AA17 [get_ports {sns2_dp74[4]}] set_property PACKAGE_PIN AB17 [get_ports {sns2_dn74[4]}] set_property PACKAGE_PIN AA15 [get_ports {sns2_dp74[5]}] set_property PACKAGE_PIN AB15 [get_ports {sns2_dn74[5]}] set_property PACKAGE_PIN AA14 [get_ports {sns2_dp74[6]}] set_property PACKAGE_PIN AB14 [get_ports {sns2_dn74[6]}] set_property PACKAGE_PIN Y14 [get_ports {sns2_dp74[7]}] set_property PACKAGE_PIN Y13 [get_ports {sns2_dn74[7]}] } else { set_property PACKAGE_PIN AA17 [get_ports {sns2_dp[4]}] set_property PACKAGE_PIN AB17 [get_ports {sns2_dn[4]}] set_property PACKAGE_PIN AA15 [get_ports {sns2_dp[5]}] set_property PACKAGE_PIN AB15 [get_ports {sns2_dn[5]}] set_property PACKAGE_PIN AA14 [get_ports {sns2_dp[6]}] set_property PACKAGE_PIN AB14 [get_ports {sns2_dn[6]}] set_property PACKAGE_PIN Y14 [get_ports {sns2_dp[7]}] set_property PACKAGE_PIN Y13 [get_ports {sns2_dn[7]}] } set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}] set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}] set_property PACKAGE_PIN T12 [get_ports {sns2_scl}] set_property PACKAGE_PIN U12 [get_ports {sns2_sda}] set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}] set_property PACKAGE_PIN W16 [get_ports {sns2_pg}] # ================= Sensor port 2 ================= set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}] set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}] set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}] set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}] set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}] set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}] set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}] set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}] if { $HISPI } { set_property PACKAGE_PIN N21 [get_ports {sns3_dp74[4]}] set_property PACKAGE_PIN N22 [get_ports {sns3_dn74[4]}] set_property PACKAGE_PIN R22 [get_ports {sns3_dp74[5]}] set_property PACKAGE_PIN T22 [get_ports {sns3_dn74[5]}] set_property PACKAGE_PIN P21 [get_ports {sns3_dp74[6]}] set_property PACKAGE_PIN R21 [get_ports {sns3_dn74[6]}] set_property PACKAGE_PIN T20 [get_ports {sns3_dp74[7]}] set_property PACKAGE_PIN U20 [get_ports {sns3_dn74[7]}] } else { set_property PACKAGE_PIN N21 [get_ports {sns3_dp[4]}] set_property PACKAGE_PIN N22 [get_ports {sns3_dn[4]}] set_property PACKAGE_PIN R22 [get_ports {sns3_dp[5]}] set_property PACKAGE_PIN T22 [get_ports {sns3_dn[5]}] set_property PACKAGE_PIN P21 [get_ports {sns3_dp[6]}] set_property PACKAGE_PIN R21 [get_ports {sns3_dn[6]}] set_property PACKAGE_PIN T20 [get_ports {sns3_dp[7]}] set_property PACKAGE_PIN U20 [get_ports {sns3_dn[7]}] } set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}] set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}] set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}] set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}] set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}] set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}] # ================= Sensor port 3 ================= set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}] set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}] set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}] set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}] set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}] set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}] set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}] set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}] if { $HISPI } { set_property PACKAGE_PIN P18 [get_ports {sns4_dp74[4]}] set_property PACKAGE_PIN P19 [get_ports {sns4_dn74[4]}] set_property PACKAGE_PIN N17 [get_ports {sns4_dp74[5]}] set_property PACKAGE_PIN N18 [get_ports {sns4_dn74[5]}] set_property PACKAGE_PIN N20 [get_ports {sns4_dp74[6]}] set_property PACKAGE_PIN P20 [get_ports {sns4_dn74[6]}] set_property PACKAGE_PIN R17 [get_ports {sns4_dp74[7]}] set_property PACKAGE_PIN R18 [get_ports {sns4_dn74[7]}] } else { set_property PACKAGE_PIN P18 [get_ports {sns4_dp[4]}] set_property PACKAGE_PIN P19 [get_ports {sns4_dn[4]}] set_property PACKAGE_PIN N17 [get_ports {sns4_dp[5]}] set_property PACKAGE_PIN N18 [get_ports {sns4_dn[5]}] set_property PACKAGE_PIN N20 [get_ports {sns4_dp[6]}] set_property PACKAGE_PIN P20 [get_ports {sns4_dn[6]}] set_property PACKAGE_PIN R17 [get_ports {sns4_dp[7]}] set_property PACKAGE_PIN R18 [get_ports {sns4_dn[7]}] } set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}] set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}] set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}] set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}] set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}] set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}] # ===================== SATA ====================== # bind gtx reference clock set_property PACKAGE_PIN U6 [get_ports EXTCLK_P] set_property PACKAGE_PIN U5 [get_ports EXTCLK_N] # bind sata inputs/outputs set_property PACKAGE_PIN AA5 [get_ports RXN] set_property PACKAGE_PIN AA6 [get_ports RXP] set_property PACKAGE_PIN AB3 [get_ports TXN] set_property PACKAGE_PIN AB4 [get_ports TXP]
