Commit bf5ea2bb authored Jun 30, 2016 by Andrey Filippov

working to add cocotb simualtion

parent bb9fdc40

.editor_defines

+1 −0

Original line number	Diff line number	Diff line
		// This file may be used to define same pre-processor macros to be included into each parsed file opened in the editor
		// `define IVERILOG 1 // if IVERILOG is defined, editor will use simulator's "point of view", if not that of synthesis.
		`define COCOTB 1 // if IVERILOG is defined, editor will use simulator's "point of view", if not that of synthesis.
		`include "system_defines.vh"

		No newline at end of file

.gitignore

+4 −1

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		@@ -52,3 +52,6 @@ simulation_data/*.jpeg
		.pydevproject
		#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported
		workingSet.psf
		*.fst
		cocotb/Makefile
		cocotb/sim_build
		No newline at end of file

.settings/com.elphel.vdt.FPGA_project.prefs

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		FPGA_project_0_SimulationTopFile=x393_testbench03.tf
		FPGA_project_1_SimulationTopModule=x393_testbench03
		FPGA_project_2_DUTTopFile=cocotb/x393_dut.v
		FPGA_project_2_ImplementationTopFile=x393.v
		FPGA_project_3_DUTTopModule=x393_dut
		FPGA_project_4_part=xc7z030fbg484-1
		FPGA_project_5_part=xc7z030fbg484-1
		com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
		com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@->
		eclipse.preferences.version=1

.settings/com.elphel.vdt.cocotb.prefs

0 → 100644

+8 −0

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		cocotb_107_CocotbDutTopFile=cocotb/x393_dut.v
		cocotb_111_CocotbMODULE=x393coco_02<-@\#\#@->
		cocotb_112_CocotbTESTCASE=run_test<-@\#\#@->
		cocotb_116_GTKWaveSavFile=x393_cocotb_02.sav
		cocotb_118_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
		cocotb_122_CocotbExtraFiles=glbl.v<-@\#\#@->
		com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->
		eclipse.preferences.version=1

cocotb/x393_dut.v

+712 −51

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