Commit bb5dabda authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Changed interrupt lines

parent a7abc965

.settings/com.elphel.vdt.VivadoBitstream.prefs

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VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->

VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->

VivadoBitstream_@_force=true

VivadoBitstream_@_force=true

VivadoBitstream_@_rawfile=x393_parallel

VivadoBitstream_@_rawfile=x393_hispi

com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->

com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->

eclipse.preferences.version=1
 
eclipse.preferences.version=1

VERSION

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@@ -4,4 +4,4 @@ 
# a. 3

# a. 3

# b. 3.2 (preferred)

# b. 3.2 (preferred)

# c. 3.2.4

# c. 3.2.4

1.160
 
1.161

fpga_version.vh

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@@ -35,7 +35,9 @@ 
 * contains all the components and scripts required to completely simulate it

 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 * with at least one of the Free Software programs.

 */

 */

        parameter FPGA_VERSION =          32'h039300a0;    // parallel, else same as 9f 78.91%, not met by -0.032

          parameter FPGA_VERSION =          32'h039300a1;      // hispi 81.19%, not met by -0.07

//        parameter FPGA_VERSION =          32'h039300a0;      // parallel, re-ran after bug fix, %79.38%, not met -0.072

//        parameter FPGA_VERSION =          32'h039300a0;    // parallel, else same as 9f 78.91%, not met by -0.032

//        parameter FPGA_VERSION =          32'h0393009f;    // hispi, adding IRQ status register (placemnt "explore") 81.36%, all met

//        parameter FPGA_VERSION =          32'h0393009f;    // hispi, adding IRQ status register (placemnt "explore") 81.36%, all met

//        parameter FPGA_VERSION =          32'h0393009e;    // hispi, adding IRQ status register 80.90%, timing failed by -0.218

//        parameter FPGA_VERSION =          32'h0393009e;    // hispi, adding IRQ status register 80.90%, timing failed by -0.218

//        parameter FPGA_VERSION =          32'h0393009d;    // hispi, adding IRQ from multi_saxi  80.95%, timing not met (-0.034 )

//        parameter FPGA_VERSION =          32'h0393009d;    // hispi, adding IRQ from multi_saxi  80.95%, timing not met (-0.034 )

system_defines.vh

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@@ -63,7 +63,7 @@ 
  `define PRELOAD_BRAMS

  `define PRELOAD_BRAMS

  `define DISPLAY_COMPRESSED_DATA  

  `define DISPLAY_COMPRESSED_DATA  

  // if HISPI is not defined, parallel sensor interface is used for all channels

  // if HISPI is not defined, parallel sensor interface is used for all channels

//  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/

  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/

//    `define USE_OLD_XDCT393  

//    `define USE_OLD_XDCT393  

//  `define USE_PCLK2X

//  `define USE_PCLK2X

//  `define USE_XCLK2X

//  `define USE_XCLK2X

x393.v

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@@ -2951,13 +2951,14 @@ sata_ahci_top sata_top( 
    .DMA3DATYPE(),               // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output

    .DMA3DATYPE(),               // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output

    .DMA3RSTN(),                 // DMAC 3 RESET output (reserved, do not use), output

    .DMA3RSTN(),                 // DMAC 3 RESET output (reserved, do not use), output

 // Interrupt signals

 // Interrupt signals

    .IRQF2P({mult_saxi_irq[3:0], // [19:16] interrupts from mult_saxi channels

    .IRQF2P({4'b0,               // [19:16] Reserved                            PPI: nFIQ, nIRQ (both CPUs)    

            cmprs_irq[3:0],      // [15:12] Compressor done interrupts

            cmprs_irq[3:0],      // [15:12] Compressor done interrupts          SPI: Numbers [91:88]

            frseq_irq[3:0],      // [11: 8] Frame sync interrupts

            frseq_irq[3:0],      // [11: 8] Frame sync interrupts               SPI: Numbers [87:84]

            7'b0,

            mult_saxi_irq[3:0],  // [ 7: 4] interrupts from mult_saxi channels  SPI: Numbers [68:65]

            sata_irq             // Put AHCI (SATA ) interrupt  

            3'b0,                // [ 3: 1] Reserved                            SPI: Numbers [65:63]

            }),                  // Interrupts, OL to PS [19:0], input

            sata_irq             // [    0] AHCI (SATA ) interrupt              SPI: Number     [62]

    .IRQP2F(),                   // Interrupts, OL to PS [28:0], output

            }),                  // Interrupts, PL to PS [19:0], input

    .IRQP2F(),                   // Interrupts, PL to PS [28:0], output

 // Event Signals

 // Event Signals

    .EVENTEVENTI(),              // EVENT Wake up one or both CPU from WFE state, input

    .EVENTEVENTI(),              // EVENT Wake up one or both CPU from WFE state, input

    .EVENTEVENTO(),              // EVENT Asserted when one of the COUs executed SEV instruction, output

    .EVENTEVENTO(),              // EVENT Asserted when one of the COUs executed SEV instruction, output