Commit baf9eed0 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

More tests with 4 sesnor and 4 compressor channels, turned off debug ring define

parent 514c0372

.gitignore

+4 −1
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@@ -4,6 +4,7 @@ syntax_* 
simulation/*

simulation/*

ise_*

ise_*

attic/*

attic/*

hardware_tests/*

IVERILOG_INCLUDE.v

IVERILOG_INCLUDE.v

x393.prj

x393.prj

*DEBUG_VDT*

*DEBUG_VDT*
@@ -13,14 +14,16 @@ x393.prj 
*.pickle

*.pickle

py393/dbg/*

py393/dbg/*

includes/x393_cur_params_sim.vh

includes/x393_cur_params_sim.vh

includes/x393_cur_params_target_gen.vh

includes/x393_cur_params_target_*.vh

py393/exp_gpio.py

py393/exp_gpio.py

py393/mon_gpio.py

py393/mon_gpio.py

savefile01.sav

savefile01.sav

x353

x353

compressor_jp/huff_fifo353.v

x393_testbench0-a1.sav

x393_testbench0-a1.sav

x393_testbench01-*.sav

x393_testbench01-*.sav

x393_testbench01.gtkw

x393_testbench01.gtkw

x393_testbench01_backup.sav

x393_testbench01_backup.sav

x393_testbench01_debug_membridge.sav

x393_testbench01_debug_membridge.sav

x393_testbench02.sav

x393_testbench02.sav

x393_testbench02-0.sav

.project

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@@ -62,42 +62,42 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150915011906545.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150916155306201.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150915011906545.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150916155306201.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150915011906545.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150916155306201.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150915011906545.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150916155306201.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150915011906545.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150916155306201.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150915011906545.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150916155306201.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150915011906545.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150916153820807.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150915011906545.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150916155306201.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

fpga_version.vh

+1 −1
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    parameter FPGA_VERSION =          32'h03930033;
 
    parameter FPGA_VERSION =          32'h03930034;
 
 No newline at end of file
 
 No newline at end of file

includes/x393_cur_params_target.vh

100644 → 100755
+9 −28
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/*******************************************************************************

/* This is a generated file with the current DDR3 memory timing parameters */

 * File: x393_cur_params_target.vh

 * Date:2015-02-07  

 * Author: Andrey Filippov     

 * Description: Memory controller parameters that need adjustment during training

 * Target ,pde

 * Copyright (c) 2015 Elphel, Inc.

 * x393_cur_params_target.vh is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 * x393_cur_params_target.vh is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

localparam  DLY_LANE0_ODELAY =  80'hd85c1014141814181218;

localparam  DLY_LANE0_IDELAY =  72'h2c7a8380897c807b88;

localparam  DLY_LANE1_ODELAY =  80'hd8581812181418181814;

localparam  DLY_LANE1_IDELAY =  72'h108078807a887c8280;

localparam          DLY_CMDA = 256'hd3d3d3d4dcd1d8cc494949494949494949d4d3ccd3d3dbd4ccd4d2d3d1d2d8cc;

localparam         DLY_PHASE =   8'h33;

// localparam   DFLT_WBUF_DELAY =   4'h9;





localparam  DLY_LANE0_ODELAY =  80'hd8e8181c1c221c201b20;

localparam  DLY_LANE0_IDELAY =  72'h2078807c88797c7884;

localparam  DLY_LANE1_ODELAY =  80'hd8e31a181b1a1c1c1c1a;

localparam  DLY_LANE1_IDELAY =  72'h247b747b7882787c7c;

localparam          DLY_CMDA = 256'hd4d4d4dadcd3dbd0484848484848484848d4d4ccd4d4dcd9ccd8d4d4d3d3dbd0;

localparam         DLY_PHASE =   8'h32;

// localparam   DFLT_WBUF_DELAY =   4'h8;

py393/dbg/x393_mcntrl.pickle

+69842 −70775

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