Loading .project +8 −8 Original line number Diff line number Diff line Loading @@ -62,42 +62,42 @@ <link> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150916153820807.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150919164827543.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> Loading compressor_jp/compressor393.v +8 −1 Original line number Diff line number Diff line Loading @@ -42,7 +42,10 @@ module compressor393 # ( parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_CORING_MODE= 4, parameter CMPRS_TABLES= 6, // 6..7 parameter TABLE_QUANTIZATION_INDEX = 0, parameter TABLE_CORING_INDEX = 1, parameter TABLE_FOCUS_INDEX = 2, parameter TABLE_HUFFMAN_INDEX = 3, parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over) // Bit-fields in compressor control word Loading Loading @@ -323,6 +326,10 @@ module compressor393 # ( .CMPRS_COLOR_SATURATION (CMPRS_COLOR_SATURATION), .CMPRS_CORING_MODE (CMPRS_CORING_MODE), .CMPRS_TABLES (CMPRS_TABLES), .TABLE_QUANTIZATION_INDEX (TABLE_QUANTIZATION_INDEX), .TABLE_CORING_INDEX (TABLE_CORING_INDEX), .TABLE_FOCUS_INDEX (TABLE_FOCUS_INDEX), .TABLE_HUFFMAN_INDEX (TABLE_HUFFMAN_INDEX), .FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS), .LAST_FRAME_BITS (LAST_FRAME_BITS), .CMPRS_CBIT_RUN (CMPRS_CBIT_RUN), Loading compressor_jp/huffman393.v +1 −1 Original line number Diff line number Diff line Loading @@ -52,7 +52,7 @@ module huffman393 ( ); `ifdef INFER_LATCHES reg [15:0] hcode_latch; // table output huffman code (1..16 bits) reg [ 3:0] hlen_latch; // table - code length only 4 LSBs are used reg [ 3:0] hlen_latch; // table - code length only 4 LSBs are used, so 0 means 16 reg [ 7:0] haddr70_latch; reg haddr8_latch; reg tables_re_latch; Loading compressor_jp/jp_channel.v +15 −7 Original line number Diff line number Diff line Loading @@ -35,6 +35,10 @@ module jp_channel#( parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_CORING_MODE= 4, parameter CMPRS_TABLES= 6, // 6(data)..7(address) parameter TABLE_QUANTIZATION_INDEX = 0, parameter TABLE_CORING_INDEX = 1, parameter TABLE_FOCUS_INDEX = 2, parameter TABLE_HUFFMAN_INDEX = 3, parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over) Loading Loading @@ -889,22 +893,26 @@ module jp_channel#( // wire table_we; // writing to tables (decoded stb from cmd_deser) wire tser_a_not_d; // address/not data distributed to submodules wire [ 7:0] tser_d; // byte-wide serialized tables address/data to submodules wire tser_qe; // write serialized table data to quantizer wire tser_ce; // write serialized table data to coring wire tser_fe; // write serialized table data to focusing wire tser_he; // write serialized table data to Huffman wire [ 3:0] tser_sel; // vector of individual table selects (decoded from the 8 MSBs of the table address) wire tser_qe = tser_sel[TABLE_QUANTIZATION_INDEX]; // write serialized table data to quantizer wire tser_ce = tser_sel[TABLE_CORING_INDEX]; // write serialized table data to coring wire tser_fe = tser_sel[TABLE_FOCUS_INDEX]; // write serialized table data to focusing wire tser_he = tser_sel[TABLE_HUFFMAN_INDEX]; // write serialized table data to Huffman //{tser_he,tser_fe,tser_ce,tser_qe} // As all commands are 32-bit data, all 4 bytes will be written to a designated table (usually 2 of 16-bit writes) table_ad_transmit #( .NUM_CHANNELS(4), .ADDR_BITS(3) ) table_ad_transmit_i ( .clk (mclk), // input @posedge .srst (mrst), // @posedge mclk .a_not_d_in (cmd_a[0]), // input writing table address /not data (a[0] from cmd_deser) .we (set_tables_w), // input writing to tables (decoded stb from cmd_deser) .din (cmd_data), // input[31:0] 32-bit data to serialize/write to tables (LSB first) - from cmd_deser .ser_d (tser_d), // output[7:0] byte-wide serialized tables address/data to submodules .a_not_d (tser_a_not_d), // output reg address/not data distributed to submodules .chn_en ({tser_he,tser_fe,tser_ce,tser_qe}) // output[0:0] reg - table 1-hot select outputs // .chn_en ({tser_he,tser_fe,tser_ce,tser_qe}) // output[0:0] reg - table 1-hot select outputs .chn_en (tser_sel) // output[0:0] reg - table 1-hot select outputs ); Loading Loading @@ -950,7 +958,7 @@ module jp_channel#( .en (frame_en), // input .mclk (mclk), // input system clock to write tables .tser_we (tser_fe), // input - write to a quantization table .tser_we (tser_fe), // input - write to a focus sharpness table .tser_a_not_d (tser_a_not_d), // input - address/not data to tables .tser_d (tser_d), // input[7:0] - byte-wide data to tables Loading fpga_version.vh +1 −1 Original line number Diff line number Diff line parameter FPGA_VERSION = 32'h03930034; No newline at end of file parameter FPGA_VERSION = 32'h03930035; No newline at end of file Loading
.project +8 −8 Original line number Diff line number Diff line Loading @@ -62,42 +62,42 @@ <link> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150916153820807.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150919164827543.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150916155306201.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150919172017385.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> Loading
compressor_jp/compressor393.v +8 −1 Original line number Diff line number Diff line Loading @@ -42,7 +42,10 @@ module compressor393 # ( parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_CORING_MODE= 4, parameter CMPRS_TABLES= 6, // 6..7 parameter TABLE_QUANTIZATION_INDEX = 0, parameter TABLE_CORING_INDEX = 1, parameter TABLE_FOCUS_INDEX = 2, parameter TABLE_HUFFMAN_INDEX = 3, parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over) // Bit-fields in compressor control word Loading Loading @@ -323,6 +326,10 @@ module compressor393 # ( .CMPRS_COLOR_SATURATION (CMPRS_COLOR_SATURATION), .CMPRS_CORING_MODE (CMPRS_CORING_MODE), .CMPRS_TABLES (CMPRS_TABLES), .TABLE_QUANTIZATION_INDEX (TABLE_QUANTIZATION_INDEX), .TABLE_CORING_INDEX (TABLE_CORING_INDEX), .TABLE_FOCUS_INDEX (TABLE_FOCUS_INDEX), .TABLE_HUFFMAN_INDEX (TABLE_HUFFMAN_INDEX), .FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS), .LAST_FRAME_BITS (LAST_FRAME_BITS), .CMPRS_CBIT_RUN (CMPRS_CBIT_RUN), Loading
compressor_jp/huffman393.v +1 −1 Original line number Diff line number Diff line Loading @@ -52,7 +52,7 @@ module huffman393 ( ); `ifdef INFER_LATCHES reg [15:0] hcode_latch; // table output huffman code (1..16 bits) reg [ 3:0] hlen_latch; // table - code length only 4 LSBs are used reg [ 3:0] hlen_latch; // table - code length only 4 LSBs are used, so 0 means 16 reg [ 7:0] haddr70_latch; reg haddr8_latch; reg tables_re_latch; Loading
compressor_jp/jp_channel.v +15 −7 Original line number Diff line number Diff line Loading @@ -35,6 +35,10 @@ module jp_channel#( parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_CORING_MODE= 4, parameter CMPRS_TABLES= 6, // 6(data)..7(address) parameter TABLE_QUANTIZATION_INDEX = 0, parameter TABLE_CORING_INDEX = 1, parameter TABLE_FOCUS_INDEX = 2, parameter TABLE_HUFFMAN_INDEX = 3, parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over) Loading Loading @@ -889,22 +893,26 @@ module jp_channel#( // wire table_we; // writing to tables (decoded stb from cmd_deser) wire tser_a_not_d; // address/not data distributed to submodules wire [ 7:0] tser_d; // byte-wide serialized tables address/data to submodules wire tser_qe; // write serialized table data to quantizer wire tser_ce; // write serialized table data to coring wire tser_fe; // write serialized table data to focusing wire tser_he; // write serialized table data to Huffman wire [ 3:0] tser_sel; // vector of individual table selects (decoded from the 8 MSBs of the table address) wire tser_qe = tser_sel[TABLE_QUANTIZATION_INDEX]; // write serialized table data to quantizer wire tser_ce = tser_sel[TABLE_CORING_INDEX]; // write serialized table data to coring wire tser_fe = tser_sel[TABLE_FOCUS_INDEX]; // write serialized table data to focusing wire tser_he = tser_sel[TABLE_HUFFMAN_INDEX]; // write serialized table data to Huffman //{tser_he,tser_fe,tser_ce,tser_qe} // As all commands are 32-bit data, all 4 bytes will be written to a designated table (usually 2 of 16-bit writes) table_ad_transmit #( .NUM_CHANNELS(4), .ADDR_BITS(3) ) table_ad_transmit_i ( .clk (mclk), // input @posedge .srst (mrst), // @posedge mclk .a_not_d_in (cmd_a[0]), // input writing table address /not data (a[0] from cmd_deser) .we (set_tables_w), // input writing to tables (decoded stb from cmd_deser) .din (cmd_data), // input[31:0] 32-bit data to serialize/write to tables (LSB first) - from cmd_deser .ser_d (tser_d), // output[7:0] byte-wide serialized tables address/data to submodules .a_not_d (tser_a_not_d), // output reg address/not data distributed to submodules .chn_en ({tser_he,tser_fe,tser_ce,tser_qe}) // output[0:0] reg - table 1-hot select outputs // .chn_en ({tser_he,tser_fe,tser_ce,tser_qe}) // output[0:0] reg - table 1-hot select outputs .chn_en (tser_sel) // output[0:0] reg - table 1-hot select outputs ); Loading Loading @@ -950,7 +958,7 @@ module jp_channel#( .en (frame_en), // input .mclk (mclk), // input system clock to write tables .tser_we (tser_fe), // input - write to a quantization table .tser_we (tser_fe), // input - write to a focus sharpness table .tser_a_not_d (tser_a_not_d), // input - address/not data to tables .tser_d (tser_d), // input[7:0] - byte-wide data to tables Loading
fpga_version.vh +1 −1 Original line number Diff line number Diff line parameter FPGA_VERSION = 32'h03930034; No newline at end of file parameter FPGA_VERSION = 32'h03930035; No newline at end of file