added interrupt status read (a7abc965) · Commits · Elphel / x393

.settings/com.elphel.vdt.VivadoBitstream.prefs

+1 −1

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		VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
		VivadoBitstream_@_force=true
		VivadoBitstream_@_rawfile=x393_hispi
		VivadoBitstream_@_rawfile=x393_parallel
		com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
		eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoPlace.prefs

+2 −1

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		VivadoPlace_@_SkipSnapshotPlace=true
		VivadoPlace_@_directive_place=Explore
		VivadoPlace_@_verbose_place=true
		com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->VivadoPlace_@_SkipSnapshotPlace<-@\#\#@->
		com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->VivadoPlace_@_SkipSnapshotPlace<-@\#\#@->VivadoPlace_@_directive_place<-@\#\#@->
		eclipse.preferences.version=1

VERSION

+1 −1

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		@@ -4,4 +4,4 @@
		# a. 3
		# b. 3.2 (preferred)
		# c. 3.2.4
		1.157
		1.160

axi/mult_saxi_wr.v

+14 −7

Original line number	Diff line number	Diff line
		@@ -48,7 +48,8 @@ module mult_saxi_wr #(
		parameter MULT_SAXI_CNTRL_MODE = 'h0, // 'h73c offset for mode register
		parameter MULT_SAXI_CNTRL_STATUS = 'h1, // 'h73d offset for status control register
		parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
		parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
		parameter MULT_SAXI_POINTERS_REG = 'h34, //..'h37 uses 4 consecutive locations
		parameter MULT_SAXI_STATUS_REG = 'h3c, //status and IRQ requests and masks
		parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
		parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
		parameter MULT_SAXI_BSLOG1 = 4,
		@@ -557,9 +558,15 @@ module mult_saxi_wr #(
		reg [29:0] status_pntr2;
		reg [29:0] status_pntr3;
		wire pntr_we_mclk;
		wire [128:0] status_data;
		// wire [128:0] status_data;
		wire [137:0] status_data;
		reg status_tgl;
		assign status_data = {2'b0, status_pntr3, 2'b0, status_pntr2, 2'b0, status_pntr1, 2'b0, status_pntr0, status_tgl};
		assign status_data = {2'b0, status_pntr3,
		2'b0, status_pntr2,
		2'b0, status_pntr1,
		2'b0, status_pntr0,
		irq_m[3:0],irq_r[3:0],
		1'b0, status_tgl};
		always @ (posedge mclk) begin
		if (!en_mclk) status_tgl <= 0;
		else if (pntr_we_mclk) status_tgl <= ~status_tgl;
		@@ -573,18 +580,18 @@ module mult_saxi_wr #(
		pulse_cross_clock status_wr_i (.rst(arst), .src_clk(aclk), .dst_clk(mclk), .in_pulse(pntr_we), .out_pulse(pntr_we_mclk),.busy());

		status_generate #(
		.STATUS_REG_ADDR (MULT_SAXI_STATUS_REG+4), // not used
		.PAYLOAD_BITS (0),
		.STATUS_REG_ADDR (MULT_SAXI_STATUS_REG),
		.PAYLOAD_BITS (10),
		.REGISTER_STATUS (1),
		.EXTRA_WORDS (4),
		.EXTRA_REG_ADDR (MULT_SAXI_STATUS_REG)
		.EXTRA_REG_ADDR (MULT_SAXI_POINTERS_REG)
		) status_generate_i (
		.rst (1'b0), //rst), // input
		.clk (mclk), // input
		.srst (mrst), // input
		.we (we_ctrl && (cmd_a[1:0] == MULT_SAXI_CNTRL_STATUS)), // input
		.wd (cmd_data[7:0]), // input[7:0]
		.status (status_data), // input[128:0]
		.status (status_data), // input[137:0]
		.ad (status_ad), // output[7:0]
		.rq (status_rq), // output
		.start (status_start) // input

fpga_version.vh

+4 −1

Original line number	Diff line number	Diff line
		@@ -35,7 +35,10 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*/
		parameter FPGA_VERSION = 32'h0393009d; // hispi, adding IRQ from multi_saxi 80.95%, timing not met (-0.034 )
		parameter FPGA_VERSION = 32'h039300a0; // parallel, else same as 9f 78.91%, not met by -0.032
		// parameter FPGA_VERSION = 32'h0393009f; // hispi, adding IRQ status register (placemnt "explore") 81.36%, all met
		// parameter FPGA_VERSION = 32'h0393009e; // hispi, adding IRQ status register 80.90%, timing failed by -0.218
		// parameter FPGA_VERSION = 32'h0393009d; // hispi, adding IRQ from multi_saxi 80.95%, timing not met (-0.034 )
		// parameter FPGA_VERSION = 32'h0393009c; // parallel, adding IRQ from multi_saxi 79.31% , timing met (2015.3)
		// parameter FPGA_VERSION = 32'h0393009b; // parallel, bug fixed in dct_chen 79.58, timing met (2015.3)
		// parameter FPGA_VERSION = 32'h0393009a; // serial, bug fixed in dct_chen 80.94%, timing met (2015.3)

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