added main Python program control over socket, testedimage control/acquisition through web browser (a69b7a9b) · Commits · Elphel / x393

.project

+8 −8

Original line number	Original line	Diff line number	Diff line
	@@ -62,42 +62,42 @@
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151115151104872.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151117233913191.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151115151104872.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151117233913191.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151115151104872.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151117233913191.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151115151104872.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151117233913191.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151115151104872.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151117233913191.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151115151104872.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151117233913191.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151115150613168.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151117233307674.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151115151104872.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151117233913191.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

axi/cmprs_afi_mux.v

+19 −7

Original line number	Original line	Diff line number	Diff line
	@@ -195,11 +195,12 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),

	// reg [2:0] cur_chn; // 'b0xx - none, 'b1 - - channel number (should match fifo_ren*)		// reg [2:0] cur_chn; // 'b0xx - none, 'b1 - - channel number (should match fifo_ren*)
	reg [1:0] cur_chn; // 'b0xx - none, 'b1 - - channel number (should match fifo_ren*)		reg [1:0] cur_chn; // 'b0xx - none, 'b1 - - channel number (should match fifo_ren*)
	reg [31:0] left_to_eof; // number of chunks left to end of frame		reg [31:0] left_to_eof; // number of chunks left to end of frame (one less: 3 means 4 left)
	reg [3:0] fifo_flush_d; // fifo_flush* delayed by 1 clk (to detect rising edge		reg [3:0] fifo_flush_d; // fifo_flush* delayed by 1 clk (to detect rising edge
	reg [3:0] eof_stb; // single-cycle pulse after fifo_flush is asserted		reg [3:0] eof_stb; // single-cycle pulse after fifo_flush is asserted
	// reg [1:0] w64_cnt; // count 64-bit words in a chunk		// reg [1:0] w64_cnt; // count 64-bit words in a chunk
	// adjusted counters used for channel arbitration		// adjusted counters used for channel arbitration
			// pessimistic FIFO content counter - decrements (form FIFO counter) on FIFO reads, knows nothing of writes
	reg [35:0] counts_corr0; // registers to hold corrected (decremented currently processed ones if any) fifo count values, MSB - needs flush		reg [35:0] counts_corr0; // registers to hold corrected (decremented currently processed ones if any) fifo count values, MSB - needs flush
	reg [17:0] counts_corr1; // first arbitration level winning values		reg [17:0] counts_corr1; // first arbitration level winning values
	reg [8:0] counts_corr2; // second arbitration level winning values		reg [8:0] counts_corr2; // second arbitration level winning values
	@@ -231,6 +232,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
	// 3'h4 :		// 3'h4 :
	// ({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);		// ({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);

			// Why it has priority for \|counts_corr2[7:2] ? If next frame started, it may skip EOF? Or not?
			// it is just to pass to a channel, actual transfer size will be decided here (depending on EOF)
	wire [1:0] pre_chunk_inc_m1 = (\|counts_corr2[7:2])? // Would like to increment, if not roll-over		wire [1:0] pre_chunk_inc_m1 = (\|counts_corr2[7:2])? // Would like to increment, if not roll-over
	2'h3 :		2'h3 :
	left_to_eof[winner2 * 8 +: 2];		left_to_eof[winner2 * 8 +: 2];
	@@ -252,12 +255,15 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),

	wire [26:0] chunk_ptr_rd;		wire [26:0] chunk_ptr_rd;
	wire [ 3:0] chunk_ptr_ra;		wire [ 3:0] chunk_ptr_ra;

			// If flushing - whatever is left to EOF, otherwise corrected FIFO contents of the winner
	wire [ 7:0] items_left = counts_corr2[8] ? left_to_eof[(winner2 * 8) +: 8] : counts_corr2[7:0];		wire [ 7:0] items_left = counts_corr2[8] ? left_to_eof[(winner2 * 8) +: 8] : counts_corr2[7:0];

	reg [5:0] afi_awid_r;		reg [5:0] afi_awid_r;
			// "rollover" - roll over destination memory range
	wire [2:0] max_wlen; // 0,1,2,3,7 (7 - not limited by rollover) - calculated by cmprs_afi_mux_ptr		wire [2:0] max_wlen; // 0,1,2,3,7 (7 - not limited by rollover) - calculated by cmprs_afi_mux_ptr
	wire [1:0] want_wleft32 = (\|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over		// wants to write (want_wleft32+1) 32-byte chunks (4,3,2,1)
			wire [1:0] want_wleft32 = (\|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over (actually "3" means 2)

	assign cmd_we_status_w = cmd_we && ((cmd_a & 'hc) == CMPRS_AFIMUX_STATUS_CNTRL);		assign cmd_we_status_w = cmd_we && ((cmd_a & 'hc) == CMPRS_AFIMUX_STATUS_CNTRL);
	assign cmd_we_mode_w = cmd_we && (cmd_a == CMPRS_AFIMUX_MODE);		assign cmd_we_mode_w = cmd_we && (cmd_a == CMPRS_AFIMUX_MODE);
	@@ -366,16 +372,22 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
	// TODO: change &w64_cnt[1:0] so left_to_eof[*] will be updated earlier and valid at pre_busy_w		// TODO: change &w64_cnt[1:0] so left_to_eof[*] will be updated earlier and valid at pre_busy_w
	// Done, updating at the first (not last) word of 4		// Done, updating at the first (not last) word of 4
	// Now seems that eof_stb[i] & fifo_ren{i} == 0		// Now seems that eof_stb[i] & fifo_ren{i} == 0
	if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - (fifo_ren0 & (&wleft[1:0]));		// Seems needs to decrement fifo_count0_m1 regardless of &wleft[1:0] - if started, will eventually decrement
			// How to make sure that decremented value always >0?
			// if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - (fifo_ren0 & (&wleft[1:0]));
			if (eof_stb[0]) left_to_eof[0 * 8 +: 8] <= fifo_count0_m1 - fifo_ren0;
	else if (fifo_ren0 & (&wleft[1:0])) left_to_eof[0 * 8 +: 8] <= left_to_eof[0 * 8 +: 8] - 1;		else if (fifo_ren0 & (&wleft[1:0])) left_to_eof[0 * 8 +: 8] <= left_to_eof[0 * 8 +: 8] - 1;

	if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - (fifo_ren1 & (&wleft[1:0]));		// if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - (fifo_ren1 & (&wleft[1:0]));
			if (eof_stb[1]) left_to_eof[1 * 8 +: 8] <= fifo_count1_m1 - fifo_ren1;
	else if (fifo_ren1 & (&wleft[1:0])) left_to_eof[1 * 8 +: 8] <= left_to_eof[1 * 8 +: 8] - 1;		else if (fifo_ren1 & (&wleft[1:0])) left_to_eof[1 * 8 +: 8] <= left_to_eof[1 * 8 +: 8] - 1;

	if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - (fifo_ren2 & (&wleft[1:0]));		// if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - (fifo_ren2 & (&wleft[1:0]));
			if (eof_stb[2]) left_to_eof[2 * 8 +: 8] <= fifo_count2_m1 - fifo_ren2;
	else if (fifo_ren2 & (&wleft[1:0])) left_to_eof[2 * 8 +: 8] <= left_to_eof[2 * 8 +: 8] - 1;		else if (fifo_ren2 & (&wleft[1:0])) left_to_eof[2 * 8 +: 8] <= left_to_eof[2 * 8 +: 8] - 1;

	if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - (fifo_ren3 & (&wleft[1:0]));		// if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - (fifo_ren3 & (&wleft[1:0]));
			if (eof_stb[3]) left_to_eof[3 * 8 +: 8] <= fifo_count3_m1 - fifo_ren3;
	else if (fifo_ren3 & (&wleft[1:0])) left_to_eof[3 * 8 +: 8] <= left_to_eof[3 * 8 +: 8] - 1;		else if (fifo_ren3 & (&wleft[1:0])) left_to_eof[3 * 8 +: 8] <= left_to_eof[3 * 8 +: 8] - 1;

	// Calculate corrected values decrementing currently served channel (if any) values by 1 (latency 1 clk)		// Calculate corrected values decrementing currently served channel (if any) values by 1 (latency 1 clk)

fpga_version.vh

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -31,7 +31,8 @@
	* contains all the components and scripts required to completely simulate it		* contains all the components and scripts required to completely simulate it
	* with at least one of the Free Software programs.		* with at least one of the Free Software programs.
	*******************************************************************************/		*******************************************************************************/
	parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)		parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
			// parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
	// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)		// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
	// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%)		// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%)
	// parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023		// parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023

py393/dbg/x393_mcntrl.pickle

+69221 −68659

File changed.

File size exceeds preview limit.

View original file

View changed file

py393/test_mcntrl.py

+101 −4

Original line number	Original line	Diff line number	Diff line
	@@ -22,6 +22,7 @@
	@contact: andrey@elphel.coml		@contact: andrey@elphel.coml
	@deffield updated: Updated		@deffield updated: Updated
	'''		'''
			from __future__ import print_function
	from __builtin__ import str		from __builtin__ import str
	__author__ = "Andrey Filippov"		__author__ = "Andrey Filippov"
	__copyright__ = "Copyright 2015, Elphel, Inc."		__copyright__ = "Copyright 2015, Elphel, Inc."
	@@ -43,6 +44,10 @@ from argparse import ArgumentParser
	#import argparse		#import argparse
	from argparse import RawDescriptionHelpFormatter		from argparse import RawDescriptionHelpFormatter
	import time		import time

			import socket
			import select

	from import_verilog_parameters import ImportVerilogParameters		from import_verilog_parameters import ImportVerilogParameters
	#from import_verilog_parameters import VerilogParameters		#from import_verilog_parameters import VerilogParameters
	from verilog_utils import hx		from verilog_utils import hx
	@@ -217,6 +222,8 @@ USAGE
	parser.add_argument("-x", "--exceptions", dest="exceptions", action="count", help="Exit on more exceptions [default: %(default)s]")		parser.add_argument("-x", "--exceptions", dest="exceptions", action="count", help="Exit on more exceptions [default: %(default)s]")
	parser.add_argument("-l", "--localparams", dest="localparams", action="store", default="",		parser.add_argument("-l", "--localparams", dest="localparams", action="store", default="",
	help="path were modified parameters are saved [default: %(default)s]", metavar="path")		help="path were modified parameters are saved [default: %(default)s]", metavar="path")
			parser.add_argument("-P", "--socket-port", dest="socket_port", action="store", default="",
			help="port to use for socket connection [default: %(default)s]")

	# Process arguments		# Process arguments
	args = parser.parse_args()		args = parser.parse_args()
	@@ -391,18 +398,75 @@ USAGE
	'''		'''
	#TODO: use readline		#TODO: use readline
	'''		'''
			if args.socket_port:
			PORT = int(args.socket_port) # 8888
			else:
			PORT = 0
			HOST = '' # Symbolic name meaning all available interfaces
			socket_conn = None
			if PORT:
			socket_conn = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
			try:
			socket_conn.bind((HOST, PORT))
			print ('Socket bind complete')
			socket_conn.listen(1) # just a single request
			print ('Socket now listening to a single request on port %d: send command, receive response, close'%(PORT))
			except socket.error as msg:
			print ('Bind failed. Error Code : %s Message %s'%( str(msg[0]),msg[1]))
			socket_conn = None # do not use sockets

	if (args.interactive):		if (args.interactive):
	line =""		line =""
	while True:		while True:
	line=raw_input('x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))).strip()		soc_conn = None
			prompt = 'x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))
			if socket_conn:
			print(prompt , end="")
			sys.stdout.flush()
			ready_to_read, _, _ = select.select( #ready_to_write, in_error
			[socket_conn, sys.stdin], # potential_readers,
			[], # potential_writers,
			[]) # potential_errs,
			if sys.stdin in ready_to_read:
			line=raw_input()
			# print ("stdin: ", line)
			elif socket_conn in ready_to_read:
			try:
			soc_conn, soc_addr = socket_conn.accept()
			print ("Connected with %s"%(soc_addr[0] + ':' + str(soc_addr[1])))
			#Sending message to connected client
			#soc_conn.send('Welcome to the server. Type something and hit enter\n') #send only takes string
			line = soc_conn.recv(4096) # or make it unlimited?
			print ('Received from socket: ', line)
			except:
			continue # socket probably died, wait for the next command
			else:
			print ("Unexpected result from select: ready_to_read = ",ready_to_read)
			continue
			else: # No sockets, just command line input
			line=raw_input(prompt)

			# line=raw_input('x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim))).strip()
			line=line.strip() # maybe also remove comment?

			# Process command, return result to a socket if it was a socket, not stdin


	tim=time.time()		tim=time.time()
	#remove comment from the input line		#remove comment from the input line
	if line.find("#") > 0:		had_comment=False
			if line.find("#") >= 0:
	line=line[:line.find("#")]		line=line[:line.find("#")]
			had_comment=True
	lineList=line.split()		lineList=line.split()
	if not line:		if not line:
			if not had_comment:
	print ('Use "quit" to exit, "help" - for help')		print ('Use "quit" to exit, "help" - for help')
	elif (line == 'quit') or (line == 'exit'):		elif (line == 'quit') or (line == 'exit'):
			if soc_conn:
			soc_conn.send('0\n') # OK\n')
			soc_conn.close()
			# soc_conn=None
	break		break
	elif line== 'help' :		elif line== 'help' :
	print ("\nAvailable tasks:")		print ("\nAvailable tasks:")
	@@ -412,7 +476,26 @@ USAGE
	print ('\n"parameters" and "defines" list known defined parameters and macros')		print ('\n"parameters" and "defines" list known defined parameters and macros')
	print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET))		print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET))
	print ("Enter 'R' to toggle show/hide command results, now it is %s"%(("OFF","ON")[showResult]))		print ("Enter 'R' to toggle show/hide command results, now it is %s"%(("OFF","ON")[showResult]))
			print ("Use 'socket_port' [PORT] to (re-)open socket on PORT (0 or no PORT - disable socket)")
	print ("Use 'pydev_predefines' to generate a parameter list to paste to vrlg.py, so Pydev will be happy")		print ("Use 'pydev_predefines' to generate a parameter list to paste to vrlg.py, so Pydev will be happy")
			elif (lineList[0].upper() == 'SOCKET_PORT') and (not soc_conn): # socket_conn):
			if socket_conn : # close old socket (if open)
			print ("Closed socket on port %d"%(PORT))
			socket_conn.close()
			socket_conn = None
			if len(lineList) > 1: # port specified
			PORT = int(lineList[1])
			if PORT:
			socket_conn = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
			try:
			socket_conn.bind((HOST, PORT))
			print ('Socket bind complete')
			socket_conn.listen(1) # just a single request
			print ('Socket now listening to a single request on port %d: send command, receive response, close'%(PORT))
			except socket.error as msg:
			print ('Bind failed. Error Code : %s Message %s'%( str(msg[0]),msg[1]))
			socket_conn = None # do not use sockets
			continue
	elif lineList[0].upper() == 'R':		elif lineList[0].upper() == 'R':
	if len(lineList)>1:		if len(lineList)>1:
	if (lineList[1].upper() == "ON") or (lineList[1].upper() == "1") or (lineList[1].upper() == "TRUE"):		if (lineList[1].upper() == "ON") or (lineList[1].upper() == "1") or (lineList[1].upper() == "TRUE"):
	@@ -506,6 +589,10 @@ USAGE
	vrlg_text=vrlg_text[:index+1]+"\n"+predefines		vrlg_text=vrlg_text[:index+1]+"\n"+predefines
	except:		except:
	print ("Failed to update %s - it is either missing or does not have a '%s'"%(vrlg_path,magic))		print ("Failed to update %s - it is either missing or does not have a '%s'"%(vrlg_path,magic))
			if soc_conn:
			soc_conn.send('0\n')
			soc_conn.close()
			# soc_conn=None
	continue		continue
	try:		try:
	with open (vrlg_path, "w") as vrlg_file:		with open (vrlg_path, "w") as vrlg_file:
	@@ -536,6 +623,16 @@ USAGE
	rslt= execTask(cmdLine)		rslt= execTask(cmdLine)
	if showResult:		if showResult:
	print (' Result: '+hx(rslt))		print (' Result: '+hx(rslt))
			if soc_conn:
			soc_conn.send(str(rslt)+'\n')
			soc_conn.close()
			# soc_conn=None
			continue
			if soc_conn:
			soc_conn.send('0\n')
			soc_conn.close()
			# soc_conn=None

	#http://stackoverflow.com/questions/11781265/python-using-getattr-to-call-function-with-variable-parameters		#http://stackoverflow.com/questions/11781265/python-using-getattr-to-call-function-with-variable-parameters
	#getattr(foo,bar)(params)		#getattr(foo,bar)(params)
	return 0		return 0

Admin message