correcting triggering - there was a false trigger when turning on extrenal trigger condition (a4377c71) · Commits · Elphel / x393

cocotb/x393_cocotb_03.sav

+75 −25

Original line number	Original line	Diff line number	Diff line
	[*]		[*]
	[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI		[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
	[*] Thu Nov 17 03:52:16 2016		[*] Tue Nov 22 04:53:52 2016
	[*]		[*]
	[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161116200800621.fst"		[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161121203439871.fst"
	[dumpfile_mtime] "Thu Nov 17 03:40:28 2016"		[dumpfile_mtime] "Tue Nov 22 04:52:55 2016"
	[dumpfile_size] 230939121		[dumpfile_size] 442146667
	[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"		[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"
	[timestart] 0		[timestart] 0
	[size] 1814 1171		[size] 1814 1171
	[pos] 0 0		[pos] 0 0
	*-25.389460 68867388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1		*-26.832495 36980000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
	[treeopen] x393_dut.		[treeopen] x393_dut.
	[treeopen] x393_dut.simul_sensor12bits_2_i.		[treeopen] x393_dut.simul_sensor12bits_2_i.
	[treeopen] x393_dut.simul_sensor12bits_3_i.		[treeopen] x393_dut.simul_sensor12bits_3_i.
	@@ -71,7 +71,7 @@
	[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.		[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
	[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.		[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
	[sst_width] 388		[sst_width] 388
	[signals_width] 276		[signals_width] 349
	[sst_expanded] 1		[sst_expanded] 1
	[sst_vpaned_height] 486		[sst_vpaned_height] 486
	@820		@820
	@@ -575,7 +575,6 @@ x393_dut.x393_i.timing393_i.camsync393_i.set_trig_src_w
	x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition		x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition
	x393_dut.x393_i.timing393_i.camsync393_i.set_period		x393_dut.x393_i.timing393_i.camsync393_i.set_period
	x393_dut.x393_i.timing393_i.camsync393_i.set_trig_dst_w		x393_dut.x393_i.timing393_i.camsync393_i.set_trig_dst_w
	x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_d
	x393_dut.x393_i.timing393_i.camsync393_i.pre_input_use_intern		x393_dut.x393_i.timing393_i.camsync393_i.pre_input_use_intern
	x393_dut.x393_i.timing393_i.camsync393_i.input_use_intern		x393_dut.x393_i.timing393_i.camsync393_i.input_use_intern
	x393_dut.x393_i.timing393_i.camsync393_i.master_got_pclk		x393_dut.x393_i.timing393_i.camsync393_i.master_got_pclk
	@@ -1225,7 +1224,6 @@ x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_filtered
	@22		@22
	x393_dut.x393_i.timing393_i.camsync393_i.trigger_filter_cntr[6:0]		x393_dut.x393_i.timing393_i.camsync393_i.trigger_filter_cntr[6:0]
	@28		@28
	x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_d
	x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition		x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition
	@1001200		@1001200
	-group_end		-group_end
	@@ -2565,9 +2563,9 @@ x393_dut.IMU_SDA
	x393_dut.IMU_TAPS[5:1]		x393_dut.IMU_TAPS[5:1]
	@1401200		@1401200
	-IMU_		-IMU_
	@c00200		@800200
	-camsync_ext_int		-camsync_ext_int
	@800022		@c00022
	x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]		x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
	@28		@28
	(0)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]		(0)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
	@@ -2580,7 +2578,7 @@ x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
	(7)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]		(7)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
	(8)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]		(8)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
	(9)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]		(9)x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
	@1001200		@1401200
	-group_end		-group_end
	@c00022		@c00022
	x393_dut.x393_i.timing393_i.frame_sync[3:0]		x393_dut.x393_i.timing393_i.frame_sync[3:0]
	@@ -2597,6 +2595,7 @@ x393_dut.x393_i.timing393_i.camsync393_i.cmd_a[2:0]
	x393_dut.x393_i.timing393_i.camsync393_i.cmd_we		x393_dut.x393_i.timing393_i.camsync393_i.cmd_we
	x393_dut.x393_i.timing393_i.camsync393_i.set_trig_dst_w		x393_dut.x393_i.timing393_i.camsync393_i.set_trig_dst_w
	x393_dut.x393_i.timing393_i.camsync393_i.en		x393_dut.x393_i.timing393_i.camsync393_i.en
			x393_dut.x393_i.timing393_i.camsync393_i.en_pclk
	x393_dut.x393_i.timing393_i.camsync393_i.pclk		x393_dut.x393_i.timing393_i.camsync393_i.pclk
	@8022		@8022
	x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]		x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
	@@ -2605,7 +2604,10 @@ x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr_run[1:0]
	@28		@28
	(0)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr_run[1:0]		(0)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr_run[1:0]
	(1)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr_run[1:0]		(1)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr_run[1:0]
			x393_dut.x393_i.timing393_i.camsync393_i.start0
			x393_dut.x393_i.timing393_i.camsync393_i.start_d
	x393_dut.x393_i.timing393_i.camsync393_i.start_en		x393_dut.x393_i.timing393_i.camsync393_i.start_en
			x393_dut.x393_i.timing393_i.camsync393_i.rep_en
	@800028		@800028
	x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]		x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
	@28		@28
	@@ -2619,7 +2621,6 @@ x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en_r[9:0]
	x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_mclk		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_mclk
	x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_pclk		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_pclk
	x393_dut.x393_i.timing393_i.camsync393_i.ext_int_trigger_condition		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_trigger_condition
	x393_dut.x393_i.timing393_i.camsync393_i.ext_int_trigger_condition_d
	@22		@22
	x393_dut.x393_i.timing393_i.camsync393_i.ext_int_trigger_filter_cntr[6:0]		x393_dut.x393_i.timing393_i.camsync393_i.ext_int_trigger_filter_cntr[6:0]
	@28		@28
	@@ -2630,10 +2631,8 @@ x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]
	@28		@28
	(0)x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]		(0)x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]
	(1)x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]		(1)x393_dut.x393_i.timing393_i.camsync393_i.ext_int_arm[1:0]
	x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition
	x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_filtered
	@22		@22
	x393_dut.x393_i.timing393_i.camsync393_i.input_pattern[9:0]		x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
	@c00022		@c00022
	x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]		x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
	@28		@28
	@@ -2649,11 +2648,64 @@ x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
	(9)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]		(9)x393_dut.x393_i.timing393_i.camsync393_i.input_use[9:0]
	@1401200		@1401200
	-group_end		-group_end
			@22
			x393_dut.x393_i.timing393_i.camsync393_i.input_pattern[9:0]
			@28
			x393_dut.x393_i.timing393_i.camsync393_i.input_use_intern
			@22
			x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_mask_w[9:0]
			@28
			x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition
			x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_filtered
			@29
			x393_dut.x393_i.timing393_i.camsync393_i.rcv_run_or_deaf
			@28
			x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_pclk
			x393_dut.x393_i.timing393_i.camsync393_i.triggered_mode
			@22
			x393_dut.x393_i.timing393_i.camsync393_i.repeat_period[31:0]
			@c00022
			x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			@28
			(0)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(1)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(2)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(3)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(4)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(5)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(6)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(7)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(8)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(9)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(10)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(11)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(12)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(13)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(14)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(15)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(16)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(17)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(18)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(19)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(20)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(21)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(22)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(23)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(24)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(25)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(26)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(27)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(28)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(29)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(30)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			(31)x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
			@1401200
			-group_end
	@1001200		@1001200
	-group_end		-group_end
	-group_end		-group_end
	-group_end		-group_end
	@1401200		@1000200
	-camsync_ext_int		-camsync_ext_int
	@800200		@800200
	-sequencers_0		-sequencers_0
	@@ -2758,8 +2810,9 @@ x393_dut.x393_i.sof_out_mclk[3:0]
	(3)x393_dut.x393_i.sof_out_mclk[3:0]		(3)x393_dut.x393_i.sof_out_mclk[3:0]
	@1401200		@1401200
	-group_end		-group_end
	@800200		@c00200
	-jpeg3		-jpeg3
			@800200
	-memsensor3		-memsensor3
	@22		@22
	x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_linear_wr_sensor_i.window_height[16:0]		x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_linear_wr_sensor_i.window_height[16:0]
	@@ -2863,7 +2916,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuf
	x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_in		x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_in
	x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.flush_hclk		x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.flush_hclk
	x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.irq		x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.irq
	@23		@22
	x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.frame_num_compressed[3:0]		x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.frame_num_compressed[3:0]
	@c00200		@c00200
	-bit_stuffer_27_32		-bit_stuffer_27_32
	@@ -2903,9 +2956,8 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuf
	-		-
	@1401200		@1401200
	-bit_stuffer_27_32		-bit_stuffer_27_32
	@1000200
	-jpeg3		-jpeg3
	@800200		@c00200
	-jpeg2		-jpeg2
	@28		@28
	x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.chn_en		x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.chn_en
	@@ -3016,9 +3068,8 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuf
	-		-
	@1401200		@1401200
	-bit_stuffer		-bit_stuffer
	@1000200
	-jpeg2		-jpeg2
	@800200		@c00200
	-jpeg1		-jpeg1
	@28		@28
	x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_tiled_rd_compressor_i.chn_en		x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_tiled_rd_compressor_i.chn_en
	@@ -3064,9 +3115,9 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuf
	@28		@28
	x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0]		x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0]
	x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv		x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv
	@1000200		@1401200
	-jpeg1		-jpeg1
	@800200		@c00200
	-jpeg0		-jpeg0
	@28		@28
	x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_rst		x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_rst
	@@ -3140,7 +3191,6 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf
	-		-
	@1401200		@1401200
	-bit_stuffer		-bit_stuffer
	@1000200
	-jpeg0		-jpeg0
	[pattern_trace] 1		[pattern_trace] 1
	[pattern_trace] 0		[pattern_trace] 0

fpga_version.vh

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -35,7 +35,8 @@
	* contains all the components and scripts required to completely simulate it		* contains all the components and scripts required to completely simulate it
	* with at least one of the Free Software programs.		* with at least one of the Free Software programs.
	*/		*/
	parameter FPGA_VERSION = 32'h039300d1; //parallel - removed extra debug -0.042/9 80.34%		parameter FPGA_VERSION = 32'h039300d2; //parallel - fixing false trigger on input condition change -0.018/21, 80.28 %
			// parameter FPGA_VERSION = 32'h039300d1; //parallel - removed extra debug -0.042/9 80.34%
	// parameter FPGA_VERSION = 32'h039300d1; //parallel - changing line_numbers_sync condition -0.011/3, 80.78 %		// parameter FPGA_VERSION = 32'h039300d1; //parallel - changing line_numbers_sync condition -0.011/3, 80.78 %
	// parameter FPGA_VERSION = 32'h039300d0; //parallel - more status data		// parameter FPGA_VERSION = 32'h039300d0; //parallel - more status data
	// parameter FPGA_VERSION = 32'h039300cf; //parallel - more status data for debugging ddr3_clk_div -0.033/2, 80.94%		// parameter FPGA_VERSION = 32'h039300cf; //parallel - more status data for debugging ddr3_clk_div -0.033/2, 80.94%

py393/x393_jpeg.py

+7 −3

Original line number	Original line	Diff line number	Diff line
	@@ -2530,7 +2530,10 @@ jpeg_sim_multi 4
	./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777		./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
	measure_all "*DI"		measure_all "*DI"
	setup_all_sensors True None 0xf		setup_all_sensors True None 0xf
	#set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?		#setup_all_sensors True None 0xf False None None None None 0 1 5 # JP4
			setup_all_sensors True None 0xf False None None None None 0 1 0 # JPEG

			set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?

	#use EOF instead of SOF for i2c sequencer advance		#use EOF instead of SOF for i2c sequencer advance
	set_sensor_i2c_command all False None None None None None None True		set_sensor_i2c_command all False None None None None None None True
	@@ -2549,7 +2552,7 @@ set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"

	reset_camsync_inout 1 # reset all outputs		reset_camsync_inout 1 # reset all outputs
	set_camsync_period 31 # set bit duration		set_camsync_period 31 # set bit duration
	set_camsync_period 10000 # 100 usec		#set_camsync_period 10000 # 100 usec
	set_camsync_delay 0 400		set_camsync_delay 0 400
	set_camsync_delay 1 1000		set_camsync_delay 1 1000
	set_camsync_delay 2 2000		set_camsync_delay 2 2000
	@@ -2562,6 +2565,7 @@ set_camsync_inout 0 7 0

	#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>		#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
	set_camsync_mode 1 1 1 1 0 0xf		set_camsync_mode 1 1 1 1 0 0xf
			set_camsync_period 10000 # 100 usec # and start

py393/x393_sens_cmprs.py

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -442,7 +442,7 @@ class X393SensCmprs(object):
	# frame_start_address, # calculate through num_sensor, num frames, frame size and start addr?		# frame_start_address, # calculate through num_sensor, num frames, frame size and start addr?
	# frame_start_address_inc,		# frame_start_address_inc,
	last_buf_frame = 1, # - just 2-frame buffer		last_buf_frame = 1, # - just 2-frame buffer
	cmode = vrlg.CMPRS_CBIT_CMODE_JPEG18,		cmode = 0, # vrlg.CMPRS_CBIT_CMODE_JPEG18,
	colorsat_blue = 0x120, # 0x90 fo 1x		colorsat_blue = 0x120, # 0x90 fo 1x
	colorsat_red = 0x16c, # 0xb6 for x1		colorsat_red = 0x16c, # 0xb6 for x1
	clk_sel = 1, # 1		clk_sel = 1, # 1
	@@ -1141,7 +1141,7 @@ class X393SensCmprs(object):

	def setup_compressor(self,		def setup_compressor(self,
	chn,		chn,
	cmode = vrlg.CMPRS_CBIT_CMODE_JPEG18,		cmode = 0, # vrlg.CMPRS_CBIT_CMODE_JPEG18,
	bayer = 0,		bayer = 0,
	qbank = 0,		qbank = 0,
	dc_sub = 1,		dc_sub = 1,
	@@ -1413,7 +1413,7 @@ class X393SensCmprs(object):
	window_top = None, # 0, # 0? 1?		window_top = None, # 0, # 0? 1?
	compressor_left_margin = 0, #0?`1?		compressor_left_margin = 0, #0?`1?
	last_buf_frame = 1, # - just 2-frame buffer		last_buf_frame = 1, # - just 2-frame buffer
	cmode = vrlg.CMPRS_CBIT_CMODE_JPEG18,		cmode = 0, # vrlg.CMPRS_CBIT_CMODE_JPEG18,
	colorsat_blue = 0x120, # 0x90 fo 1x		colorsat_blue = 0x120, # 0x90 fo 1x
	colorsat_red = 0x16c, # 0xb6 for x1		colorsat_red = 0x16c, # 0xb6 for x1
	clk_sel = 1, # 1		clk_sel = 1, # 1

timing/camsync393.v

+21 −11

Original line number	Original line	Diff line number	Diff line
	@@ -263,9 +263,11 @@ module camsync393 #(
	reg [31:0] restart_cntr; // restart period counter		reg [31:0] restart_cntr; // restart period counter
	reg [1:0] restart_cntr_run; // restart counter running		reg [1:0] restart_cntr_run; // restart counter running
	wire restart; // restart out sync		wire restart; // restart out sync
			wire [9:0] trigger_condition_mask_w; // which bits to watch for the trigger condition
	reg trigger_condition; // GPIO input trigger condition met		reg trigger_condition; // GPIO input trigger condition met
	reg trigger_condition_d; // GPIO input trigger condition met, delayed (for edge detection)		reg [1:0] trigger_condition_d; // GPIO input trigger condition met, delayed (for edge detection)
	reg trigger_condition_filtered; // trigger condition filtered		reg trigger_condition_filtered; // trigger condition filtered
			reg trigger_condition_filtered_d; // trigger condition filtered delayed (to detect leading edge)
	reg [6:0] trigger_filter_cntr;		reg [6:0] trigger_filter_cntr;
	reg [3:0] trig_r;		reg [3:0] trig_r;
	wire [3:0] trig_r_mclk;		wire [3:0] trig_r_mclk;
	@@ -347,7 +349,7 @@ module camsync393 #(
	reg ext_int_mode_pclk;		reg ext_int_mode_pclk;

	reg ext_int_trigger_condition; // GPIO input trigger condition met		reg ext_int_trigger_condition; // GPIO input trigger condition met
	reg ext_int_trigger_condition_d; // GPIO input trigger condition met, delayed (for edge detection)		reg [1:0] ext_int_trigger_condition_d; // GPIO input trigger condition met, delayed (for edge detection)
	reg ext_int_trigger_condition_filtered; // trigger condition filtered		reg ext_int_trigger_condition_filtered; // trigger condition filtered
	reg ext_int_trigger_condition_filtered_d; // trigger condition filtered - delayed version		reg ext_int_trigger_condition_filtered_d; // trigger condition filtered - delayed version
	reg [6:0] ext_int_trigger_filter_cntr;		reg [6:0] ext_int_trigger_filter_cntr;
	@@ -633,35 +635,43 @@ module camsync393 #(
	/// if the trigger pulses continue to come.		/// if the trigger pulses continue to come.

	assign pre_rcv_error= (sr_rcv_first[31:26]!=CAMSYNC_PRE_MAGIC) \|\| (sr_rcv_second[5:0]!=CAMSYNC_POST_MAGIC);		assign pre_rcv_error= (sr_rcv_first[31:26]!=CAMSYNC_PRE_MAGIC) \|\| (sr_rcv_second[5:0]!=CAMSYNC_POST_MAGIC);
			assign trigger_condition_mask_w = input_use[9:0] & ~(ext_int_mode_pclk?(10'b1 << CAMSYNC_GPIO_EXT_IN):10'b0);

	always @ (posedge pclk) begin		always @ (posedge pclk) begin

	triggered_mode_pclk<= triggered_mode_r;		triggered_mode_pclk<= triggered_mode_r;
	bit_length_short[7:0] <= bit_length[7:0]-bit_length_plus1[7:2]-1; // 3/4 of the duration		bit_length_short[7:0] <= bit_length[7:0]-bit_length_plus1[7:2]-1; // 3/4 of the duration

	// trigger_condition <= (((gpio_in[9:0] ^ input_pattern[9:0]) & input_use[9:0]) == 10'b0);		// trigger_condition <= (((gpio_in[9:0] ^ input_pattern[9:0]) & input_use[9:0]) == 10'b0);
	trigger_condition <= (((gpio_in[9:0] ^ input_pattern[9:0]) & input_use[9:0] &		// trigger_condition <= (((gpio_in[9:0] ^ input_pattern[9:0]) & input_use[9:0] &
	~(ext_int_mode_pclk?(10'b1 << CAMSYNC_GPIO_EXT_IN):10'b0)) == 10'b0); // disable external trigger in line		// ~(ext_int_mode_pclk?(10'b1 << CAMSYNC_GPIO_EXT_IN):10'b0)) == 10'b0); // disable external trigger in line
	trigger_condition_d <= trigger_condition;
			// trigger_condition_mask_w is @ mclk, but input signal is asynchronous too, so filtering is needed anyway)
			trigger_condition <= (\|trigger_condition_mask_w) && (((gpio_in[9:0] ^ input_pattern[9:0]) & trigger_condition_mask_w) == 10'b0); // disable external trigger in line

			trigger_condition_d <= {trigger_condition_d[0], trigger_condition};

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