Commit a2528fa9 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

generated bitstream for the HiSPI sesnor

parent 05656146

.settings/com.elphel.vdt.VivadoBitstream.prefs

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VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->

VivadoBitstream_@_force=true

VivadoBitstream_@_rawfile=x393_parallel

VivadoBitstream_@_rawfile=x393_hispi

com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->

eclipse.preferences.version=1

fpga_version.vh

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@@ -35,7 +35,8 @@ 
 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

        parameter FPGA_VERSION =          32'h039300bc;      //parallel, 100kHz min i2c speed -0.076/8, 79.69%

        parameter FPGA_VERSION =          32'h039300bd;      //hispi,  trying the same -0.173/36, 80.95%

//      parameter FPGA_VERSION =          32'h039300bc;      //parallel, 100kHz min i2c speed -0.076/8, 79.69%

//      parameter FPGA_VERSION =          32'h039300bb;      //parallel, adding i2c almost full. -0.101/8, 79.37%

//      parameter FPGA_VERSION =          32'h039300ba;      //parallel, fixing introduced by debug bug in sens_parallel12.v: met, 80.03%

//      parameter FPGA_VERSION =          32'h039300b9;      //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64%

system_defines.vh

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@@ -64,7 +64,7 @@ 
  `define PRELOAD_BRAMS

  `define DISPLAY_COMPRESSED_DATA  

  // if HISPI is not defined, parallel sensor interface is used for all channels

//  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/

  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/

//    `define USE_OLD_XDCT393  

//  `define USE_PCLK2X

//  `define USE_XCLK2X

x393_hispi.bit

+5.7 MiB (5.7 MiB)

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