Commit 9bc20efc authored by Andrey Filippov's avatar Andrey Filippov
Browse files

re-generated bitfiles

parent 752e66c6

.settings/com.elphel.vdt.VivadoBitstream.prefs

+1 −1
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VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->

VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->

VivadoBitstream_@_force=true

VivadoBitstream_@_force=true

VivadoBitstream_@_rawfile=x393_hispi

VivadoBitstream_@_rawfile=x393_parallel

com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->

com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->

eclipse.preferences.version=1
 
eclipse.preferences.version=1

fpga_version.vh

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@@ -35,7 +35,9 @@ 
 * contains all the components and scripts required to completely simulate it

 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 * with at least one of the Free Software programs.

 */

 */

          parameter FPGA_VERSION =          32'h039300a2;      // hispi trying default placement 81.39% not met by -0.183

          parameter FPGA_VERSION =          32'h039300a4;      // parallel 79.66, -0.1

//          parameter FPGA_VERSION =          32'h039300a3;      // hispi, after minor interface changes (separated control bits)80.52% -0.163

//          parameter FPGA_VERSION =          32'h039300a2;      // hispi trying default placement 81.39% not met by -0.183

//          parameter FPGA_VERSION =          32'h039300a1;      // hispi 81.19%, not met by -0.07

//          parameter FPGA_VERSION =          32'h039300a1;      // hispi 81.19%, not met by -0.07

//        parameter FPGA_VERSION =          32'h039300a0;      // parallel, re-ran after bug fix, %79.38%, not met -0.072

//        parameter FPGA_VERSION =          32'h039300a0;      // parallel, re-ran after bug fix, %79.38%, not met -0.072

//        parameter FPGA_VERSION =          32'h039300a0;    // parallel, else same as 9f 78.91%, not met by -0.032

//        parameter FPGA_VERSION =          32'h039300a0;    // parallel, else same as 9f 78.91%, not met by -0.032

system_defines.vh

+1 −1
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@@ -63,7 +63,7 @@ 
  `define PRELOAD_BRAMS

  `define PRELOAD_BRAMS

  `define DISPLAY_COMPRESSED_DATA  

  `define DISPLAY_COMPRESSED_DATA  

  // if HISPI is not defined, parallel sensor interface is used for all channels

  // if HISPI is not defined, parallel sensor interface is used for all channels

  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/

//  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/

//    `define USE_OLD_XDCT393  

//    `define USE_OLD_XDCT393  

//  `define USE_PCLK2X

//  `define USE_PCLK2X

//  `define USE_XCLK2X

//  `define USE_XCLK2X

timing/timing393.v

+2 −1
Original line number Original line Diff line number Diff line
@@ -58,7 +58,8 @@ module timing393 #( 
    parameter CAMSYNC_EXTERNAL_BIT =            'h5, // enable writing ts_external (0 - local timestamp in the frame header)

    parameter CAMSYNC_EXTERNAL_BIT =            'h5, // enable writing ts_external (0 - local timestamp in the frame header)

    parameter CAMSYNC_TRIGGERED_BIT =           'h7, // triggered mode ( 0- async)

    parameter CAMSYNC_TRIGGERED_BIT =           'h7, // triggered mode ( 0- async)

    parameter CAMSYNC_MASTER_BIT =              'ha, // select a 2-bit master channel (master delay may be used as a flash delay)

    parameter CAMSYNC_MASTER_BIT =              'ha, // select a 2-bit master channel (master delay may be used as a flash delay)

    parameter CAMSYNC_CHN_EN_BIT =              'hf, // per-channel enable timestamp generation

//    parameter CAMSYNC_CHN_EN_BIT =              'hf, // per-channel enable timestamp generation

    parameter CAMSYNC_CHN_EN_BIT =              'h12, // per-channel enable timestamp generation (4 bits themselves, then for enables for them)

    parameter CAMSYNC_PRE_MAGIC =               6'b110100,

    parameter CAMSYNC_PRE_MAGIC =               6'b110100,

    parameter CAMSYNC_POST_MAGIC =              6'b001101,

    parameter CAMSYNC_POST_MAGIC =              6'b001101,

x393_hispi.bit

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