Commit 9b620b6b authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Debugging vospi mode, fpga: 0x03930133

parent 465135b4

cocotb/x393_cocotb_lwir_04.sav

+47 −8
Original line number Diff line number Diff line 
[*]

[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI

[*] Thu Apr 25 23:42:15 2019

[*] Tue Apr 30 17:21:50 2019

[*]

[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190425172733675.fst"

[dumpfile_mtime] "Thu Apr 25 23:38:14 2019"

[dumpfile_size] 13065486

[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190430003141791.fst"

[dumpfile_mtime] "Tue Apr 30 17:20:36 2019"

[dumpfile_size] 1896466138

[savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_lwir_04.sav"

[timestart] 34144200

[timestart] 0

[size] 1804 1171

[pos] -1 -1

*-14.717531 34226035 1019686803 237352388 855469045 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

*-28.897251 1413970273 1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] x393_dut.

[treeopen] x393_dut.simul_lwir160x120_vospi1_i.

[treeopen] x393_dut.x393_i.
@@ -2771,7 +2771,9 @@ x393_dut.simul_lwir160x120_vospi1_i.start_segm_rd 
x393_dut.simul_lwir160x120_vospi1_i.readout_word_indx[6:0]

@28

x393_dut.simul_lwir160x120_vospi1_i.readout_pre_last_bit

@22

x393_dut.simul_lwir160x120_vospi1_i.readout_segment[1:0]

@28

x393_dut.simul_lwir160x120_vospi1_i.spi_cs

x393_dut.simul_lwir160x120_vospi1_i.packet_sent

x393_dut.simul_lwir160x120_vospi1_i.readout_last_packet
@@ -2808,6 +2810,7 @@ x393_dut.simul_lwir160x120_vospi1_i.readout_sr_good[15:0] 
@1401200

-group_end

@22

[color] 2

x393_dut.simul_lwir160x120_vospi1_i.readout_sr_good_dbg[15:0]

@28

x393_dut.simul_lwir160x120_vospi1_i.readout_good
@@ -3071,13 +3074,47 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto 
@800200

-vospi_segment61_0

@28

[color] 3

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.start_d

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.we

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.waddr[10:0]

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_dout[15:0]

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_running

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_dv

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.discard_segment_r

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_start_waddr[10:0]

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_start_packet[7:0]

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.full_packet[7:0]

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_running

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.discard_segment_r

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_stb

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_good_w

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.discard_set

@200

-

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.sof_w

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.raddr[10:0]

@29

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.hact_r[2:0]

@800200

-packet

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.dv_r

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.dout[15:0]

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.set_d_r

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_invalid

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.will_sync

@1000200

-packet

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.start_out_frame_w

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.sof_w

@22
@@ -3157,6 +3194,10 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto 
-group_end

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_done

@22

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_dout[15:0]

@28

x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_dv

@800200

-vospi_packet80_0

@28
@@ -3302,9 +3343,7 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto 
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]

@28

(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]

@29

(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]

@28

(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]

(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]

(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]

fpga_version.vh

+6 −1
Original line number Diff line number Diff line
@@ -35,7 +35,12 @@ 
 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

        parameter FPGA_VERSION =          32'h0393012e;      // re-arranged control bits, added telemetry on/off

        parameter FPGA_VERSION =          32'h03930133;      // Testing sof to hact delay

//        parameter FPGA_VERSION =          32'h03930132;      // Sync from serial bumber start, added output (with hact)

//        parameter FPGA_VERSION =          32'h03930131;      // Sync from serial bumber start

//        parameter FPGA_VERSION =          32'h03930130;      // Adding output for receive start frame

//        parameter FPGA_VERSION =          32'h0393012f;      // debugging resync on othjer sesnor

//        parameter FPGA_VERSION =          32'h0393012e;      // re-arranged control bits, added telemetry on/off

//        parameter FPGA_VERSION =          32'h0393012d;      // debugging - working sync

//        parameter FPGA_VERSION =          32'h0393012c;      // debugging - working sync

//      parameter FPGA_VERSION =          32'h0393012b;      // debugging

includes/x393_parameters.vh

+3 −3
Original line number Diff line number Diff line
@@ -585,7 +585,7 @@ 
    parameter VOSPI_SOF_TO_HACT =     1000,  // clock cycles from SOF to HACT

    parameter VOSPI_HACT_TO_HACT_EOF =1000,  // pixel clock is 480 MHz, need to slow down for memory

`else

    parameter VOSPI_SOF_TO_HACT =        10,  // clock cycles from SOF to HACT

    parameter VOSPI_SOF_TO_HACT =      100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)

    parameter VOSPI_HACT_TO_HACT_EOF =   2,  // minimal clock cycles from HACT to HACT or to EOF

`endif    

    parameter VOSPI_MCLK_HALFDIV =       4,  // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock

py393/x393_sensor.py

+1 −1
Original line number Diff line number Diff line
@@ -1104,7 +1104,7 @@ class X393Sensor(object): 
        @param vsync_use =  Wait for VSYNC (should be enabled over i2c) before reading each segment

        @param noresync =   Disable resynchronization by discard packets

        @param dbg_src =    source of the hardware debug output: 0 - dbg_running

                                                                 1 - vsync_rdy[0]

                                                                 1 - will_sync

                                                                 2 - vsync_rdy[1]

                                                                 3 - discard_segment

                                                                 4 - in_busy

sensor/sens_lepton3.v

+16 −11
Original line number Diff line number Diff line
@@ -140,7 +140,7 @@ module sens_lepton3 #( 
    parameter VOSPI_PACKET_FIRST =     0,

    parameter VOSPI_PACKET_LAST =     60,

    parameter VOSPI_PACKET_TTT =      20,  // line number where segment number is provided

    parameter VOSPI_SOF_TO_HACT =      2,  // clock cycles from SOF to HACT

    parameter VOSPI_SOF_TO_HACT =    100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)

    parameter VOSPI_HACT_TO_HACT_EOF = 2,  // minimal clock cycles from HACT to HACT or to EOF

    parameter VOSPI_MCLK_HALFDIV =     4   // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock

)(
@@ -202,6 +202,7 @@ module sens_lepton3 #( 
    wire                         dbg_segment_stb;

    wire                         dbg_will_sync;

    wire                  [4:0]  dbg_state;

    wire                         dbg_frame_start;   // output //from receiving first packet to SOF

    wire                         crc_err_w;  // single-cycle CRC error

    reg                          crc_err_r;  // at least one CRC error happened since reset

    wire                         sync_err_w;  // single-cycle synchronzation error
@@ -280,8 +281,8 @@ module sens_lepton3 #( 
    wire        mipi_dn_int;

    wire        mipi_clkp_int;

    wire        mipi_clkn_int;

    

    

    wire        dbg_tel_sync; // certain 32 bits in the telemetry

    wire        dbg_tel_sync_out;

// temporary?

    assign fake_in = sns_ctl_int ^ mipi_dp_int ^ mipi_dn_int ^ mipi_clkp_int ^ mipi_clkn_int ^ fake_dp2 ^ fake_dn2 ^ fake_dn6;
@@ -309,12 +310,12 @@ module sens_lepton3 #( 
                             

    assign dbg_sources[0] =   dbg_running;

    assign dbg_sources[1] =   dbg_will_sync;    //

    assign dbg_sources[2] =   dbg_vsync_rdy[1]; //

    assign dbg_sources[2] =   dbg_state[3];     // dbg_vsync_rdy[1]; //

    assign dbg_sources[3] =   discard_segment;  // dbg_state[0]; //

    assign dbg_sources[4] =   in_busy;          // dbg_state[1]; //

    assign dbg_sources[5] =   out_busy;         // dbg_state[2]; //  

    assign dbg_sources[4] =   dbg_tel_sync_out; // in_busy;          // dbg_state[2];     // in_busy;          // dbg_state[1]; //

    assign dbg_sources[5] =   dbg_frame_start;  // out_busy;         // dbg_state[2]; //  

    assign dbg_sources[6] =   hact;             // dbg_state[3]; //  

    assign dbg_sources[7] =   sof;              // dbg_state[4]; //  

    assign dbg_sources[7] =   dbg_tel_sync;     // sof;              // dbg_state[4]; //  



//dbg_will_sync dbg_state
@@ -687,7 +688,7 @@ module sens_lepton3 #( 
        .VOSPI_PACKET_FIRST     (VOSPI_PACKET_FIRST),     //  0

        .VOSPI_PACKET_LAST      (VOSPI_PACKET_LAST),      // 60

        .VOSPI_PACKET_TTT       (VOSPI_PACKET_TTT),       // 20

        .VOSPI_SOF_TO_HACT      (VOSPI_SOF_TO_HACT),      //  2

        .VOSPI_SOF_TO_HACT      (VOSPI_SOF_TO_HACT),      //100

        .VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF)  //  2

    ) vospi_segment_61_i (

        .rst             (!spi_nrst_pclk[1]),   // input
@@ -718,7 +719,11 @@ module sens_lepton3 #( 
        .dbg_vsync_rdy   (dbg_vsync_rdy),    // output[1:0]'

        .dbg_segment_stb (dbg_segment_stb),  // output 

        .dbg_will_sync   (dbg_will_sync),    // output

        .dbg_state       (dbg_state) // output[4:0]         

        .dbg_state       (dbg_state),        // output[4:0]

        .dbg_frame_start (dbg_frame_start),  // output //from receiving first packet to SOF

        .dbg_tel_sync    (dbg_tel_sync),      // output[4:0] certain 32 bits in telemetry data

        .dbg_tel_sync_out(dbg_tel_sync_out)      // output[4:0] certain 32 bits in telemetry data

                 

        

    );

    cmd_deser #(