4-image acquisition with parallel sensors, re-tested (9a7f17fa) · Commits · Elphel / x393

py393/x393_export_c.py

+2 −2

Original line number	Diff line number	Diff line
		@@ -385,7 +385,7 @@ class X393ExportC(object):
		frmt_spcs = frmt_spcs)
		stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
		data = self._enc_sensio_jtag(),
		name = "x393_sensio_jpag", typ="wo",
		name = "x393_sensio_jtag", typ="wo",
		frmt_spcs = frmt_spcs)
		"""
		stypedefs += self.get_typedef32(comment = "Sensor delays (uses 4 DWORDs)",
		@@ -754,7 +754,7 @@ class X393ExportC(object):
		(("X393_SENS_SYNC_LATE", c, vrlg.SENS_SYNC_RADDR + vrlg.SENS_SYNC_LATE + ba, ia, z3, "x393_sens_sync_late", "wo", "Configure frame sync delay")),
		(("X393_SENSIO_CTRL", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL + ba, ia, z3, "x393_sensio_ctl", "wo", "Configure sensor I/O port")),
		(("X393_SENSIO_STATUS_CNTRL", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_STATUS + ba, ia, z3, "x393_status_ctrl", "rw", "Set status control for SENSIO module")),
		(("X393_SENSIO_JTAG", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_JTAG + ba, ia, z3, "x393_sensio_jpag", "wo", "Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)")),
		(("X393_SENSIO_JTAG", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_JTAG + ba, ia, z3, "x393_sensio_jtag", "wo", "Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)")),
		(("X393_SENSIO_WIDTH", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_WIDTH + ba, ia, z3, "x393_sensio_width", "rw", "Set sensor line in pixels (0 - use line sync from the sensor)")),
		# (("X393_SENSIO_DELAYS", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS + ba, ia, z3, "x393_sensio_dly", "rw", "Sensor port input delays (uses 4 DWORDs)")),
		(("X393_SENSIO_TIM0", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS + 0 + ba, ia, z3, "x393_sensio_tim0", "rw", "Sensor port i/o timing configuration, register 0")),

py393/x393_jpeg.py

+57 −1

Original line number	Diff line number	Diff line
		@@ -828,7 +828,7 @@ class X393Jpeg(object):
		y_quality = y_quality, #80,
		c_quality = c_quality,
		portrait = portrait,
		color_mode = window["cmode"], #
		# color_mode = window["cmode"], #
		byrshift = byrshift,
		verbose = verbose)
		html_text += html_text_finish
		@@ -965,6 +965,62 @@ class X393Jpeg(object):
		ff d9
		"""
		"""
		################## Parallel ##################
		cd /usr/local/verilog/; test_mcntrl.py @hargs
		setupSensorsPower "PAR12"
		measure_all "*DI"
		setup_all_sensors True None 0xf
		#set quadrants
		set_sensor_io_ctl 0 None None None None None 0 0xe
		set_sensor_io_ctl 1 None None None None None 0 0xe
		set_sensor_io_ctl 2 None None None None None 0 0x4
		set_sensor_io_ctl 3 None None None None None 0 0xe
		# Set Bayer = 3 (probably #1 and #3 need different hact/pxd delays to use the same compressor bayer for all channels)
		compressor_control all None None None None None 3

		#Get rid of the corrupted last pixel column
		#longer line (default 0xa1f)
		write_sensor_i2c all 1 0 0x90040a23
		#increase scanline write (memory controller) width in 16-bursts (was 0xa2)
		axi_write_single_w 0x696 0x079800a3
		axi_write_single_w 0x686 0x079800a3
		axi_write_single_w 0x6a6 0x079800a3
		axi_write_single_w 0x6b6 0x079800a3

		#Gamma 0.57
		program_gamma all 0 0.57 0.04

		#colors - outdoor
		write_sensor_i2c all 1 0 0x9035000a
		write_sensor_i2c all 1 0 0x902c000e
		write_sensor_i2c all 1 0 0x902d000d

		#colors indoor
		write_sensor_i2c all 1 0 0x90350009
		write_sensor_i2c all 1 0 0x902c000f
		write_sensor_i2c all 1 0 0x902d000a

		#exposure 0x100 lines (default was 0x797)
		write_sensor_i2c all 1 0 0x90090100

		#exposure 0x797 (default)
		write_sensor_i2c all 1 0 0x90090797


		#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
		compressor_control all 2

		jpeg_write "img.jpeg" 0
		#jpeg_write "img.jpeg" All

		#changing quality (example 85%):
		set_qtables all 0 85
		compressor_control all 2
		#jpeg_write "img.jpeg" all 85
		jpeg_write "img.jpeg" 0 85


		################## Serial ####################
		cd /usr/local/verilog/; test_mcntrl.py @hargs
		setupSensorsPower "HISPI"
		measure_all "*DI"

py393/x393_sens_cmprs.py

+16 −6

Original line number	Diff line number	Diff line
		@@ -188,11 +188,18 @@ class X393SensCmprs(object):
		print(voltage_mv, file = f)
		if quiet == 0:
		print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv))
		# time.sleep(0.1)
		time.sleep(0.1)

		def setupSensorsPower(self, ifaceType, quiet=0):
		for sub_pair in (0,1):
		self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
		def setupSensorsPower(self, ifaceType, pairs = "all", quiet=0):
		try:
		if (pairs == all) or (pairs[0].upper() == "A"): #all is a built-in function
		pairs = (0,1)
		except:
		pass
		if not isinstance(pairs,(list,tuple)):
		pairs = (pairs,)
		for pair in pairs:
		self.setSensorIfaceVoltagePower(pair, SENSOR_INTERFACES[ifaceType]["mv"])

		def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0):
		"""
		@@ -208,16 +215,19 @@ class X393SensCmprs(object):
		if self.DRY_MODE:
		print ("Not defined for simulation mode")
		return
		if quiet == 0:
		print ("Turning on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
		time.sleep(0.2)
		with open (POWER393_PATH + "/channels_en","w") as f:
		print(("vcc_sens01", "vcc_sens23")[sub_pair], file = f)
		if quiet == 0:
		print ("Turned on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
		# time.sleep(0.1)
		time.sleep(0.2)
		with open (POWER393_PATH + "/channels_en","w") as f:
		print(("vp33sens01", "vp33sens23")[sub_pair], file = f)
		if quiet == 0:
		print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair]))
		# time.sleep(0.1)
		time.sleep(0.2)
		# for sub_pair in (0,1):
		# self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])

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