synchronizing i2c frame number with command sequence frame number (96092048) · Commits · Elphel / x393

.project

+11 −11

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		@@ -62,52 +62,52 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160507151954677.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160508121344091.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160507151954677.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160508121344091.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160507151954677.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160508121344091.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160507151954677.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160508121344091.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160507151954677.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160508121344091.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160507151954677.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160508121344091.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160507151111576.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160508120724364.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160507151954677.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160508121344091.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160507151111576.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160508120724364.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160507151111576.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160508120724364.log</location>
		</link>
		<link>
		<name>vivado_state/x393-opt-phys.dcp</name>
		@@ -127,7 +127,7 @@
		<link>
		<name>vivado_state/x393-synth.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_state/x393-synth-20160507151111576.dcp</location>
		<location>/home/andrey/git/x393/vivado_state/x393-synth-20160508120724364.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

fpga_version.vh

+2 −1

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		@@ -32,7 +32,8 @@
		* with at least one of the Free Software programs.
		*******************************************************************************/

		parameter FPGA_VERSION = 32'h03930088; // Fixing circbuf rollover pointers bug
		parameter FPGA_VERSION = 32'h03930089; // Auto-synchronizing io2c sequencers with the command ones
		// parameter FPGA_VERSION = 32'h03930088; // Fixing circbuf rollover pointers bug (only one path violated)
		// parameter FPGA_VERSION = 32'h03930087; // Fixed default 90% quantization table
		// parameter FPGA_VERSION = 32'h03930087; // Synchronizing i2c sequencer frame number with that of a command sequencer
		// parameter FPGA_VERSION = 32'h03930086; // Adding byte-wide JTAG read to speed-up 10359 load

sensor/sensor_channel.v

+8 −1

Original line number	Diff line number	Diff line
		@@ -198,6 +198,8 @@ module sensor_channel#(
		parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
		parameter SENSI2C_SLEW = "SLOW",

		parameter NUM_FRAME_BITS = 4,

		`ifndef HISPI
		//sensor_fifo parameters
		parameter SENSOR_DATA_WIDTH = 12,
		@@ -322,6 +324,9 @@ module sensor_channel#(
		input trigger_mode, // running in triggered mode (0 - free running mode)
		input trig_in, // per-sensor trigger input

		input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c)


		// 16/8-bit mode data to memory (8-bits are packed by 2 in 16 mode @posedge pclk
		output [15:0] dout, // @posedge pclk
		output dout_valid, // in 8-bit mode continues pixel flow have dout_valid alternating on/off
		@@ -637,7 +642,8 @@ module sensor_channel#(
		.SENSI2C_DRIVE (SENSI2C_DRIVE),
		.SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
		.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
		.SENSI2C_SLEW (SENSI2C_SLEW)
		.SENSI2C_SLEW (SENSI2C_SLEW),
		.NUM_FRAME_BITS (NUM_FRAME_BITS)
		) sensor_i2c_io_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		@@ -647,6 +653,7 @@ module sensor_channel#(
		.status_rq (sens_i2c_status_rq), // output
		.status_start (sens_i2c_status_start), // input
		.frame_sync (sof_out_mclk), // input
		.frame_num_seq (frame_num_seq), // input[3:0]
		.scl (sns_scl), // inout
		.sda (sns_sda) // inout
		);

sensor/sensor_i2c.v

+43 −24

Original line number	Diff line number	Diff line
		@@ -32,7 +32,7 @@
		* with at least one of the Free Software programs.
		*******************************************************************************/
		`timescale 1ns/1ps

		`undef I2C_FRAME_INDEPENDENT
		module sensor_i2c#(
		parameter SENSI2C_ABS_ADDR = 'h410,
		parameter SENSI2C_REL_ADDR = 'h420,
		@@ -67,7 +67,8 @@ module sensor_i2c#(
		parameter SENSI2C_TBL_NBRD_BITS = 3,
		parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
		parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
		parameter SENSI2C_TBL_DLY_BITS= 8
		parameter SENSI2C_TBL_DLY_BITS= 8,
		parameter NUM_FRAME_BITS = 4
		)(
		input mrst, // @ posedge mclk
		input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
		@@ -81,6 +82,7 @@ module sensor_i2c#(
		output status_rq, // input request to send status downstream
		input status_start,// Acknowledge of the first status packet byte (address)
		input frame_sync, // @posedge mclk increment/reset frame number
		input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c)
		input sda_in, // i2c SDA input
		input scl_in, // i2c SCL input
		output scl_out, // i2c SCL output
		@@ -178,10 +180,16 @@ module sensor_i2c#(
		wire sda_en_hard;
		wire scl_hard;

		`ifdef I2C_FRAME_INDEPENDENT
		localparam sync_to_seq = -;
		`else
		reg sync_to_seq;
		`endif

		assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0
		assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0
		assign pre_wpage0_inc = (!wen && !(\|wen_r) && !wpage0_inc[0]) && (req_clr \|\| reset_on) ;
		/// assign pre_wpage0_inc = (!wen && !(\|wen_r) && !(\|wpage0_inc)) && (req_clr \|\| reset_on) ;

		assign fifo_wr_pointers_outw = fifo_wr_pointers_ram[wpage_wr[3:0]]; // valid next after command
		assign fifo_wr_pointers_outr = fifo_wr_pointers_ram[page_r[3:0]];
		@@ -308,12 +316,18 @@ module sensor_i2c#(
		// request to clear pointer(s)? for one page - during reset or delayed frame sync (if previous was not finished)
		req_clr <= frame_sync \|\| (req_clr && !wpage0_inc[0]);

		`ifndef I2C_FRAME_INDEPENDENT
		sync_to_seq <= frame_sync \|\| (reset_on && ( wpage0[3:0] == 4'hf));
		`endif


		if (reset_cmd) wpage0 <= 0;
		// else if (frame_0) wpage0 <= 0;
		else if (wpage0_inc[0]) wpage0 <= wpage0 + 1;
		else if (sync_to_seq) wpage0 <= frame_num_seq;

		if (reset_cmd) wpage_prev <= 4'hf;
		else if (wpage0_inc[0]) wpage_prev <= wpage0;
		else if (sync_to_seq) wpage_prev <= frame_num_seq - 1 ;


		if (we_abs) wpage_wr <= ((wa==wpage_prev)? wpage0[3:0] : wa);
		@@ -333,10 +347,15 @@ module sensor_i2c#(
		i2c_cmd_we <= !reset_cmd && wen_fifo; // [0];

		// signals related to reading from i2c FIFO
		`ifdef I2C_FRAME_INDEPENDENT
		if (reset_on) page_r <= 0;
		else if (page_r_inc[0]) page_r <= page_r+1;
		`else
		if (reset_on) page_r <= frame_num_seq;
		else if (page_r_inc[0]) page_r <= page_r+1;
		`endif


		//############ rpointer should startt not from 0, but form valuie in another RAM???
		if (reset_cmd \|\| page_r_inc[0]) rpointer[5:0] <= 6'h0;
		else if (i2c_run_d && ! i2c_run) rpointer[5:0] <= rpointer[5:0] + 1;

sensor/sensor_i2c_io.v

+20 −16

Original line number	Diff line number	Diff line
		@@ -75,7 +75,8 @@ module sensor_i2c_io#(
		`else
		parameter SENSI2C_IOSTANDARD = "LVCMOS25",
		`endif
		parameter SENSI2C_SLEW = "SLOW"
		parameter SENSI2C_SLEW = "SLOW",
		parameter NUM_FRAME_BITS = 4
		)(
		input mrst, // @mclk
		input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
		@@ -85,6 +86,7 @@ module sensor_i2c_io#(
		output status_rq, // input request to send status downstream
		input status_start,// Acknowledge of the first status packet byte (address)
		input frame_sync, // increment/reset frame number
		input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c)
		inout scl,
		inout sda
		);
		@@ -126,7 +128,8 @@ module sensor_i2c_io#(
		.SENSI2C_TBL_NBRD_BITS (SENSI2C_TBL_NBRD_BITS),
		.SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
		.SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period)
		.SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS)
		.SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS),
		.NUM_FRAME_BITS (NUM_FRAME_BITS)
		) sensor_i2c_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		@@ -136,6 +139,7 @@ module sensor_i2c_io#(
		.status_rq (status_rq), // output
		.status_start (status_start), // input
		.frame_sync (frame_sync), // input
		.frame_num_seq (frame_num_seq), // input[3:0]
		.scl_in (scl_in), // input
		.sda_in (sda_in), // input
		.scl_out (scl_out), // output

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