From 901e1d6a9d1550dd2895a2a74c4f7957864bf39e Mon Sep 17 00:00:00 2001 From: Andrey Filippov Date: Tue, 29 Mar 2016 11:51:49 -0600 Subject: [PATCH] cleaned up constarints to simplify switching between sensor types --- .project | 22 ++++++++-------- .../com.elphel.vdt.VivadoSynthesis.prefs | 5 ++-- fpga_version.vh | 3 ++- x393_placement.tcl | 26 +------------------ 4 files changed, 17 insertions(+), 39 deletions(-) diff --git a/.project b/.project index 56ab0b1..f57a927 100644 --- a/.project +++ b/.project @@ -62,52 +62,52 @@ vivado_logs/VivadoBitstream.log 1 - /home/andrey/git/x393/vivado_logs/VivadoBitstream-20160329000509294.log + /home/andrey/git/x393/vivado_logs/VivadoBitstream-20160329103342970.log vivado_logs/VivadoOpt.log 1 - /home/andrey/git/x393/vivado_logs/VivadoOpt-20160329000509294.log + /home/andrey/git/x393/vivado_logs/VivadoOpt-20160329103342970.log vivado_logs/VivadoOptPhys.log 1 - /home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160329000509294.log + /home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160329103342970.log vivado_logs/VivadoOptPower.log 1 - /home/andrey/git/x393/vivado_logs/VivadoOptPower-20160329000509294.log + /home/andrey/git/x393/vivado_logs/VivadoOptPower-20160329103342970.log vivado_logs/VivadoPlace.log 1 - /home/andrey/git/x393/vivado_logs/VivadoPlace-20160329000509294.log + /home/andrey/git/x393/vivado_logs/VivadoPlace-20160329103342970.log vivado_logs/VivadoRoute.log 1 - /home/andrey/git/x393/vivado_logs/VivadoRoute-20160329000509294.log + /home/andrey/git/x393/vivado_logs/VivadoRoute-20160329103342970.log vivado_logs/VivadoSynthesis.log 1 - /home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160328235916328.log + /home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160329102811515.log vivado_logs/VivadoTimimgSummaryReportImplemented.log 1 - /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160329000509294.log + /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160329103342970.log vivado_logs/VivadoTimimgSummaryReportSynthesis.log 1 - /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160328235916328.log + /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160329102811515.log vivado_logs/VivadoTimingReportSynthesis.log 1 - /home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160328235916328.log + /home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160329102811515.log vivado_state/x393-opt-phys.dcp @@ -127,7 +127,7 @@ vivado_state/x393-synth.dcp 1 - /home/andrey/git/x393/vivado_state/x393-synth-20160328235916328.dcp + /home/andrey/git/x393/vivado_state/x393-synth-20160329102811515.dcp diff --git a/.settings/com.elphel.vdt.VivadoSynthesis.prefs b/.settings/com.elphel.vdt.VivadoSynthesis.prefs index 67e4625..53fcf62 100644 --- a/.settings/com.elphel.vdt.VivadoSynthesis.prefs +++ b/.settings/com.elphel.vdt.VivadoSynthesis.prefs @@ -7,10 +7,11 @@ VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.x VivadoSynthesis_122_SkipSnapshotSynth=true VivadoSynthesis_123_ResetProject=true VivadoSynthesis_123_SkipSnapshotSynth=true -VivadoSynthesis_124_ConstraintsFiles=x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@-> +VivadoSynthesis_124_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@-> VivadoSynthesis_127_verbose=true +VivadoSynthesis_128_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@-> VivadoSynthesis_81_parser_mode=1 VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@-> VivadoSynthesis_95_ShowInfo=true -com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_MaxMsg<-@\#\#@-> +com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_MaxMsg<-@\#\#@->VivadoSynthesis_128_PreTCL<-@\#\#@-> eclipse.preferences.version=1 diff --git a/fpga_version.vh b/fpga_version.vh index 300a584..5e3f10f 100644 --- a/fpga_version.vh +++ b/fpga_version.vh @@ -32,7 +32,8 @@ * with at least one of the Free Software programs. *******************************************************************************/ - parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc + parameter FPGA_VERSION = 32'h0393007f; // More constraints files tweaking +// parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc - timing met // parameter FPGA_VERSION = 32'h0393007d; // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers. Timing met // parameter FPGA_VERSION = 32'h0393007c; // fixed cmdseqmux - reporting interrupt status and mask correctly // parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff diff --git a/x393_placement.tcl b/x393_placement.tcl index bebdb87..629d797 100644 --- a/x393_placement.tcl +++ b/x393_placement.tcl @@ -47,31 +47,7 @@ if { $HISPI} { } else { puts "using parallel sensors" } - -# Global constraints - -set_property INTERNAL_VREF 0.750 [get_iobanks 34] -set_property DCI_CASCADE 34 [get_iobanks 35] -set_property INTERNAL_VREF 0.750 [get_iobanks 35] -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] - -# Disabling some of the DRC checks: -#http://forums.xilinx.com/t5/7-Series-FPGAs/MMCM-reference-clock-muxing/td-p/550622 -set_property is_enabled false [get_drc_checks REQP-119] -#Input Buffer Connections .. has no loads. An input buffer must drive an internal load. -set_property is_enabled false [get_drc_checks BUFC-1] -#DSP Buffering: -set_property is_enabled false [get_drc_checks DPIP-1] -set_property is_enabled false [get_drc_checks DPOP-1] -#MMCME2_ADV connectivity violation -set_property is_enabled false [get_drc_checks REQP-1577] -#Synchronous clocking for BRAM (mult_saxi_wr_inbuf_i/ram_var_w_var_r_i/ram_i/RAMB36E1_i) in SDP mode ... -set_property is_enabled false [get_drc_checks REQP-165] -#Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS. -set_property is_enabled false [get_drc_checks REQP-14] - - +#Placement constraints (I/O pads) set_property PACKAGE_PIN J4 [get_ports {SDRST}] set_property PACKAGE_PIN K3 [get_ports {SDCLK}] set_property PACKAGE_PIN K2 [get_ports {SDNCLK}] -- 2.18.1