simulating/debugging (8b79e3f7) · Commits · Elphel / x393

.project

+15 −15

Original line number	Original line	Diff line number	Diff line
	@@ -62,77 +62,77 @@
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150426202414513.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150428234740722.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150426202414513.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150428234740722.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150426202414513.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150428234740722.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150426202414513.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150428234740722.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150426202414513.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150428234740722.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150426202414513.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150428234740722.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150426202222327.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150428234540494.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150426202414513.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150428234740722.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150426202222327.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150428234540494.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportImplemented.log</name>		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150426202414513.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150428234740722.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportSynthesis.log</name>		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150426202222327.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150428234540494.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393-opt-phys.dcp</name>		<name>vivado_state/x393-opt-phys.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150426202414513.dcp</location>		<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150428234740722.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393-place.dcp</name>		<name>vivado_state/x393-place.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_state/x393-place-20150426202414513.dcp</location>		<location>/home/andrey/git/x393/vivado_state/x393-place-20150428234740722.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393-route.dcp</name>		<name>vivado_state/x393-route.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_state/x393-route-20150426202414513.dcp</location>		<location>/home/andrey/git/x393/vivado_state/x393-route-20150428234740722.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393-synth.dcp</name>		<name>vivado_state/x393-synth.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_state/x393-synth-20150426202222327.dcp</location>		<location>/home/andrey/git/x393/vivado_state/x393-synth-20150428234540494.dcp</location>
	</link>		</link>
	</linkedResources>		</linkedResources>
	</projectDescription>		</projectDescription>

axi/membridge.v

+21 −16

Original line number	Original line	Diff line number	Diff line
	@@ -23,7 +23,7 @@
	module membridge#(		module membridge#(
	parameter MEMBRIDGE_ADDR= 'h200,		parameter MEMBRIDGE_ADDR= 'h200,
	parameter MEMBRIDGE_MASK= 'h3f0,		parameter MEMBRIDGE_MASK= 'h3f0,
	parameter MEMBRIDGE_CTRL= 'h0, // bit 0 - enable, bits[2:1]: 01 - start, 11 - start and reset address		parameter MEMBRIDGE_CTRL= 'h0, // bit 0 - enable, bits[2:1]: 11 - start(continue), 01 - start and reset address
	parameter MEMBRIDGE_STATUS_CNTRL= 'h1,		parameter MEMBRIDGE_STATUS_CNTRL= 'h1,
	parameter MEMBRIDGE_LO_ADDR64= 'h2, // low address of the system memory, in 64-bit words (<<3 to get byte address)		parameter MEMBRIDGE_LO_ADDR64= 'h2, // low address of the system memory, in 64-bit words (<<3 to get byte address)
	parameter MEMBRIDGE_SIZE64= 'h3, // size of the system memory range (access will roll over to lo_addr		parameter MEMBRIDGE_SIZE64= 'h3, // size of the system memory range (access will roll over to lo_addr
	@@ -52,7 +52,7 @@ module membridge#(
	input page_ready_chn, // output single mclk		input page_ready_chn, // output single mclk
	input frame_done_chn, // output single mclk		input frame_done_chn, // output single mclk
	input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn1, // output[15:0] @SuppressThisWarning VEditor unused (yet)		input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn1, // output[15:0] @SuppressThisWarning VEditor unused (yet)
	output suspend_chn1, // input @SuppressThisWarning VEditor unused (yet)		output suspend_chn1, //
	// buffer interface, DDR3 memory read		// buffer interface, DDR3 memory read
	input xfer_reset_page_rd, // input		input xfer_reset_page_rd, // input
	input buf_wpage_nxt, // input		input buf_wpage_nxt, // input
	@@ -139,7 +139,7 @@ module membridge#(


	assign frame_start_chn = start_mclk;		assign frame_start_chn = start_mclk;
			assign suspend_chn1 = 1'b0;
	wire [ 3:0] cmd_a; // control register address		wire [ 3:0] cmd_a; // control register address
	wire [31:0] cmd_data; // register data		wire [31:0] cmd_data; // register data
	wire cmd_we; // register write		wire cmd_we; // register write
	@@ -277,7 +277,7 @@ module membridge#(
	pulse_cross_clock next_page_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(next_page), .out_pulse(next_page_chn),.busy(busy_next_page));		pulse_cross_clock next_page_i (.rst(rst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(next_page), .out_pulse(next_page_chn),.busy(busy_next_page));

	// Common to both directions		// Common to both directions
	localparam DELAY_ADVANCE_ADDR=4;		localparam DELAY_ADVANCE_ADDR=3;
	reg [28:0] rel_addr64; // realtive (to lo_addr) address		reg [28:0] rel_addr64; // realtive (to lo_addr) address
	wire advance_rel_addr_w;		wire advance_rel_addr_w;
	wire advance_rel_addr_wr;		wire advance_rel_addr_wr;
	@@ -308,8 +308,8 @@ module membridge#(
	assign left_zero = low4_zero && last_burst;		assign left_zero = low4_zero && last_burst;
	always @ (posedge hclk or posedge rst) begin		always @ (posedge hclk or posedge rst) begin
	if (rst) advance_rel_addr_d <= 0;		if (rst) advance_rel_addr_d <= 0;
	else if (advance_rel_addr_w) advance_rel_addr_d <= {DELAY_ADVANCE_ADDR{1'b1}};		// else if (advance_rel_addr_w) advance_rel_addr_d <= {DELAY_ADVANCE_ADDR{1'b1}};
	else advance_rel_addr_d <= advance_rel_addr_d << 1;		else advance_rel_addr_d <= {advance_rel_addr_d[DELAY_ADVANCE_ADDR-2:0],advance_rel_addr};

	end		end

	@@ -322,17 +322,17 @@ module membridge#(
	assign rw_in_progress = read_started \|\| write_busy;		assign rw_in_progress = read_started \|\| write_busy;

	always @ (posedge hclk) begin		always @ (posedge hclk) begin
	advance_rel_addr <= advance_rel_addr_w && !advance_rel_addr_d[DELAY_ADVANCE_ADDR-1]; // make sure advance_rel_addr_w is recalculated after address change		advance_rel_addr <= advance_rel_addr_w && !advance_rel_addr && !(\|advance_rel_addr_d); // make sure advance_rel_addr_w is recalculated after address change
	last_burst <= ! (\|left64[28:4]);		last_burst <= ! (\|left64[28:4]);
	rollover <= rel_addr64[28:4] == last_addr1k;		rollover <= rel_addr64[28:4] == last_addr1k;
	low4_zero <= ! (\|left64[3:0]);		low4_zero <= ! (\|left64[3:0]);
	if (rdwr_start[0] && rdwr_reset_addr) rel_addr64 <= start64;		if (rdwr_start[0] && rdwr_reset_addr) rel_addr64 <= start64;
	else if (advance_rel_addr) rel_addr64 <= last_burst?(rel_addr64 + left64[3:0]) : (rollover?29'h0:(rel_addr64 + 4'h10));		else if (advance_rel_addr) rel_addr64 <= last_burst?(rel_addr64 + {25'h0,left64[3:0]}) : (rollover?29'h0:(rel_addr64 + 29'h10));

	axi_addr64 <= lo_addr64 + rel_addr64;		axi_addr64 <= lo_addr64 + rel_addr64;

	if (rdwr_start) left64 <= len64;		if (rdwr_start) left64 <= len64;
	else if (advance_rel_addr) left64 <= last_burst? 0: (left64 - 4'h10);		else if (advance_rel_addr) left64 <= last_burst? 0: (left64 - 29'h10);

	afi_len <= (\|left64[28:4])?4'hf : (left64[3:0]-1);		afi_len <= (\|left64[28:4])?4'hf : (left64[3:0]-1);
	afi_len_plus1 <= (\|left64[28:4]) ? 5'h10 : {1'b0,left64[3:0]};		afi_len_plus1 <= (\|left64[28:4]) ? 5'h10 : {1'b0,left64[3:0]};
	@@ -381,11 +381,15 @@ module membridge#(
	else if (!read_busy) read_started <= 0;		else if (!read_busy) read_started <= 0;
	else if (page_ready) read_started <= 1; // first page is in the buffer - use it to mask page number comparison		else if (page_ready) read_started <= 1; // first page is in the buffer - use it to mask page number comparison

			//TODO: Make wresp_pending as difference of 2 counters, wa - on input (variable increment) wresp - on output


	if (rst) wresp_pending <= 0;		if (rst) wresp_pending <= 0;
	else if (!read_busy) wresp_pending <= 0;		else if (!read_busy) wresp_pending <= 0;
	else if ( afi_wvalid && !afi_bvalid_r) wresp_pending <= wresp_pending +1;		else if ( afi_wvalid && !afi_bvalid_r) wresp_pending <= wresp_pending +1;
	else if (!afi_wvalid && afi_bvalid_r) wresp_pending <= wresp_pending -1;		else if (!afi_wvalid && afi_bvalid_r) wresp_pending <= wresp_pending -1;
	read_over <= left_zero && (wresp_pending == 0);		// TODO: Make a counter for addresses outside of afi_wacount
			read_over <= left_zero && (wresp_pending == 0) && (afi_wacount==0);

	if (rst) read_page <= 0;		if (rst) read_page <= 0;
	else if (reset_page_rd) read_page <= 0;		else if (reset_page_rd) read_page <= 0;
	@@ -408,6 +412,7 @@ module membridge#(
	if (rst) done <= 0;		if (rst) done <= 0;
	else if (!rdwr_en) done <= 0; // disabling when idle will reset done		else if (!rdwr_en) done <= 0; // disabling when idle will reset done
	else if ((write_busy && frame_done) \|\| (read_busy && read_over)) done <= 1;		else if ((write_busy && frame_done) \|\| (read_busy && read_over)) done <= 1;
			else if (rdwr_start) done <= 0;


	end		end
	@@ -434,9 +439,9 @@ module membridge#(
	//last_in_line64 - last word number in scan line		//last_in_line64 - last word number in scan line
	reg left_was_1; // was 1 or 0 (0 does not matter)		reg left_was_1; // was 1 or 0 (0 does not matter)
	reg [3:0] src_wcntr;		reg [3:0] src_wcntr;
	reg [1:0] wlast_in_burst;		reg [2:0] wlast_in_burst;

	assign afi_wlast = wlast_in_burst[1];		assign afi_wlast = wlast_in_burst[2];

	always @ (posedge hclk) begin		always @ (posedge hclk) begin
	if (!rw_in_progress) left_was_1 <= 0;		if (!rw_in_progress) left_was_1 <= 0;
	@@ -446,7 +451,7 @@ module membridge#(
	else if (bufrd_rd[0]) src_wcntr <= src_wcntr+1;		else if (bufrd_rd[0]) src_wcntr <= src_wcntr+1;

	if (!read_started) wlast_in_burst <= 0;		if (!read_started) wlast_in_burst <= 0;
	else if (bufrd_rd[0]) wlast_in_burst <= {wlast_in_burst[0],left_was_1 \| (&src_wcntr)};		else if (bufrd_rd[0]) wlast_in_burst <= {wlast_in_burst[1:0],left_was_1 \| (&src_wcntr)};

	bufrd_rd <= {bufrd_rd[1:0], bufrd_rd_w };		bufrd_rd <= {bufrd_rd[1:0], bufrd_rd_w };
	buf_rdwr <= bufrd_rd_w \|\| bufwr_we_w;		buf_rdwr <= bufrd_rd_w \|\| bufwr_we_w;
	@@ -515,7 +520,7 @@ module membridge#(
	else if (next_page_wr_w) write_page <= write_page + 1;		else if (next_page_wr_w) write_page <= write_page + 1;

	if (rst) write_pages_ready <= 0;		if (rst) write_pages_ready <= 0;
	else if (!read_busy) write_pages_ready <= 0;		else if (!write_busy) write_pages_ready <= 0;
	else if ( page_ready_wr && !next_page_wr_w) write_pages_ready <= write_pages_ready -1; //+1;		else if ( page_ready_wr && !next_page_wr_w) write_pages_ready <= write_pages_ready -1; //+1;
	else if (!page_ready_wr && next_page_wr_w) write_pages_ready <= write_pages_ready +1; //-1;		else if (!page_ready_wr && next_page_wr_w) write_pages_ready <= write_pages_ready +1; //-1;

	@@ -552,7 +557,7 @@ module membridge#(
	.clk (mclk), // input		.clk (mclk), // input
	.we (set_status_w), // input		.we (set_status_w), // input
	.wd (cmd_data[7:0]), // input[7:0]		.wd (cmd_data[7:0]), // input[7:0]
	.status ({busy,done}), // input[25:0]		.status ({done,busy}), // input[25:0]
	.ad (status_ad), // output[7:0]		.ad (status_ad), // output[7:0]
	.rq (status_rq), // output		.rq (status_rq), // output
	.start (status_start) // input		.start (status_start) // input

includes/x393_localparams.vh

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -118,6 +118,11 @@
	localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT;		localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT;
	localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)		localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
	localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes)		localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes)

			localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words
			localparam AFI_SIZE64= 'h4000; // size of system memory range in 64-bit words


	// localparam SCANLINE_WINDOW_WH= `h079000a2; // 2592*1936: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)		// localparam SCANLINE_WINDOW_WH= `h079000a2; // 2592*1936: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
	// localparam SCANLINE_WINDOW_WH= 'h0009000b; // 176*9: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)		// localparam SCANLINE_WINDOW_WH= 'h0009000b; // 176*9: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
	localparam WINDOW_WIDTH= 'h000b; //'h005b; //'h000b; // 176: 13-bit window width (0->'h4000)		localparam WINDOW_WIDTH= 'h000b; //'h005b; //'h000b; // 176: 13-bit window width (0->'h4000)

includes/x393_tasks_mcntrl_buffers.vh

+4 −4

Original line number	Original line	Diff line number	Diff line
	@@ -85,12 +85,12 @@ task write_block_buf_chn; // S uppressThisWarning VEditor : may be unused
	begin		begin
	case (chn)		case (chn)
	0: start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);		0: start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);
	1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);		// 1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
	2: start_addr=MCONTR_BUF2_WR_ADDR + (page << 8);		2: start_addr=MCONTR_BUF2_WR_ADDR + (page << 8);
	3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);		3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
	4: start_addr=MCONTR_BUF4_WR_ADDR + (page << 8);		4: start_addr=MCONTR_BUF4_WR_ADDR + (page << 8);
	default: begin		default: begin
	$display("**** ERROR: Invalid channel for write buffer = %d @%t", chn, $time);		$display("**** ERROR: Invalid channel (not 0,2,3,4) for write buffer = %d @%t", chn, $time);
	start_addr = MCONTR_BUF0_WR_ADDR+ (page << 8);		start_addr = MCONTR_BUF0_WR_ADDR+ (page << 8);
	end		end
	endcase		endcase
	@@ -142,12 +142,12 @@ task read_block_buf_chn; // S uppressThisWarning VEditor : may be unused
	begin		begin
	case (chn)		case (chn)
	0: start_addr=MCONTR_BUF0_RD_ADDR + (page << 8);		0: start_addr=MCONTR_BUF0_RD_ADDR + (page << 8);
	1: start_addr=MCONTR_BUF1_RD_ADDR + (page << 8);		// 1: start_addr=MCONTR_BUF1_RD_ADDR + (page << 8);
	2: start_addr=MCONTR_BUF2_RD_ADDR + (page << 8);		2: start_addr=MCONTR_BUF2_RD_ADDR + (page << 8);
	3: start_addr=MCONTR_BUF3_RD_ADDR + (page << 8);		3: start_addr=MCONTR_BUF3_RD_ADDR + (page << 8);
	4: start_addr=MCONTR_BUF4_RD_ADDR + (page << 8);		4: start_addr=MCONTR_BUF4_RD_ADDR + (page << 8);
	default: begin		default: begin
	$display("**** ERROR: Invalid channel for read buffer = %d @%t", chn, $time);		$display("**** ERROR: Invalid channel (not 0,2,3,4) for read buffer = %d @%t", chn, $time);
	start_addr = 30'b0+ (page << 8);		start_addr = 30'b0+ (page << 8);
	end		end
	endcase		endcase

includes/x393_tasks_status.vh

+5 −2

Original line number	Original line	Diff line number	Diff line
	@@ -85,10 +85,12 @@ endtask
	read_status (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR);		read_status (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR);
	read_status (MCNTRL_TILED_STATUS_REG_CHN2_ADDR);		read_status (MCNTRL_TILED_STATUS_REG_CHN2_ADDR);
	read_status (MCNTRL_TILED_STATUS_REG_CHN4_ADDR);		read_status (MCNTRL_TILED_STATUS_REG_CHN4_ADDR);
	read_status (MCNTRL_TEST01_STATUS_REG_CHN1_ADDR);		// read_status (MCNTRL_TEST01_STATUS_REG_CHN1_ADDR);
	read_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);		read_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);
	read_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);		read_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);
	read_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);		read_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);
			read_status (MEMBRIDGE_STATUS_REG);

	end		end
	endtask		endtask

	@@ -112,10 +114,11 @@ endtask
	program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,		program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
	program_status (MCNTRL_TILED_CHN2_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,		program_status (MCNTRL_TILED_CHN2_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
	program_status (MCNTRL_TILED_CHN4_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,		program_status (MCNTRL_TILED_CHN4_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
	program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,		// program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
	program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,		program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
	program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d,		program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d,
	program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,		program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
			program_status (MEMBRIDGE_ADDR , MEMBRIDGE_STATUS_CNTRL, mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
	end		end
	endtask		endtask

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