more bugs fixing with simulation (7b13989a) · Commits · Elphel / x393

includes/x393_parameters.vh

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -103,7 +103,7 @@
	parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller		parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller


	parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))		parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))

	parameter DFLT_DQS_PATTERN= 8'h55,		parameter DFLT_DQS_PATTERN= 8'h55,
	parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00		parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00

includes/x393_tasks_pio_sequences.vh

+12 −4

Original line number	Original line	Diff line number	Diff line
	@@ -98,7 +98,7 @@ task set_write_block;
	cmd_addr <= MCONTR_CMD_WR_ADDR + WRITE_BLOCK_OFFSET;		cmd_addr <= MCONTR_CMD_WR_ADDR + WRITE_BLOCK_OFFSET;
	// activate		// activate
	// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST		// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
	data <= func_encode_cmd( ra[14:0], ba[2:0], 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);		data <= func_encode_cmd( ra[14:0], ba[2:0], 4, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0);
	@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
	// see if pause is needed . See when buffer read should be started - maybe before WR command		// see if pause is needed . See when buffer read should be started - maybe before WR command
	// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST		// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
	@@ -115,15 +115,23 @@ task set_write_block;
	data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 0, 0, 0, 1, 0);		data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 0, 0, 0, 1, 0);
	@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
	//repeat remaining writes		//repeat remaining writes
	for (i = 1; i < 63; i = i + 1) begin		for (i = 1; i < 62; i = i + 1) begin
	// write		// write
	// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST		// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
	data <= func_encode_cmd( {5'b0,ca[9:0]}+(i<<3),ba[2:0],3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0);		data <= func_encode_cmd( {5'b0,ca[9:0]}+(i<<3),ba[2:0],3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0);
	@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
	end		end
			// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
			data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0); // write w/o nop
			@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
			// nop
			// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
			data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 1, 1, 1, 1, 0, 0, 0, 0); // nop with buffer read off
			@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;

	// One last write pair w/o buffer		// One last write pair w/o buffer
	// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST		// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
	data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0],3,1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0);		data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0); // write with nop
	@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;

	// nop		// nop

memctrl/cmd_encod_linear_rd.v

+13 −12

Original line number	Original line	Diff line number	Diff line
	@@ -74,7 +74,7 @@ module cmd_encod_linear_rd #(
	reg [NUM_XFER_BITS-1:0] num128; // number of 128-bit words to transfer		reg [NUM_XFER_BITS-1:0] num128; // number of 128-bit words to transfer
	reg skip_next_page;		reg skip_next_page;
	reg gen_run;		reg gen_run;
	reg gen_run_d;		// reg gen_run_d;
	reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM		reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM

	reg [ROM_WIDTH-1:0] rom_r;		reg [ROM_WIDTH-1:0] rom_r;
	@@ -82,7 +82,7 @@ module cmd_encod_linear_rd #(
	wire [1:0] rom_cmd;		wire [1:0] rom_cmd;
	wire [1:0] rom_skip;		wire [1:0] rom_skip;
	wire [2:0] full_cmd;		wire [2:0] full_cmd;
	reg done;		// reg done;

	assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;		assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
	assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2];		assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2];
	@@ -94,8 +94,8 @@ module cmd_encod_linear_rd #(
	else if (start) gen_run<= 1;		else if (start) gen_run<= 1;
	else if (pre_done) gen_run<= 0;		else if (pre_done) gen_run<= 0;

	if (rst) gen_run_d <= 0;		// if (rst) gen_run_d <= 0;
	else gen_run_d <= gen_run;		// else gen_run_d <= gen_run;

	if (rst) gen_addr <= 0;		if (rst) gen_addr <= 0;
	else if (!start && !gen_run) gen_addr <= 0;		else if (!start && !gen_run) gen_addr <= 0;
	@@ -136,19 +136,20 @@ module cmd_encod_linear_rd #(
	endcase		endcase
	end		end
	always @ (posedge rst or posedge clk) begin		always @ (posedge rst or posedge clk) begin
	if (rst) done <= 0;		// if (rst) done <= 0;
	else done <= pre_done;		// else done <= pre_done;

	if (rst) enc_wr <= 0;		if (rst) enc_wr <= 0;
	else enc_wr <= gen_run \|\| gen_run_d;		else enc_wr <= gen_run; // \|\| gen_run_d;

	if (rst) enc_done <= 0;		if (rst) enc_done <= 0;
	else enc_done <= enc_wr && !gen_run_d;		else enc_done <= enc_wr && !gen_run; // !gen_run_d;

	if (rst) enc_cmd <= 0;		if (rst) enc_cmd <= 0;
	else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause		else if (gen_run) begin
			if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
	{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)		{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
	done, // end of sequence		pre_done, // done, // end of sequence
	bank[2:0], // bank (here OK to be any)		bank[2:0], // bank (here OK to be any)
	1'b0, // odt_en; // enable ODT		1'b0, // odt_en; // enable ODT
	1'b0, // cke; // disable CKE		1'b0, // cke; // disable CKE
	@@ -178,7 +179,7 @@ module cmd_encod_linear_rd #(
	rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data		rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
	rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
	end		end
			end

	// move to include?		// move to include?
	`include "includes/x393_mcontr_encode_cmd.vh"		`include "includes/x393_mcontr_encode_cmd.vh"

memctrl/cmd_encod_linear_wr.v

+86 −44

Original line number	Original line	Diff line number	Diff line
	@@ -22,7 +22,6 @@
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module cmd_encod_linear_wr #(		module cmd_encod_linear_wr #(
	// parameter BASEADDR = 0,
	parameter ADDRESS_NUMBER= 15,		parameter ADDRESS_NUMBER= 15,
	parameter COLADDR_NUMBER= 10,		parameter COLADDR_NUMBER= 10,
	parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length		parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
	@@ -32,8 +31,6 @@ module cmd_encod_linear_wr #(
	input rst,		input rst,
	input clk,		input clk,
	// programming interface		// programming interface
	// input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
	// input cmd_stb, // strobe (with first byte) for the command a/d
	input [2:0] bank_in, // bank address		input [2:0] bank_in, // bank address
	input [ADDRESS_NUMBER-1:0] row_in, // memory row		input [ADDRESS_NUMBER-1:0] row_in, // memory row
	input [COLADDR_NUMBER-4:0] start_col, // start memory column (3 LSBs should be 0?)		input [COLADDR_NUMBER-4:0] start_col, // start memory column (3 LSBs should be 0?)
	@@ -44,7 +41,7 @@ module cmd_encod_linear_wr #(
	output reg enc_wr, // write encoded command		output reg enc_wr, // write encoded command
	output reg enc_done // encoding finished		output reg enc_done // encoding finished
	);		);
	localparam ROM_WIDTH=13;		localparam ROM_WIDTH=12;
	localparam ROM_DEPTH=4;		localparam ROM_DEPTH=4;

	localparam ENC_NOP= 0;		localparam ENC_NOP= 0;
	@@ -57,13 +54,26 @@ module cmd_encod_linear_wr #(
	localparam ENC_PAUSE_SHIFT= 8; // [9:8] - 2- bit pause (for NOP commandes)		localparam ENC_PAUSE_SHIFT= 8; // [9:8] - 2- bit pause (for NOP commandes)
	localparam ENC_PRE_DONE= 10;		localparam ENC_PRE_DONE= 10;
	localparam ENC_BUF_PGNEXT= 11;		localparam ENC_BUF_PGNEXT= 11;
	localparam ENC_DUAL_CYC= 12; // 2-cycle command (with nop or skip) to count number of buffer reads (longer pauses are not used with buffer reads)

	localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands		localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands
	localparam ENC_CMD_WRITE= 1;		localparam ENC_CMD_WRITE= 1;
	localparam ENC_CMD_PRECHARGE=2;		localparam ENC_CMD_PRECHARGE=2;
	localparam ENC_CMD_ACTIVATE= 3;		localparam ENC_CMD_ACTIVATE= 3;
	localparam REPEAT_ADDR=4;
			// read buffer is always at addr 0 and 1,
			localparam REPEAT_ADDR= 5; // loop here (2-cycle command write)
			localparam PRELAST_WRITE_ADDR='h6; // jump here (from 4) if only 2 writes are needed (are fall from 4 wnen 1 write is left
			localparam LAST_WRITE_ADDR= 'h8; // jump here (from 4) if only 2 writes are needed (are fall from 4 wnen 1 write is left
			localparam NO_WRITE_ADDR= 'ha; // jump here (from 4) if only 1 write is needed
			localparam WRITE_ADDR1= 3;
			localparam WRITE_ADDR2= 5;
			// localparam WRITE_ADDR3= 6;
			// localparam WRITE_ADDR4= 8;
			localparam CUT_SINGLE_ADDR= 2; // cut read buffer after this address if only one burst is needed
			localparam CUT_DUAL_ADDR= 4; // cut read buffer after this address if two bursts are needed




	localparam CMD_NOP= 0; // 3-bit normal memory RCW commands (positive logic)		localparam CMD_NOP= 0; // 3-bit normal memory RCW commands (positive logic)
	localparam CMD_WRITE= 3;		localparam CMD_WRITE= 3;
	@@ -77,7 +87,7 @@ module cmd_encod_linear_wr #(
	reg skip_next_page;		reg skip_next_page;

	reg gen_run;		reg gen_run;
	reg gen_run_d;		// reg gen_run_d;
	reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM		reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM

	reg [ROM_WIDTH-1:0] rom_r;		reg [ROM_WIDTH-1:0] rom_r;
	@@ -85,27 +95,25 @@ module cmd_encod_linear_wr #(
	wire [1:0] rom_cmd;		wire [1:0] rom_cmd;
	wire [1:0] rom_skip;		wire [1:0] rom_skip;
	wire [2:0] full_cmd;		wire [2:0] full_cmd;
	reg done;		// reg done;
	// reg buf_rd_23; // read buffer at steps 2&3 (0 if only 1 read is required)
	reg start_d;		reg start_d;
	// reg [ROM_DEPTH-1:0] gen_addr_jump; // next conditonal address		wire next_zero_w= single_write?((gen_addr==CUT_SINGLE_ADDR)?1:0):(dual_write?(gen_addr==CUT_DUAL_ADDR):0);
	reg [NUM_XFER_BITS:0] num_bufrd_left; //counts number of buffer reads left
	wire [NUM_XFER_BITS:0] num_bufrd_left_next_w; //next clock value of the counter
	wire next_zero_w=(num_bufrd_left_next_w==0);
	reg cut_buf_rd;		reg cut_buf_rd;
			reg single_write; // only one burst has to be written
			reg dual_write; // Two bursts have to be written
			reg few_write; //write 1,2 or 3 bursts
			wire write_addr_w; // gen_addr that generates write commands
			reg [ROM_DEPTH-1:0] jump_gen_addr; // will overrun as stop comes from ROM

	assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;		assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
	assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2];		assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2];
	assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];		assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
	assign full_cmd= rom_cmd[1]?(rom_cmd[0]?CMD_ACTIVATE:CMD_PRECHARGE):(rom_cmd[0]?CMD_WRITE:CMD_NOP);		assign full_cmd= rom_cmd[1]?(rom_cmd[0]?CMD_ACTIVATE:CMD_PRECHARGE):(rom_cmd[0]?CMD_WRITE:CMD_NOP);
	assign num_bufrd_left_next_w= num_bufrd_left - (rom_r[ENC_DUAL_CYC]?2:1);
	// prepare jump address? and bufrd during 2,3		// prepare jump address? and bufrd during 2,3
			assign write_addr_w= (gen_addr==WRITE_ADDR1) \|\| (gen_addr==WRITE_ADDR2); // do not need to update after WRITE_ADDR2
	// make num128 7-bits to accommodate 64!		// make num128 7-bits to accommodate 64!
	always @ (posedge clk) begin		always @ (posedge clk) begin
	start_d <= start;		start_d <= start;
	if (start_d) num_bufrd_left <= {num128[NUM_XFER_BITS-1:0],1'b0};
	else if (rom_r[ENC_BUF_RD]) num_bufrd_left <= num_bufrd_left_next_w;
	cut_buf_rd <= rom_r[ENC_BUF_RD] && (cut_buf_rd \|\| next_zero_w);		cut_buf_rd <= rom_r[ENC_BUF_RD] && (cut_buf_rd \|\| next_zero_w);
	end		end
	always @ (posedge rst or posedge clk) begin		always @ (posedge rst or posedge clk) begin
	@@ -114,19 +122,46 @@ module cmd_encod_linear_wr #(
	else if (start) gen_run<= 1;		else if (start) gen_run<= 1;
	else if (pre_done) gen_run<= 0;		else if (pre_done) gen_run<= 0;

	if (rst) gen_run_d <= 0;		// if (rst) gen_run_d <= 0;
	else gen_run_d <= gen_run;		// else gen_run_d <= gen_run;

	if (rst) gen_addr <= 0;		if (rst) gen_addr <= 0;
	else if (!start && !gen_run) gen_addr <= 0;		else if (!start && !gen_run) gen_addr <= 0;
	else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[NUM_XFER_BITS:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter		else if ((gen_addr==(REPEAT_ADDR-1)) && few_write) gen_addr <= jump_gen_addr;
	else if ((gen_addr !=REPEAT_ADDR) \|\| (num128[NUM_XFER_BITS:1]==0)) gen_addr <= gen_addr+1; // not in a loop		// else if ((gen_addr !=REPEAT_ADDR) \|\| (num128[NUM_XFER_BITS:1]==0)) gen_addr <= gen_addr+1; // not in a loop
			else if ((gen_addr !=REPEAT_ADDR) \|\| (num128==2)) gen_addr <= gen_addr+1; // not in a loop

	//counting loops		//counting loops
	if (rst) num128 <= 0;		if (rst) num128 <= 0;
	else if (start) num128 <= {(num128_in==0)?1'b1:1'b0,num128_in};		else if (start) num128 <= {(num128_in==0)?1'b1:1'b0,num128_in};
	else if (!gen_run) num128 <= 0; //		else if (!gen_run) num128 <= 0; //
	else if ((gen_addr == (REPEAT_ADDR-1)) \|\| (gen_addr == REPEAT_ADDR)) num128 <= num128 -1; // ????? - FIXME		// else if ((gen_addr == (REPEAT_ADDR-1)) \|\| (gen_addr == REPEAT_ADDR)) num128 <= num128 -1; // ????? - FIXME
			else if (write_addr_w) num128 <= num128 -1;

			if (rst) single_write <= 0;
			else if (start_d) single_write <= (num128[NUM_XFER_BITS:1]==0); // could not be 0

			if (rst) dual_write <= 0;
			else if (start_d) dual_write <= (num128==2);

			// if (rst) triple_write <= 0;
			// else if (start_d) triple_write <= (num128==3);

			if (rst) few_write <= 0;
			else if (start_d) few_write <=(num128[NUM_XFER_BITS:2]==0); // (0,)1,2 or3
			//
			// if (rst) few_write <= 0;
			// else few_write <= single_write \| dual_write \| triple_write;

			if (rst) jump_gen_addr <= 0;
			else jump_gen_addr <= single_write ? NO_WRITE_ADDR : (dual_write ? LAST_WRITE_ADDR:PRELAST_WRITE_ADDR);


			//triple_write
			// reg single_write; // only one burst has to be written
			// reg dual_write; // Two bursts have to be written


	end		end

	always @ (posedge clk) if (start) begin		always @ (posedge clk) if (start) begin
	@@ -146,35 +181,41 @@ module cmd_encod_linear_wr #(
	always @ (posedge rst or posedge clk) begin		always @ (posedge rst or posedge clk) begin
	if (rst) rom_r <= 0;		if (rst) rom_r <= 0;
	else case (gen_addr)		else case (gen_addr)
	4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);// \| (1 << ENC_NOP);		4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD);// \| (1 << ENC_NOP);
	4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) \| (1 << ENC_PAUSE_SHIFT) \| (1 << ENC_DUAL_CYC); // dual cycle		4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD);
	4'h2: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) \| (1 << ENC_SEL) \| (1 << ENC_ODT); // single cycle		4'h2: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD);
	4'h3: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_ODT); // single cycle		4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) \| (1 << ENC_SEL) \| (1 << ENC_ODT); // single cycle
			4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_ODT); // single cycle
	// next may loop		// next may loop
	4'h4: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_BUF_RD) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_SEL) \| (1 << ENC_ODT) \| (1 << ENC_DUAL_CYC); // dual cycle		4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_BUF_RD) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_SEL) \| (1 << ENC_ODT); // dual cycle
	4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_ODT);		4'h6: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) \| (1 << ENC_BUF_RD) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_SEL) \| (1 << ENC_ODT); // dual cycle
	4'h6: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT);		4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_SEL) \| (1 << ENC_ODT);
	4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) \| (1 << ENC_BUF_PGNEXT);		4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_SEL) \| (1 << ENC_ODT); // dual cycle
	4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT);		4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_ODT);
	4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PRE_DONE);		4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_ODT);
			4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT);
			4'hc: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) \| (1 << ENC_BUF_PGNEXT);
			4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT);
			4'he: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PRE_DONE);
	default:rom_r <= 0;		default:rom_r <= 0;
	endcase		endcase
	end		end
	always @ (posedge rst or posedge clk) begin		always @ (posedge rst or posedge clk) begin
	if (rst) done <= 0;		// if (rst) done <= 0;
	else done <= pre_done;		// else done <= pre_done;

	if (rst) enc_wr <= 0;		if (rst) enc_wr <= 0;
	else enc_wr <= gen_run \|\| gen_run_d;		else enc_wr <= gen_run; // \|\| gen_run_d;

	if (rst) enc_done <= 0;		if (rst) enc_done <= 0;
	// else enc_done <= enc_wr \|\| !gen_run_d;		// else enc_done <= enc_wr \|\| !gen_run_d;
	else enc_done <= enc_wr && !gen_run_d;		else enc_done <= enc_wr && !gen_run; // !gen_run_d;

	if (rst) enc_cmd <= 0;		if (rst) enc_cmd <= 0;
	else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause		else if (gen_run) begin
			if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
	{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)		{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
	done, // end of sequence		pre_done, // done, // end of sequence
	bank[2:0], // bank (here OK to be any)		bank[2:0], // bank (here OK to be any)
	rom_r[ENC_ODT], // odt_en; // enable ODT		rom_r[ENC_ODT], // odt_en; // enable ODT
	1'b0, // cke; // disable CKE		1'b0, // cke; // disable CKE
	@@ -204,6 +245,7 @@ module cmd_encod_linear_wr #(
	rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data		rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
	rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
	end		end
			end


	// move to include?		// move to include?

memctrl/cmd_encod_tiled_32_rd.v

+14 −12

Original line number	Original line	Diff line number	Diff line
	@@ -104,7 +104,7 @@ module cmd_encod_tiled_32_rd #(
	reg keep_open;		reg keep_open;
	reg skip_next_page;		reg skip_next_page;
	reg gen_run;		reg gen_run;
	reg gen_run_d; // to output "done"?		// reg gen_run_d; // to output "done"?
	reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM		reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM

	reg [ROM_WIDTH-1:0] rom_r;		reg [ROM_WIDTH-1:0] rom_r;
	@@ -112,7 +112,7 @@ module cmd_encod_tiled_32_rd #(
	wire [1:0] rom_cmd;		wire [1:0] rom_cmd;
	wire [1:0] rom_skip;		wire [1:0] rom_skip;
	wire [2:0] full_cmd;		wire [2:0] full_cmd;
	reg done;		// reg done;

	reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act		reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
	reg first_col;		reg first_col;
	@@ -162,8 +162,8 @@ module cmd_encod_tiled_32_rd #(
	else if (start_d) gen_run<= 1; // delaying		else if (start_d) gen_run<= 1; // delaying
	else if (pre_done) gen_run<= 0;		else if (pre_done) gen_run<= 0;

	if (rst) gen_run_d <= 0;		// if (rst) gen_run_d <= 0;
	else gen_run_d <= gen_run;		// else gen_run_d <= gen_run;

	if (rst) num_rows_m1 <= 0;		if (rst) num_rows_m1 <= 0;
	else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows		else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
	@@ -247,18 +247,19 @@ module cmd_encod_tiled_32_rd #(
	endcase		endcase
	end		end
	always @ (posedge rst or posedge clk) begin		always @ (posedge rst or posedge clk) begin
	if (rst) done <= 0;		// if (rst) done <= 0;
	else done <= pre_done;		// else done <= pre_done;

	if (rst) enc_wr <= 0;		if (rst) enc_wr <= 0;
	else enc_wr <= gen_run \|\| gen_run_d;		else enc_wr <= gen_run; // \|\| gen_run_d;

	if (rst) enc_done <= 0;		if (rst) enc_done <= 0;
	else enc_done <= enc_wr && !gen_run_d;		else enc_done <= enc_wr && !gen_run; // !gen_run_d;

	if (rst) enc_cmd <= 0;		if (rst) enc_cmd <= 0;
	// else if ((rom_cmd==0) \|\| (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause		// else if ((rom_cmd==0) \|\| (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
	else if (rom_cmd[0] \|\| (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command		else if (gen_run) begin
			if (rom_cmd[0] \|\| (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
	rom_cmd[1]? // activate		rom_cmd[1]? // activate
	row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act		row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
	{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},		{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
	@@ -282,7 +283,7 @@ module cmd_encod_tiled_32_rd #(
	rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
	else enc_cmd <= func_encode_skip ( // encode pause		else enc_cmd <= func_encode_skip ( // encode pause
	{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)		{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
	done, // end of sequence		pre_done, // done, // end of sequence
	3'b0, // bank (here OK to be any)		3'b0, // bank (here OK to be any)
	1'b0, // odt_en; // enable ODT		1'b0, // odt_en; // enable ODT
	1'b0, // cke; // disable CKE		1'b0, // cke; // disable CKE
	@@ -295,6 +296,7 @@ module cmd_encod_tiled_32_rd #(
	1'b0, // buf_rd; // connect to external buffer (but only if not paused)		1'b0, // buf_rd; // connect to external buffer (but only if not paused)
	rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
	end		end
			end
	fifo_2regs #(		fifo_2regs #(
	.WIDTH(COLADDR_NUMBER)		.WIDTH(COLADDR_NUMBER)
	) fifo_2regs_i (		) fifo_2regs_i (