fixed wrong include

79e0b9a4 · Andrey Filippov · 6030b5c1 · 79e0b9a4
Commit 79e0b9a4 authored May 17, 2016 by Andrey Filippov
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ram18t_var_w_var_r.v wrap/ram18t_var_w_var_r.v +1 -1

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--- a/wrap/ram18t_var_w_var_r.v
+++ b/wrap/ram18t_var_w_var_r.v
@@ -101,7 +101,7 @@ module  ram18t_var_w_var_r
  parameter WRITE_MODE_B =        "NO_CHANGE"  //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
 `ifdef PRELOAD_BRAMS
    ,
-    `include "includes/ram36_declare_init.vh"
+    `include "includes/ram18_declare_init.vh"
 `endif
 )(
      input                               clk_a,     // clock for port A