debugging JP4 mode, got correct JP4 image (78d2e067) · Commits · Elphel / x393

.project

+8 −8

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		@@ -62,42 +62,42 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151111121710210.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151115001220264.log</location>
		</link>
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		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151111121710210.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151115001220264.log</location>
		</link>
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		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151111121710210.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151115001220264.log</location>
		</link>
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		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151111121710210.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151115001220264.log</location>
		</link>
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		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151111121710210.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151115001220264.log</location>
		</link>
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		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151111121710210.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151115001220264.log</location>
		</link>
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		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151111121710210.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151115000630414.log</location>
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		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151111121710210.log</location>
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		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

axi/membridge.v

+2 −1

Original line number	Diff line number	Diff line
		@@ -749,6 +749,7 @@ wire [63:0] afi_wdata0;
		.ext_rd (bufrd_rd[0]), // input
		.ext_regen (bufrd_rd[1]), // input
		.ext_data_out (afi_wdata0), // output[63:0]
		// .emul64 (1'b0), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
		.wclk (!mclk), // input
		.wpage_in (2'b0), // input[1:0]
		.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start

compressor_jp/cmprs_pixel_buf_iface.v

+28 −9

Original line number	Diff line number	Diff line
		@@ -67,9 +67,11 @@ module cmprs_pixel_buf_iface #(
		// controller this can just be the same as mb_pre_end_in
		input mb_pre_start, // 1 clock cycle before stream of addresses to the buffer
		input [ 1:0] start_page, // page to read next tile from (or first of several pages)
		input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
		input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide.
		// valid 3 cycles before mb_pre_start
		output reg [ 7:0] data_out, //
		output pre_first_out, // For each macroblock in a frame
		output pre2_first_out, // 1 cycle before pre_first_out
		output reg data_valid //
		);
		localparam PERIOD_COLOR18 = 384; // >1818, limited by 664 (macroblocks)
		@@ -105,8 +107,13 @@ module cmprs_pixel_buf_iface #(
		reg [ 8:0] period_cntr;
		reg mb_pre_end_r;
		reg mb_release_buf_r;
		reg pre_first_out_r;
		reg [CMPRS_BUF_EXTRA_LATENCY+2:0] pre_first_out_r;

		reg [ 2:0] mb_col_number; // number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start
		wire [ 9:0] extra_start_addr_w = mb_col_number * mb_h_m1; //added to mb_start_addr when non-zero column
		reg [ 5:0] extra_start_addr_r;
		// reg [ 5:0] mb_h; // macroblock height (lost MSB - OK)
		reg [ 9:0] mb_start_addr; // was macroblock_x, noccrected for multi-column. valid with mb_pre_start

		assign buf_ra = bufa_r;
		assign tile_width_or= tile_width[1]?(tile_width[0]?0:'h40):(tile_width[0]?'h60:'h70);
		@@ -119,9 +126,15 @@ module cmprs_pixel_buf_iface #(
		assign mb_release_buf = mb_release_buf_r;
		assign buf_rd = buf_re[1:0];
		// assign data_out = do_r;
		assign pre_first_out = pre_first_out_r;
		assign pre_first_out = pre_first_out_r[0];
		assign pre2_first_out = pre_first_out_r[1];

		always @(posedge xclk) begin
		// mb_h <= mb_h_m1+1; // macroblock height
		mb_col_number <= {macroblock_x[6:5],tile_col_width?1'b0:macroblock_x[4]};
		extra_start_addr_r <= extra_start_addr_w[5:0];
		mb_start_addr <= {3'b0,macroblock_x} + {extra_start_addr_r,4'b0};

		if (!frame_en) buf_re[0] <= 0;
		else if (mb_pre_start) buf_re[0] <= 1'b1;
		else if (addr_run_end) buf_re[0] <= 1'b0;
		@@ -131,9 +144,13 @@ module cmprs_pixel_buf_iface #(

		// Buffer data read:
		if (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]) data_out <= buf_di;

		//mb_pre_start
		if (!frame_en) pre_first_out_r <= 0;
		else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
		else pre_first_out_r <= {mb_pre_start, pre_first_out_r[CMPRS_BUF_EXTRA_LATENCY + 2 : 1]};
		// else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];

		// if (!frame_en) pre2_first_out <= 0;
		// else pre2_first_out <= buf_re[CMPRS_BUF_EXTRA_LATENCY + 0] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY + 1];

		if (mb_pre_start) rows_left <= mb_h_m1;
		else if (last_col) rows_left <= rows_left - 1;
		@@ -153,7 +170,8 @@ module cmprs_pixel_buf_iface #(

		first_col <= (mb_pre_start \|\| (last_col && !last_row));

		if (mb_pre_start) row_sa <= {start_page,3'b0,macroblock_x};
		// if (mb_pre_start) row_sa <= {start_page,3'b0,mb_start_addr}; // macroblock_x};
		if (mb_pre_start) row_sa <= {start_page,mb_start_addr}; // macroblock_x};
		else if (first_col) row_sa <= row_sa + (tile_col_width ? 12'h20:12'h10);

		if (mb_pre_start) tile_sa <= 0;
		@@ -172,7 +190,8 @@ module cmprs_pixel_buf_iface #(
		else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;

		// Most time critical - calculation of the buffer address
		if (mb_pre_start) bufa_r[9:0] <= {3'b0,macroblock_x};
		// if (mb_pre_start) bufa_r[9:0] <= {3'b0,mb_start_addr}; // macroblock_x};
		if (mb_pre_start) bufa_r[9:0] <= {mb_start_addr}; // macroblock_x};
		else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
		else if (last_in_tile) bufa_r[9:0] <= tile_sa;
		else if (buf_re[0]) bufa_r[9:0] <= bufa_r[9:0] + {last_in_col?col_inc[9:4]:6'b0,4'b1};

compressor_jp/csconvert.v

+16 −15

Original line number	Diff line number	Diff line
		@@ -55,7 +55,7 @@ module csconvert#(
		input [ 9:0] m_cr, // [9:0] scale for CB - default 0.713 (10'hb6)
		input [ 7:0] mb_din, // input bayer data in scanline sequence, GR/BG sequence
		input [ 1:0] bayer_phase,
		input pre_first_in, // marks the first input pixel
		input pre2_first_in, // marks the first input pixel (2 cycles ahead)

		output reg [ 8:0] signed_y, // - now signed char, -128(black) to +127 (white)
		output reg [ 8:0] signed_c, // new, q is just signed char
		@@ -69,7 +69,7 @@ module csconvert#(
		// output reg ccv_out_start, //TODO: adjust to minimal latency?
		output reg [ 7:0] n000, // not clear how they are used, make them just with latency1 from old
		output reg [ 7:0] n255);

		reg pre_first_in;
		// outputs to be multiplexed:
		wire [7:0] conv18_signed_y, conv20_signed_y, mono16_signed_y, jp4_signed_y;
		wire [8:0] jp4diff_signed_y, conv18_signed_c, conv20_signed_c;
		@@ -100,7 +100,8 @@ module csconvert#(
		reg [5:0] component_firstsS; // first_r this component in a frame (DC absolute, otherwise - difference to previous)
		*/
		always @ (posedge xclk) begin
		if (pre_first_in) begin
		pre_first_in <= pre2_first_in;
		if (pre2_first_in) begin
		converter_type_r [2:0] <= converter_type[2:0];
		ignore_color_r <= ignore_color;
		// jp4_dc_improved_r <= jp4_dc_improved;
		@@ -117,22 +118,22 @@ module csconvert#(

		// generate one-hot converter enable
		if (!frame_en) en_converters[CMPRS_COLOR18] <= 0;
		else if (pre_first_in) en_converters[CMPRS_COLOR18] <= converter_type == CMPRS_COLOR18;
		else if (pre2_first_in) en_converters[CMPRS_COLOR18] <= converter_type == CMPRS_COLOR18;

		if (!frame_en) en_converters[CMPRS_COLOR20] <= 0;
		else if (pre_first_in) en_converters[CMPRS_COLOR20] <= converter_type == CMPRS_COLOR20;
		else if (pre2_first_in) en_converters[CMPRS_COLOR20] <= converter_type == CMPRS_COLOR20;

		if (!frame_en) en_converters[CMPRS_MONO16] <= 0;
		else if (pre_first_in) en_converters[CMPRS_MONO16] <= converter_type == CMPRS_MONO16;
		else if (pre2_first_in) en_converters[CMPRS_MONO16] <= converter_type == CMPRS_MONO16;

		if (!frame_en) en_converters[CMPRS_JP4] <= 0;
		else if (pre_first_in) en_converters[CMPRS_JP4] <= converter_type == CMPRS_JP4;
		else if (pre2_first_in) en_converters[CMPRS_JP4] <= converter_type == CMPRS_JP4;

		if (!frame_en) en_converters[CMPRS_JP4DIFF] <= 0;
		else if (pre_first_in) en_converters[CMPRS_JP4DIFF] <= converter_type == CMPRS_JP4DIFF;
		else if (pre2_first_in) en_converters[CMPRS_JP4DIFF] <= converter_type == CMPRS_JP4DIFF;

		if (!frame_en) en_converters[CMPRS_MONO8] <= 0;
		else if (pre_first_in) en_converters[CMPRS_MONO8] <= converter_type == CMPRS_MONO8;
		else if (pre2_first_in) en_converters[CMPRS_MONO8] <= converter_type == CMPRS_MONO8;
		end

compressor_jp/jp_channel.v

+32 −23

Original line number	Diff line number	Diff line
		@@ -262,6 +262,7 @@ module jp_channel#(
		// signals connecting modules: chn_rd_buf_i and ???:
		wire [ 7:0] mb_data_out; // Macroblock data out in scanline order
		wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid
		wire mb_pre2_first_out; // Macroblock data out strobe - 2 cycles just before data valid
		// wire mb_data_valid; // Macroblock data out valid

		wire limit_diff = 1'b1; // as in the prototype - just a constant 1
		@@ -421,15 +422,15 @@ module jp_channel#(
		wire [2:0] dbg_block_mem_wa_save;
		`ifndef USE_XCLK2X
		// temporarily assigning unused debug signals to 0
		assign dbg_add_invalid = 0;
		assign dbg_mb_release_buf = 0;
		assign etrax_dma = 0;
		assign dbg_ts_rstb = 0; // output
		assign dbg_ts_dout = 0; //output [7:0]
		assign dbg_flushing = 0;
		assign dbg_test_lbw = 0;
		assign dbg_gotLastBlock = 0;
		assign dbg_fifo_or_full = 0;
		// assign dbg_add_invalid = 0;
		// assign dbg_mb_release_buf = 0;
		// assign etrax_dma = 0;
		// assign dbg_ts_rstb = 0; // output
		// assign dbg_ts_dout = 0; //output [7:0]
		assign dbg_flushing = 0; // still not used in huffman_stuffer_meta
		// assign dbg_test_lbw = 0;
		// assign dbg_gotLastBlock = 0;
		assign dbg_fifo_or_full = 0; // still not used in huffman_stuffer_meta

		`endif
		timestamp_to_parallel dbg_timestamp_to_parallel_i (
		@@ -612,7 +613,13 @@ module jp_channel#(
		.start (status_start) // input
		);
		//hifreq
		// Port buffer - TODO: Move to memory controller
		// Not needed?
		// reg emul64;
		// always @ (negedge mclk) begin
		// emul64 <= tile_width[1]; // will not work for monochrome (128 pixel wide) - chnge to 64?
		// end


		mcntrl_buf_rd #(
		.LOG2WIDTH_RD(3) // 64 bit external interface
		) chn_rd_buf_i (
		@@ -621,6 +628,7 @@ module jp_channel#(
		.ext_rd (buf_rd[0]), // input
		.ext_regen (buf_rd[1]), // input
		.ext_data_out (buf_pxd), // output[7:0]
		// .emul64 (1'b0), //emul64), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
		.wclk (!mclk), // input
		.wpage_in (2'b0), // input[1:0]
		.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
		@@ -837,7 +845,8 @@ module jp_channel#(
		.data_out (mb_data_out), // output[7:0] // Macroblock data out in scanline order
		.pre_first_out (mb_pre_first_out), // output // Macroblock data out strobe - 1 cycle just before data valid == old pre_first_pixel?
		// .data_valid (mb_data_valid) // output // Macroblock data out valid
		.data_valid () // output // Macroblock data out valid Unused
		.pre2_first_out (mb_pre2_first_out), // output reg
		.data_valid () // output reg // Macroblock data out valid Unused
		);

		csconvert #(
		@@ -859,7 +868,7 @@ module jp_channel#(
		.m_cr (m_cr), // input[9:0]
		.mb_din (mb_data_out), // input[7:0]
		.bayer_phase (bayer_phase), // input[1:0]
		.pre_first_in (mb_pre_first_out), // input
		.pre2_first_in (mb_pre2_first_out),// input
		.signed_y (signed_y), // output[8:0] reg
		.signed_c (signed_c), // output[8:0] reg
		.yaddrw (yaddrw), // output[7:0] reg

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