simulating/bug fixing

.settings/com.elphel.vdt.FPGA_project.prefs

-FPGA_project_0_SimulationTopFile=x393_testbench02.tf
-FPGA_project_1_SimulationTopModule=x393_testbench02
+FPGA_project_0_SimulationTopFile=x393_testbench03.tf
+FPGA_project_1_SimulationTopModule=x393_testbench03
 FPGA_project_2_ImplementationTopFile=x393.v
 FPGA_project_4_part=xc7z030fbg484-1
 FPGA_project_5_part=xc7z030fbg484-1

includes/x393_parameters.vh

@@ -429,11 +429,20 @@
         parameter SENS_CTRL_ARST =        2,  //  3: 2
         parameter SENS_CTRL_ARO =         4,  //  5: 4
         parameter SENS_CTRL_RST_MMCM =    6,  //  7: 6
+//`ifdef HISPI
+        parameter SENS_CTRL_IGNORE_EMBED =8,  //  9: 8
+//`else        
         parameter SENS_CTRL_EXT_CLK =     8,  //  9: 8
+//`endif        
         parameter SENS_CTRL_LD_DLY =     10,  // 10
+//`ifdef HISPI
+        parameter SENS_CTRL_GP0=      12,  // 13:12
+        parameter SENS_CTRL_GP1=      14,  // 15:14
+//`else        
         parameter SENS_CTRL_QUADRANTS =  12,  // 17:12, enable - 20
         parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
         parameter SENS_CTRL_QUADRANTS_EN =   20,  // 17:12, enable - 20 (2 bits reserved)
+//`endif        
       parameter SENSIO_STATUS =         'h1,
       parameter SENSIO_JTAG =           'h2,
         // SENSIO_JTAG register bits
@@ -442,7 +451,9 @@
         parameter SENS_JTAG_TCK =         4,
         parameter SENS_JTAG_TMS =         2,
         parameter SENS_JTAG_TDI =         0,
+//`ifndef HISPI
       parameter SENSIO_WIDTH =          'h3, // 1.. 2^16, 0 - use HACT
+//`endif      
       parameter SENSIO_DELAYS =         'h4, // 'h4..'h7
         // 4 of 8-bit delays per register
     // sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
@@ -466,10 +477,13 @@
     parameter SENSI2C_IOSTANDARD =       "LVCMOS25",
     parameter SENSI2C_SLEW =             "SLOW",
     
+//`ifndef HISPI
     //sensor_fifo parameters
     parameter SENSOR_DATA_WIDTH =      12,
     parameter SENSOR_FIFO_2DEPTH =     4,
-    parameter SENSOR_FIFO_DELAY =        4'd5, // 7,
+    parameter SENSOR_FIFO_DELAY =      5, // 7,
+//`endif    
+
     // other parameters for histogram_saxi module
     parameter HIST_SAXI_ADDR_MASK =      'h7f0,
       parameter HIST_SAXI_MODE_WIDTH =   8,
@@ -505,15 +519,30 @@
 `endif    
     parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
 
+//`ifdef HISPI
+    parameter PXD_CAPACITANCE =          "DONT_CARE",
+    parameter PXD_CLK_DIV =              10, // 220MHz -> 22MHz
+    parameter PXD_CLK_DIV_BITS =          4,
+//`endif    
+    
     parameter SENS_PHASE_WIDTH=          8,      // number of bits for te phase counter (depends on divisors)
     parameter SENS_PCLK_PERIOD =         10.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter SENS_BANDWIDTH =           "OPTIMIZED",  //"OPTIMIZED", "HIGH","LOW"
 
+    // parameters for the sensor-synchronous clock PLL
+`ifdef HISPI    
+    parameter CLKIN_PERIOD_SENSOR =      3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+    parameter CLKFBOUT_MULT_SENSOR =     3,      // 330 MHz --> 990 MHz
+    parameter CLKFBOUT_PHASE_SENSOR =    0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
+    parameter IPCLK_PHASE =              0.000,
+    parameter IPCLK2X_PHASE =            0.000,
+`else    
+    parameter CLKIN_PERIOD_SENSOR =      10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter CLKFBOUT_MULT_SENSOR =     8,      // 100 MHz --> 800 MHz
     parameter CLKFBOUT_PHASE_SENSOR =    0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
     parameter IPCLK_PHASE =              0.000,
     parameter IPCLK2X_PHASE =            0.000,
-
+`endif
 //    parameter BUF_IPCLK =                "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
 //    parameter BUF_IPCLK2X =              "BUFMR", //G", // "BUFR",  
 
@@ -536,6 +565,18 @@
     parameter SENS_SS_MODE       =       "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
     parameter SENS_SS_MOD_PERIOD =       10000,        // integer 4000-40000 - SS modulation period in ns
 
+//`ifdef HISPI
+    parameter HISPI_MSB_FIRST =            0,
+    parameter HISPI_NUMLANES =             4,
+    parameter HISPI_CAPACITANCE =         "DONT_CARE",
+    parameter HISPI_DIFF_TERM =           "TRUE",
+    parameter HISPI_DQS_BIAS =            "TRUE",
+    parameter HISPI_IBUF_DELAY_VALUE =    "0",
+    parameter HISPI_IBUF_LOW_PWR =        "TRUE",
+    parameter HISPI_IFD_DELAY_VALUE =     "AUTO",
+    parameter HISPI_IOSTANDARD =          "DEFAULT",
+//`endif    
+    
     parameter CMPRS_NUM_AFI_CHN =         1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
     parameter CMPRS_GROUP_ADDR =          'h600, // total of 'h60
     parameter CMPRS_BASE_INC =            'h10,

includes/x393_simulation_parameters.vh

@@ -38,6 +38,15 @@
 //    parameter SENSOR12BITS_NROWA   =     1,   // number of "blank rows" from last hact to end of vact
 //    parameter nAV   =      24,   //240;   // clocks from ARO to VACT (actually from en_dclkd)
 //    parameter SENSOR12BITS_NBPF =       20,   //16; // bpf length
+`ifdef HISPI
+    parameter SENSOR12BITS_NGPL =        2,   // bpf to hact
+    parameter SENSOR12BITS_NVLO =        1,   // VACT=0 in video mode (clocks)
+    //parameter tMD   =   14;    //
+    //parameter tDDO   =   10;   //   some confusion here - let's assume that it is from DCLK to Data out
+    parameter SENSOR12BITS_TMD =         1.2,   //
+    parameter SENSOR12BITS_TDDO =        0.8,   //   some confusion here - let's assume that it is from DCLK to Data out
+    parameter SENSOR12BITS_TDDO1 =       1.6,   //
+`else
     parameter SENSOR12BITS_NGPL =        8,   // bpf to hact
     parameter SENSOR12BITS_NVLO =        1,   // VACT=0 in video mode (clocks)
     //parameter tMD   =   14;    //
@@ -45,6 +54,7 @@
     parameter SENSOR12BITS_TMD =         4,   //
     parameter SENSOR12BITS_TDDO =        2,   //   some confusion here - let's assume that it is from DCLK to Data out
     parameter SENSOR12BITS_TDDO1 =       5,   //
+`endif    
 //    parameter SENSOR12BITS_TRIGDLY =     8,   // delay between trigger input and start of output (VACT) in lines
 //    parameter SENSOR12BITS_RAMP =        1,   // 1 - ramp, 0 - random (now - sensor.dat)
 //    parameter SENSOR12BITS_NEW_BAYER =   0,   // 0 - "old" tiles (16x16, 1 - new - (18x18)   

sensor/sens_10398.v

@@ -56,10 +56,11 @@ module  sens_10398 #(
     parameter real REFCLK_FREQUENCY =      200.0,
     parameter HIGH_PERFORMANCE_MODE =     "FALSE",
     parameter SENS_PHASE_WIDTH=            8,      // number of bits for te phase counter (depends on divisors)
-    parameter SENS_PCLK_PERIOD =           3.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+//    parameter SENS_PCLK_PERIOD =           3.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter SENS_BANDWIDTH =             "OPTIMIZED",  //"OPTIMIZED", "HIGH","LOW"
 
-    parameter CLKFBOUT_MULT_SENSOR =       4,  // 220 MHz --> 880 MHz
+    parameter CLKIN_PERIOD_SENSOR =        3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+    parameter CLKFBOUT_MULT_SENSOR =       3,      // 330 MHz --> 990 MHz
     parameter CLKFBOUT_PHASE_SENSOR =      0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
     parameter IPCLK_PHASE =                0.000,
     parameter IPCLK2X_PHASE =              0.000,
@@ -127,10 +128,11 @@ module  sens_10398 #(
 
     input                      sns_flash_tdo,   // sns_dp[4]           TDO  (differs from 10353)
     input                      sns_shutter_done,// sns_dn[4]           DONE (differs from 10353)
-    // output
+
     output              [11:0] pxd,
-    output                     vact, 
-    output                     hact
+    output                     hact,
+    output                     sof, // @pclk
+    output                     eof // @pclk
     
 
 );
@@ -145,18 +147,6 @@ module  sens_10398 #(
     reg         set_status_r;
     reg         set_jtag_r;
     
-//    reg [LINE_WIDTH_BITS-1:0] line_width_m1;       // regenerated HACT duration;
-//    reg [LINE_WIDTH_BITS-1:0] line_width_m1_ipclk;  // regenerated HACT duration;
-    
-//    reg                       line_width_internal; // use regenetrated ( 0 - use HACT as is)
-//    reg                       line_width_internal_ipclk;
-//    reg [LINE_WIDTH_BITS-1:0] hact_cntr;
-    
-//    reg         set_quad; // [1:0] - px, [3:2] - HACT, [5:4] - VACT,
-    
-//    wire  [2:0] set_pxd_delay;
-//    wire        set_other_delay;
-    
     wire        ps_rdy;
     wire  [7:0] ps_out;      
     wire        locked_pxd_mmcm;
@@ -167,17 +157,11 @@ module  sens_10398 #(
     reg         iaro_soft  = 0;
     wire        iaro;
     reg         iarst = 0;
-    reg         imrst = 0;
+    reg         imrst = 0;  // active low 
     reg         rst_mmcm=1; // rst and command - en/dis 
-//    reg  [SENS_CTRL_QUADRANTS_WIDTH-1:0]  quadrants=0; //90-degree shifts for data {1:0], hact [3:2] and vact [5:4]
     reg         ld_idelay=0;
-//    reg         sel_ext_clk=0; // select clock source from the sensor (0 - use internal clock - to sensor)
-
     reg         ignore_embed=0; // do not process sensor data marked as "embedded"
 
-
-
-//    wire [17:0] status;
     wire [14:0] status;
     
     wire        cmd_we;
@@ -195,30 +179,10 @@ module  sens_10398 #(
     reg            xfpgatdi=0;   // TDI to be sent to external FPGA
     
     reg      [1:0] gp_r;         // sensor GP0, GP1. For now just software control, later use for something else
-//    wire           hact_ext;     // received hact signal
-//    reg            hact_ext_r;   // received hact signal, delayed by 1 clock
-//    reg            hact_r;       // received or regenerated hact 
-
-// for debug/test alive    
-/*
-    reg            vact_r;       
-    reg            hact_r2;
-    wire           vact_a_mclk;
-    wire           hact_ext_a_mclk;
-    wire           hact_a_mclk;
-    reg            vact_alive;
-    reg            hact_ext_alive;
-    reg            hact_alive;
-    reg  [STATUS_ALIVE_WIDTH-1:0] status_alive; 
-*/    
     reg [ PXD_CLK_DIV_BITS-1:0] pxd_clk_cntr;
-//        parameter PXD_CLK_DIV =              10, // 220MHz -> 22MHz
-//    parameter PXD_CLK_DIV_BITS =          4,
+    reg      [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
+    wire           async_prst_with_sens_mrst =  ~imrst | rst_mmcm; // mclk domain   
 
-     
-//    assign set_pxd_delay =   set_idelay[2:0];
-//    assign set_other_delay = set_idelay[3];
-//    assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm, 
     assign status = { locked_pxd_mmcm, 
                      clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
                      ps_rdy, ps_out, xfpgatdo, senspgmin};
@@ -273,15 +237,9 @@ module  sens_10398 #(
         if      (mrst)                                          rst_mmcm <= 0;
         else if (set_ctrl_r && data_r[SENS_CTRL_RST_MMCM + 1])  rst_mmcm <= data_r[SENS_CTRL_RST_MMCM]; 
          
-//        if      (mrst)                                      sel_ext_clk <= 0;
-//        else if (set_ctrl_r && data_r[SENS_CTRL_EXT_CLK + 1])   sel_ext_clk <= data_r[SENS_CTRL_EXT_CLK]; 
         if      (mrst)                                               ignore_embed <= 0;
         else if (set_ctrl_r && data_r[SENS_CTRL_IGNORE_EMBED + 1])   ignore_embed <= data_r[SENS_CTRL_IGNORE_EMBED]; 
          
-         
-//        if      (mrst)                                         quadrants <= 0;
-//        else if (set_ctrl_r && data_r[SENS_CTRL_QUADRANTS_EN])  quadrants <= data_r[SENS_CTRL_QUADRANTS +: SENS_CTRL_QUADRANTS_WIDTH]; 
-
         if  (mrst) ld_idelay <= 0;
         else       ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY]; 
 
@@ -291,27 +249,22 @@ module  sens_10398 #(
         if      (mrst)                                      gp_r[1] <= 0;
         else if (set_ctrl_r && data_r[SENS_CTRL_GP1 + 1])   gp_r[1] <= data_r[SENS_CTRL_GP1]; 
 
-
-
-        
-//        if  (mrst) set_width_r <= 0;
-//        else           set_width_r <= {set_width_r[0],cmd_we && (cmd_a== SENSIO_WIDTH)}; 
-        
-//        if      (mrst)       line_width_m1 <= 0;
-//        else if (set_width_r[1]) line_width_m1 <= data_r[LINE_WIDTH_BITS-1:0] -1;
-        
-//        if      (mrst)       line_width_internal <= 0;
-//        else if (set_width_r[1]) line_width_internal <= ~ (|data_r[LINE_WIDTH_BITS:0]); // line width is 0
     end
 
+    // generate (slow) clock for the sensor - it will be multiplied by the sensor VCO
     always @(posedge pclk) begin
         if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2);
         else                                                   pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] - 1;
-    
+        // treat MSB separately to make 50% duty cycle
         if      (prst)                                         pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <=   0;
         else if (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)      pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <=  ~pxd_clk_cntr[PXD_CLK_DIV_BITS-1];
     
-//    reg [ PXD_CLK_DIV_BITS-1:0] pxd_clk_cntr;
+    end
+
+    always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
+        if (async_prst_with_sens_mrst) prst_with_sens_mrst <=  2'h3;
+        else if (prst)                 prst_with_sens_mrst <=  2'h3;
+        else                           prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
     
     end
     cmd_deser #(
@@ -353,8 +306,8 @@ module  sens_10398 #(
         .REFCLK_FREQUENCY       (REFCLK_FREQUENCY),
         .HIGH_PERFORMANCE_MODE  (HIGH_PERFORMANCE_MODE),
         .SENS_PHASE_WIDTH       (SENS_PHASE_WIDTH),
-        .SENS_PCLK_PERIOD       (SENS_PCLK_PERIOD),
         .SENS_BANDWIDTH         (SENS_BANDWIDTH),
+        .CLKIN_PERIOD_SENSOR    (CLKIN_PERIOD_SENSOR),
         .CLKFBOUT_MULT_SENSOR   (CLKFBOUT_MULT_SENSOR),
         .CLKFBOUT_PHASE_SENSOR  (CLKFBOUT_PHASE_SENSOR),
         .IPCLK_PHASE            (IPCLK_PHASE),
@@ -378,14 +331,15 @@ module  sens_10398 #(
         .HISPI_IOSTANDARD       (HISPI_IOSTANDARD)
     ) sens_hispi12l4_i (
         .pclk                   (pclk),                   // input
-        .prst                   (prst),                   // input
+        .prst                   (prst_with_sens_mrst[0]), //prst),                   // input
         .sns_dp                 (sns_dp[3:0]),            // input[3:0] 
         .sns_dn                 (sns_dn[3:0]),            // input[3:0] 
         .sns_clkp               (sns_clkp),               // input
         .sns_clkn               (sns_clkn),               // input
         .pxd_out                (pxd),                    // output[11:0] reg 
-        .vact_out               (vact),                   // output reg 
         .hact_out               (hact),                   // output
+        .sof                    (sof),                    // output
+        .eof                    (eof),                    // output reg 
         .mclk                   (mclk),                   // input
         .mrst                   (mrst),                   // input
         .dly_data               (data_r),                 // input[31:0] 

sensor/sens_hispi12l4.v

@@ -26,10 +26,11 @@ module  sens_hispi12l4#(
     parameter real REFCLK_FREQUENCY =      200.0,
     parameter HIGH_PERFORMANCE_MODE =     "FALSE",
     parameter SENS_PHASE_WIDTH=            8,      // number of bits for te phase counter (depends on divisors)
-    parameter SENS_PCLK_PERIOD =           3.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+//    parameter SENS_PCLK_PERIOD =           3.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter SENS_BANDWIDTH =             "OPTIMIZED",  //"OPTIMIZED", "HIGH","LOW"
 
-    parameter CLKFBOUT_MULT_SENSOR =       4,  // 220 MHz --> 880 MHz
+    parameter CLKIN_PERIOD_SENSOR =        3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+    parameter CLKFBOUT_MULT_SENSOR =       3,      // 330 MHz --> 990 MHz
     parameter CLKFBOUT_PHASE_SENSOR =      0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
     parameter IPCLK_PHASE =                0.000,
     parameter IPCLK2X_PHASE =              0.000,
@@ -51,19 +52,23 @@ module  sens_hispi12l4#(
     parameter HISPI_IBUF_DELAY_VALUE =    "0",
     parameter HISPI_IBUF_LOW_PWR =        "TRUE",
     parameter HISPI_IFD_DELAY_VALUE =     "AUTO",
-    parameter HISPI_IOSTANDARD =          "DEFAULT"
+    parameter HISPI_IOSTANDARD =          "DEFAULT",
+    parameter HISPI_KEEP_IRST =           5 // number of cycles to keep irst on after release of prst (small number - use 1 hot)
 )(
     input             pclk,   // global clock input, pixel rate (220MHz for MT9F002)
-    input             prst,
+    input             prst,   // reset @pclk (add sensor reset here)
     // I/O pads
     input [HISPI_NUMLANES-1:0] sns_dp,
     input [HISPI_NUMLANES-1:0] sns_dn,
     input                      sns_clkp,
     input                      sns_clkn,
     // output
-    output reg          [11:0] pxd_out,
-    output reg                 vact_out, 
+//    output reg          [11:0] pxd_out,
+    output              [11:0] pxd_out,
+//    output reg                 vact_out, 
     output                     hact_out,
+    output                     sof, // @pclk
+    output reg                 eof, // @pclk
     
     // delay control inputs
     input                           mclk,
@@ -86,10 +91,15 @@ module  sens_hispi12l4#(
     wire                          ipclk;  // re-generated half HiSPi clock (165 MHz) 
     wire                          ipclk2x;// re-generated HiSPi clock (330 MHz)
     wire [HISPI_NUMLANES * 4-1:0] sns_d;
+    localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
+    localparam FIFO_DEPTH = 4;
+    reg      [HISPI_KEEP_IRST-1:0] irst_r;
+    wire                         irst = irst_r[0];
+    
     sens_hispi_clock #(
         .SENS_PHASE_WIDTH       (SENS_PHASE_WIDTH),
-        .SENS_PCLK_PERIOD       (SENS_PCLK_PERIOD),
         .SENS_BANDWIDTH         (SENS_BANDWIDTH),
+        .CLKIN_PERIOD_SENSOR    (CLKIN_PERIOD_SENSOR),
         .CLKFBOUT_MULT_SENSOR   (CLKFBOUT_MULT_SENSOR),
         .CLKFBOUT_PHASE_SENSOR  (CLKFBOUT_PHASE_SENSOR),
         .IPCLK_PHASE            (IPCLK_PHASE),
@@ -153,11 +163,6 @@ module  sens_hispi12l4#(
         .dout         (sns_d) // output[15:0] 
     );
     
-    localparam WAIT_ALL_LANES = 8; // number of output pixel cycles to wait after the earliest lane
-    localparam FIFO_DEPTH = 4;
-
-    reg       [2:0] irst_r;
-    wire            irst = irst_r[2];
     
 
     wire [HISPI_NUMLANES * 12-1:0] hispi_aligned;
@@ -188,12 +193,29 @@ module  sens_hispi12l4#(
     wire                            hact_on;
     wire                            hact_off;
     reg                             ignore_embedded_ipclk;
+    reg                       [1:0] vact_pclk;
+    wire                     [11:0] pxd_out_pre = ({12 {fifo_re_r[0] & rd_run[0]}} & fifo_out[0 * 12 +:12]) |
+                                                  ({12 {fifo_re_r[1] & rd_run[1]}} & fifo_out[1 * 12 +:12]) |
+                                                  ({12 {fifo_re_r[2] & rd_run[2]}} & fifo_out[2 * 12 +:12]) |
+                                                  ({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]);
+       
+    
+    
     assign hact_out = hact_r;
+    assign sof =      sof_pclk;
+    
+    // async reset
+    always @ (posedge ipclk or posedge prst) begin
+        if (prst) irst_r <= {HISPI_KEEP_IRST{1'b1}}; // HISPI_KEEP_IRST-1
+        else      irst_r <= irst_r >> 1; 
+    end
+    
+    
     
     always @(posedge ipclk) begin
-        irst_r <= {irst_r[1:0], prst};
+//        irst_r <= {irst_r[1:0], prst};
     
-        if (irst || (|hispi_eof[i])) vact_ipclk <= 0; // extend output if hact active
+        if (irst || (|hispi_eof)) vact_ipclk <= 0; // extend output if hact active
         else if (|hispi_sof)      vact_ipclk <= 1;
     
         ignore_embedded_ipclk <= ignore_embedded;
@@ -212,25 +234,28 @@ module  sens_hispi12l4#(
        
         rd_line_r <= rd_line;
         
-        if (sol_pclk && !rd_line) good_lanes <= ~rd_run;             // should be off before start
+        if (sol_pclk && !rd_line) good_lanes <= ~rd_run_d;             // should be off before start
         else if (sol_all_dly)     good_lanes <= good_lanes & rd_run; // and now they should be on
         
         fifo_re_r <= fifo_re & rd_run; // when data out is ready, mask if not running
         
         // not using HISPI_NUMLANES here - fix? Will be 0 (not possible in hispi) when no data
-        pxd_out <= ({12 {fifo_re_r[0]}} & fifo_out[0 * 12 +:12]) |
-                   ({12 {fifo_re_r[1]}} & fifo_out[1 * 12 +:12]) |
-                   ({12 {fifo_re_r[2]}} & fifo_out[2 * 12 +:12]) |
-                   ({12 {fifo_re_r[3]}} & fifo_out[3 * 12 +:12]);
+/*        pxd_out <= ({12 {fifo_re_r[0] & rd_run[0]}} & fifo_out[0 * 12 +:12]) |
+                   ({12 {fifo_re_r[1] & rd_run[1]}} & fifo_out[1 * 12 +:12]) |
+                   ({12 {fifo_re_r[2] & rd_run[2]}} & fifo_out[2 * 12 +:12]) |
+                   ({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]); */
        
        if      (prst)                                                 fifo_re <= 0;
        else if (sol_pclk || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
        else                                                           fifo_re <= fifo_re << 1;
        
-       if (prst || hact_off) hact_r <= 0;
+//       if (prst || (hact_off && (|(good_lanes & ~rd_run)))) hact_r <= 0;
+       if (prst || (hact_off && (!rd_line || (good_lanes[3] & ~rd_run[3])))) hact_r <= 0;
        else if (hact_on)                                    hact_r <= 1;
        
-       vact_out <= vact_pclk_strt [0] || hact_r;
+       vact_pclk <= {vact_pclk[0],vact_pclk_strt [0] || hact_r};
+       eof <= vact_pclk[1] && !vact_pclk[0]; 
+//       vact_out <= vact_pclk_strt [0] || hact_r;
     end
 
     dly_16 #(
@@ -248,7 +273,10 @@ module  sens_hispi12l4#(
     ) dly_16_hact_on_i (
         .clk  (pclk),                        // input
         .rst  (1'b0),                        // input
-        .dly  (2),                           // input[3:0] 
+//        .dly  (4'h2),                        // input[3:0] 
+//        .dly  (4'h3),                        // input[3:0] 
+//        .dly  (4'h1),                        // input[3:0] 
+        .dly  (4'h2),                        // input[3:0] 
         .din  (sol_pclk),                    // input[0:0] 
         .dout (hact_on)                      // output[0:0] 
     );
@@ -258,11 +286,25 @@ module  sens_hispi12l4#(
     ) dly_16_hact_off_i (
         .clk  (pclk),                        // input
         .rst  (1'b0),                        // input
-        .dly  (2),                           // input[3:0] 
+//        .dly  (4'h2),                        // input[3:0] 
+//        .dly  (4'h0),                        // input[3:0] 
+//        .dly  (4'h1),                        // input[3:0] 
+        .dly  (4'h2),                        // input[3:0] 
         .din  (fifo_re[HISPI_NUMLANES - 1]), // input[0:0] 
         .dout (hact_off)                     // output[0:0] 
     );
 
+    dly_16 #(
+        .WIDTH(12)
+    ) dly_16_pxd_out_i (
+        .clk  (pclk),                        // input
+        .rst  (1'b0),                        // input
+//        .dly  (4'h2),                        // input[3:0] 
+//        .dly  (4'h0),                        // input[3:0] 
+        .dly  (4'h1),                        // input[3:0] 
+        .din  (pxd_out_pre),                 // input[0:0] 
+        .dout (pxd_out)                      // output[0:0] 
+    );
    
     generate
         genvar i;
@@ -289,7 +331,7 @@ module  sens_hispi12l4#(
                 .ipclk    (ipclk),                     // input
                 .irst     (irst),                      // input
                 .we       (hispi_dv[i]),               // input
-                .sol      (hispi_sol[i] && (hispi_embed[i] || !ignore_embedded_ipclk)), // input
+                .sol      (hispi_sol[i] && !(hispi_embed[i] && ignore_embedded_ipclk)), // input
                 .eol      (hispi_eol[i]),              // input
                 .din      (hispi_aligned[12*i +: 12]), // input[11:0] 
                 .pclk     (pclk),                      // input

sensor/sens_hispi_clock.v

@@ -23,10 +23,11 @@
 module  sens_hispi_clock#(
     
     parameter SENS_PHASE_WIDTH=            8,      // number of bits for te phase counter (depends on divisors)
-    parameter SENS_PCLK_PERIOD =           3.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+//    parameter SENS_PCLK_PERIOD =           3.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter SENS_BANDWIDTH =             "OPTIMIZED",  //"OPTIMIZED", "HIGH","LOW"
 
-    parameter CLKFBOUT_MULT_SENSOR =       4,  // 220 MHz --> 880 MHz
+    parameter CLKIN_PERIOD_SENSOR =        3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+    parameter CLKFBOUT_MULT_SENSOR =       3,      // 330 MHz --> 990 MHz
     parameter CLKFBOUT_PHASE_SENSOR =      0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
     parameter IPCLK_PHASE =                0.000,
     parameter IPCLK2X_PHASE =              0.000,
@@ -91,7 +92,7 @@ module  sens_hispi_clock#(
     // received from the sensor (may need to reset MMCM after resetting sensor)
     mmcm_phase_cntr #(
         .PHASE_WIDTH         (SENS_PHASE_WIDTH),
-        .CLKIN_PERIOD        (SENS_PCLK_PERIOD),
+        .CLKIN_PERIOD        (CLKIN_PERIOD_SENSOR),
         .BANDWIDTH           (SENS_BANDWIDTH),
         .CLKFBOUT_MULT_F     (CLKFBOUT_MULT_SENSOR), // 4
         .DIVCLK_DIVIDE       (SENS_DIVCLK_DIVIDE),
@@ -101,8 +102,8 @@ module  sens_hispi_clock#(
         .CLKFBOUT_USE_FINE_PS("FALSE"),
         .CLKOUT0_USE_FINE_PS ("TRUE"),
         .CLKOUT1_USE_FINE_PS ("TRUE"),
-        .CLKOUT0_DIVIDE_F    (CLKFBOUT_MULT_SENSOR),  // 4  // 8.000),
-        .CLKOUT1_DIVIDE      (CLKFBOUT_MULT_SENSOR / 2), //2 // 4),
+        .CLKOUT0_DIVIDE_F    (CLKFBOUT_MULT_SENSOR * 2),  // 6  // 8.000),
+        .CLKOUT1_DIVIDE      (CLKFBOUT_MULT_SENSOR ), // 3 // 4),
         .COMPENSATION        ("ZHOLD"),
         .REF_JITTER1         (SENS_REF_JITTER1),
         .REF_JITTER2         (SENS_REF_JITTER2),

sensor/sens_hispi_din.v

@@ -53,7 +53,7 @@ module  sens_hispi_din #(
 
     generate
         genvar i;
-        for (i=1; i < HISPI_NUMLANES; i=i+1) begin: din_block
+        for (i=0; i < HISPI_NUMLANES; i=i+1) begin: din_block
             ibufds_ibufgds #(
                 .CAPACITANCE      (HISPI_CAPACITANCE),
                 .DIFF_TERM        (HISPI_DIFF_TERM),
@@ -84,16 +84,17 @@ module  sens_hispi_din #(
             );
             
             iserdes_mem #(
-                .DYN_CLKDIV_INV_EN("FALSE")
+                .DYN_CLKDIV_INV_EN ("FALSE"),
+                .MSB_FIRST         (1)          // MSB is received first
             ) iserdes_pxd_i (
-                .iclk(ipclk2x),           // source-synchronous clock
-                .oclk(ipclk2x),           // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
-                .oclk_div(ipclk),         // oclk divided by 2, front aligned
-                .inv_clk_div(1'b0),       // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
-                .rst(irst),               // reset
-                .d_direct(1'b0),          // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
-                .ddly(din_dly[i]),        // serial input from idelay 
-                .dout(dout[4*i +:4]),     // parallel data out
+                .iclk         (ipclk2x),       // source-synchronous clock
+                .oclk         (ipclk2x),       // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
+                .oclk_div     (ipclk),         // oclk divided by 2, front aligned
+                .inv_clk_div  (1'b0),          // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
+                .rst          (irst),          // reset
+                .d_direct     (1'b0),          // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
+                .ddly         (din_dly[i]),    // serial input from idelay 
+                .dout         (dout[4*i +:4]), // parallel data out
                 .comb_out()                    // output
             );
         

sensor/sens_hispi_fifo.v

@@ -46,13 +46,13 @@ module  sens_hispi_fifo#(
     reg                  run_r;
     
     assign run = run_r;
-    
+    // TODO: generate early done by comparing ra with (wa-1) - separate counter
     
     always @ (posedge ipclk) begin
         if      (irst ||sol)           wa <= 0;
         else if (we && line_run_ipclk) wa <= wa + 1;
         
-        if (we && line_run_ipclk) fifo_ram[wa] <= din;
+        if (we && line_run_ipclk) fifo_ram[wa[DATA_DEPTH-1:0]] <= din;
         
         if (irst || eol) line_run_ipclk <= 0;
         else if (sol)    line_run_ipclk <= 1;
@@ -68,7 +68,7 @@ module  sens_hispi_fifo#(
         if (prst ||line_start_pclk) ra <= 0;
         else if (re)                ra <= ra + 1;
         
-        if (re) dout <= fifo_ram[ra];
+        if (re) dout <= fifo_ram[ra[DATA_DEPTH-1:0]];
         
     end
     

sensor/sens_hispi_lane.v

@@ -79,7 +79,8 @@ module  sens_hispi_lane#(
 
     assign num_trail_1_w = (&din) ? 3'h4 : ((&din[2:0]) ? 3'h3 : ((&din[1:0]) ? 3'h2 :((&din[0]) ? 3'h1 : 3'h0)));
     assign num_lead_1_w =  (&din) ? 3'h4 : ((&din[3:1]) ? 3'h3 : ((&din[3:2]) ? 3'h2 :((&din[3]) ? 3'h1 : 3'h0)));
-    assign zero_after_ones_w = !((din[0] && !din[1]) || (din[1] && !din[2]) || (din[2] && !din[3]) || (d_r[3] && !din[0]));
+//    assign zero_after_ones_w = !((din[0] && !din[1]) || (din[1] && !din[2]) || (din[2] && !din[3]) || (d_r[3] && !din[0]));
+    assign zero_after_ones_w = !((din[0] && !din[1]) || (din[1] && !din[2]) || (din[2] && !din[3]) || (din[3] && !d_r[0]));
     
     always @(posedge ipclk) begin
         d_r <= din;
@@ -100,7 +101,8 @@ module  sens_hispi_lane#(
         // Saturate number with 24 (5'h18), but only first transition from <24 to >=24 is used for sync
         // detection.
         if      (irst || !num_running_ones[3]) num_running_zeros <= 0;
-        else if (!num_running_ones[2])         num_running_zeros <= {2'b0,num_trail_0_w};
+//        else if (!num_running_ones[2])         num_running_zeros <= {2'b0,num_trail_0_w};
+        else if (prev4ones)                    num_running_zeros <= {2'b0,num_trail_0_w};
         else                                   num_running_zeros <= (&num_running_zeros[4:3])? 5'h18 : num_running_zeros_w;
 
         if (irst) got_sync <= 0;
@@ -109,13 +111,16 @@ module  sens_hispi_lane#(
         // got_sync should also abort data run - delayed by 10 clocks
         
         if      (irst)       shift_val <= 0;
-        else if (got_sync) shift_val <= num_first_zeros;
+//      else if (got_sync)   shift_val <= num_first_zeros;
+        else if (got_sync_w) shift_val <= num_first_zeros;
         
         case (shift_val)
             2'h0: barrel <= din;
-            2'h1: barrel <= {d_r[2:0], din[3]};
+//            2'h1: barrel <= {d_r[2:0], din[3]};
+            2'h1: barrel <= {d_r[0],   din[3:1]};
             2'h2: barrel <= {d_r[1:0], din[3:2]};
-            2'h3: barrel <= {d_r[0],   din[3:1]};
+//            2'h3: barrel <= {d_r[0],   din[3:1]};
+            2'h3: barrel <= {d_r[2:0], din[3]};
         endcase
 
         if      (irst)     sync_decode <= 0;
@@ -174,7 +179,7 @@ module  sens_hispi_lane#(
     ) dly_16_dout_i (
         .clk  (ipclk), // input
         .rst  (1'b0),  // input
-        .dly  (8),     // input[3:0] 
+        .dly  (4'h8),     // input[3:0] 
         .din  (HISPI_MSB_FIRST ? barrel :{barrel[0],barrel[1],barrel[2],barrel[3]}), // input[0:0] 
         .dout (dout_w) // output[0:0] 
     );
@@ -183,7 +188,7 @@ module  sens_hispi_lane#(
     ) dly_16_pre_start_line_i (
         .clk  (ipclk), // input
         .rst  (1'b0),  // input
-        .dly  (7),     // input[3:0] 
+        .dly  (4'h7),     // input[3:0] 
         .din  (start_line), // input[0:0] 
         .dout (start_line_d) // output[0:0] 
     );

sensor/sens_parallel12.v

@@ -59,9 +59,10 @@ module  sens_parallel12 #(
     parameter SENS_HIGH_PERFORMANCE_MODE =    "FALSE",
     
     parameter SENS_PHASE_WIDTH=               8,      // number of bits for te phase counter (depends on divisors)
-    parameter SENS_PCLK_PERIOD =              10.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+//    parameter SENS_PCLK_PERIOD =              10.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter SENS_BANDWIDTH =                "OPTIMIZED",  //"OPTIMIZED", "HIGH","LOW"
 
+    parameter CLKIN_PERIOD_SENSOR =   10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter CLKFBOUT_MULT_SENSOR =   8,  // 100 MHz --> 800 MHz
     parameter CLKFBOUT_PHASE_SENSOR =  0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
     parameter IPCLK_PHASE =            0.000,
@@ -642,7 +643,7 @@ module  sens_parallel12 #(
     // received from the sensor (may need to reset MMCM after resetting sensor)
     mmcm_phase_cntr #(
         .PHASE_WIDTH         (SENS_PHASE_WIDTH),
-        .CLKIN_PERIOD        (SENS_PCLK_PERIOD),
+        .CLKIN_PERIOD        (CLKIN_PERIOD_SENSOR), // SENS_PCLK_PERIOD), assuming both sources have the same frequency!
         .BANDWIDTH           (SENS_BANDWIDTH),
         .CLKFBOUT_MULT_F     (CLKFBOUT_MULT_SENSOR), //8
         .DIVCLK_DIVIDE       (SENS_DIVCLK_DIVIDE),

sensor/sensor_channel.v

@@ -136,11 +136,20 @@ module  sensor_channel#(
         parameter SENS_CTRL_ARST =        2,  //  3: 2
         parameter SENS_CTRL_ARO =         4,  //  5: 4
         parameter SENS_CTRL_RST_MMCM =    6,  //  7: 6
+`ifdef HISPI
+        parameter SENS_CTRL_IGNORE_EMBED =8,  //  9: 8
+`else        
         parameter SENS_CTRL_EXT_CLK =     8,  //  9: 8
+`endif        
         parameter SENS_CTRL_LD_DLY =     10,  // 10
+`ifdef HISPI
+        parameter SENS_CTRL_GP0=      12,  // 13:12
+        parameter SENS_CTRL_GP1=      14,  // 15:14
+`else        
         parameter SENS_CTRL_QUADRANTS =  12,  // 17:12, enable - 20
         parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
         parameter SENS_CTRL_QUADRANTS_EN =   20,  // 17:12, enable - 20 (2 bits reserved)
+`endif        
       parameter SENSIO_STATUS =         'h1,
       parameter SENSIO_JTAG =           'h2,
         // SENSIO_JTAG register bits
@@ -149,7 +158,9 @@ module  sensor_channel#(
         parameter SENS_JTAG_TCK =         4,
         parameter SENS_JTAG_TMS =         2,
         parameter SENS_JTAG_TDI =         0,
+`ifndef HISPI
       parameter SENSIO_WIDTH =          'h3, // 1.. 2^16, 0 - use HACT
+`endif      
       parameter SENSIO_DELAYS =         'h4, // 'h4..'h7
         // 4 of 8-bit delays per register
     // sensor_i2c_io command/data write registers s (relative to SENSOR_BASE_ADDR)
@@ -173,11 +184,12 @@ module  sensor_channel#(
     parameter SENSI2C_IOSTANDARD =    "DEFAULT",
     parameter SENSI2C_SLEW =          "SLOW",
     
+`ifndef HISPI
     //sensor_fifo parameters
     parameter SENSOR_DATA_WIDTH =      12,
     parameter SENSOR_FIFO_2DEPTH =     4,
     parameter SENSOR_FIFO_DELAY =      5, // 7,
-    
+`endif    
     
     // sens_parallel12 other parameters
     
@@ -189,15 +201,31 @@ module  sensor_channel#(
     parameter PXD_SLEW = "SLOW",
     parameter real SENS_REFCLK_FREQUENCY =    300.0,
     parameter SENS_HIGH_PERFORMANCE_MODE =    "FALSE",
+`ifdef HISPI
+    parameter PXD_CAPACITANCE =          "DONT_CARE",
+    parameter PXD_CLK_DIV =              10, // 220MHz -> 22MHz
+    parameter PXD_CLK_DIV_BITS =          4,
+`endif    
     
     parameter SENS_PHASE_WIDTH=        8,      // number of bits for te phase counter (depends on divisors)
     parameter SENS_PCLK_PERIOD =       10.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter SENS_BANDWIDTH =         "OPTIMIZED",  //"OPTIMIZED", "HIGH","LOW"
 
+    // parameters for the sensor-synchronous clock PLL
+`ifdef HISPI    
+    parameter CLKIN_PERIOD_SENSOR =      3.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+    parameter CLKFBOUT_MULT_SENSOR =     3,      // 330 MHz --> 990 MHz
+    parameter CLKFBOUT_PHASE_SENSOR =    0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
+    parameter IPCLK_PHASE =              0.000,
+    parameter IPCLK2X_PHASE =            0.000,
+`else    
+    parameter CLKIN_PERIOD_SENSOR =      10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter CLKFBOUT_MULT_SENSOR =     8,      // 100 MHz --> 800 MHz
     parameter CLKFBOUT_PHASE_SENSOR =    0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
     parameter IPCLK_PHASE =              0.000,
     parameter IPCLK2X_PHASE =            0.000,
+`endif
+    
     parameter BUF_IPCLK =             "BUFR",
     parameter BUF_IPCLK2X =           "BUFR",  
 
@@ -207,12 +235,25 @@ module  sensor_channel#(
     parameter SENS_SS_EN         =     "FALSE",      // Enables Spread Spectrum mode
     parameter SENS_SS_MODE       =     "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
     parameter SENS_SS_MOD_PERIOD =     10000        // integer 4000-40000 - SS modulation period in ns
+    
+`ifdef HISPI
+   ,parameter HISPI_MSB_FIRST =            0,
+    parameter HISPI_NUMLANES =             4,
+    parameter HISPI_CAPACITANCE =         "DONT_CARE",
+    parameter HISPI_DIFF_TERM =           "TRUE",
+    parameter HISPI_DQS_BIAS =            "TRUE",
+    parameter HISPI_IBUF_DELAY_VALUE =    "0",
+    parameter HISPI_IBUF_LOW_PWR =        "TRUE",
+    parameter HISPI_IFD_DELAY_VALUE =     "AUTO",
+    parameter HISPI_IOSTANDARD =          "DEFAULT"
+`endif    
+    
 `ifdef DEBUG_RING
         ,parameter DEBUG_CMD_LATENCY = 2 
 `endif        
     
 ) (
-//    input         rst,
+
     input         pclk,   // global clock input, pixel rate (96MHz for MT9P006)
     // TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones)
     // How to erase?
@@ -225,11 +266,20 @@ module  sensor_channel#(
     // I/O pads, pin names match circuit diagram
     inout   [7:0] sns_dp,
     inout   [7:0] sns_dn,
+`ifdef HISPI   
+    input         sns_clkp,
+    input         sns_clkn,
+`else
     inout         sns_clkp,
     inout         sns_clkn,
+`endif    
     inout         sns_scl,
     inout         sns_sda,
+`ifdef HISPI   
+    output        sns_ctl,
+`else    
     inout         sns_ctl,
+`endif    
     inout         sns_pg,
     // programming interface
     input         mclk,     // global clock, half DDR3 clock, synchronizes all I/O through the command port
@@ -301,16 +351,16 @@ module  sensor_channel#(
     wire   [7:0] sens_i2c_status_ad;
     wire         sens_i2c_status_rq;
     wire         sens_i2c_status_start;
-    wire   [7:0] sens_par12_status_ad;
-    wire         sens_par12_status_rq;
-    wire         sens_par12_status_start;
+    wire   [7:0] sens_phys_status_ad;
+    wire         sens_phys_status_rq;
+    wire         sens_phys_status_start;
     
+`ifndef HISPI        
     wire         ipclk;   // Use in FIFO
-//    wire         ipclk2x; // Use in FIFO?
     wire  [11:0] pxd_to_fifo;
     wire         vact_to_fifo;    // frame active @posedge  ipclk
     wire         hact_to_fifo;    // line active @posedge  ipclk
-    
+`endif    
     // data from FIFO
     wire  [11:0] pxd;     // TODO: align MSB? parallel data, @posedge  ipclk
     wire         hact;    // line active @posedge  ipclk
@@ -468,9 +518,9 @@ module  sensor_channel#(
         .db_in0    (sens_i2c_status_ad),      // input[7:0] 
         .rq_in0    (sens_i2c_status_rq),      // input
         .start_in0 (sens_i2c_status_start),   // output
-        .db_in1    (sens_par12_status_ad),    // input[7:0] 
-        .rq_in1    (sens_par12_status_rq),    // input
-        .start_in1 (sens_par12_status_start), // output
+        .db_in1    (sens_phys_status_ad),    // input[7:0] 
+        .rq_in1    (sens_phys_status_rq),    // input
+        .start_in1 (sens_phys_status_start), // output
         .db_out    (status_ad),               // output[7:0] 
         .rq_out    (status_rq),               // output
         .start_out (status_start)             // input
@@ -540,57 +590,47 @@ module  sensor_channel#(
         .sda                   (sns_sda)                // inout
     );
 
-//    wire [3:0] debug_hist_mclk;
-    wire irst; // @ posedge ipclk
-    localparam STATUS_ALIVE_WIDTH = 8;
-    wire [STATUS_ALIVE_WIDTH - 1 : 0] status_alive;
+// debug_hist_mclk is never active, alive_hist0_rq == 0
+//    assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
+//    assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
+`ifndef HISPI    
     reg  hact_r; // hact delayed by 1 cycle to generate start pulse
+    reg dout_valid_d_pclk; //@ pclk - delayed by 1 clk from dout_valid to detect edge
+    reg last_in_line_d_pclk; //@ pclk - delayed by 1 clk from last_in_line to detect edge
+    reg hist_rq0_r;
+    reg hist_gr0_r;
     wire sol_mclk;
     wire sof_mclk;
     wire eof_mclk;
-    reg hist_rq0_r;
-    reg hist_gr0_r;
     wire alive_hist0_rq = hist_rq[0] && !hist_rq0_r;
     wire alive_hist0_gr = hist_gr[0] && !hist_gr0_r;
     // sof_out_mclk - already exists
-    reg dout_valid_d_pclk; //@ pclk - delayed by 1 clk from dout_valid to detect edge
-    reg last_in_line_d_pclk; //@ pclk - delayed by 1 clk from last_in_line to detect edge
     wire dout_valid_1cyc_mclk;
     wire last_in_line_1cyc_mclk;
-// debug_hist_mclk is never active, alive_hist0_rq == 0
-//    assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
-//    assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
-    assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
-/*
- sof, hact are tested to be active
-
-                .sof        (gamma_sof_out),  // input
-                .hact       (gamma_hact_out), // input
+//    wire [3:0] debug_hist_mclk;
+    wire irst; // @ posedge ipclk
+    localparam STATUS_ALIVE_WIDTH = 8;
+    wire [STATUS_ALIVE_WIDTH - 1 : 0] status_alive;
+    assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq,
+                            sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
+    always @ (posedge mclk) begin
+        hist_rq0_r <= hist_rq[0];
+        hist_gr0_r <= hist_gr[0];
+    end
 
-*/    
     always @ (posedge pclk) begin
-//        hact_r <= hact;
         hact_r <= gamma_hact_out;
         dout_valid_d_pclk <= dout_valid;
         last_in_line_d_pclk <= last_in_line;
     end
     
-    always @ (posedge mclk) begin
-//        hist_rq0_r <= en_mclk & (hist_rq[0] ^ hist_rq0_r);
-        hist_rq0_r <= hist_rq[0];
-        hist_gr0_r <= hist_gr[0];
-    end
 
-    /*
-                .hist_rq    (hist_rq[0]),     // output
-                .hist_grant (hist_gr[0]),     // input
-    */
-// for debug/test alive   
+    // for debug/test alive   
         pulse_cross_clock pulse_cross_clock_sol_mclk_i (
             .rst         (prst),                  // input
             .src_clk     (pclk),                  // input
             .dst_clk     (mclk),                  // input
-//        .in_pulse    (hact && !hact_r),       // input
+    //        .in_pulse    (hact && !hact_r),       // input
             .in_pulse    (gamma_hact_out && !hact_r),       // input
             .out_pulse   (sol_mclk),              // output
             .busy() // output
@@ -600,7 +640,7 @@ module  sensor_channel#(
             .rst         (prst),                  // input
             .src_clk     (pclk),                  // input
             .dst_clk     (mclk),                  // input
-//        .in_pulse    (sof),                   // input
+    //        .in_pulse    (sof),                   // input
             .in_pulse    (gamma_sof_out),         // input
             .out_pulse   (sof_mclk),              // output
             .busy() // output
@@ -633,7 +673,102 @@ module  sensor_channel#(
             .busy() // output
         );
     
+`endif    
+
     
+
+
+`ifdef HISPI
+        sens_10398 #(
+            .SENSIO_ADDR            (SENSIO_ADDR),
+            .SENSIO_ADDR_MASK       (SENSIO_ADDR_MASK),
+            .SENSIO_CTRL            (SENSIO_CTRL),
+            .SENSIO_STATUS          (SENSIO_STATUS),
+            .SENSIO_JTAG            (SENSIO_JTAG),
+            .SENSIO_DELAYS          (SENSIO_DELAYS),
+            .SENSIO_STATUS_REG      (SENSIO_STATUS_REG),
+            .SENS_JTAG_PGMEN        (SENS_JTAG_PGMEN),
+            .SENS_JTAG_PROG         (SENS_JTAG_PROG),
+            .SENS_JTAG_TCK          (SENS_JTAG_TCK),
+            .SENS_JTAG_TMS          (SENS_JTAG_TMS),
+            .SENS_JTAG_TDI          (SENS_JTAG_TDI),
+            .SENS_CTRL_MRST         (SENS_CTRL_MRST),
+            .SENS_CTRL_ARST         (SENS_CTRL_ARST),
+            .SENS_CTRL_ARO          (SENS_CTRL_ARO),
+            .SENS_CTRL_RST_MMCM     (SENS_CTRL_RST_MMCM),
+            .SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
+            .SENS_CTRL_LD_DLY       (SENS_CTRL_LD_DLY),
+            .SENS_CTRL_GP0          (SENS_CTRL_GP0),
+            .SENS_CTRL_GP1          (SENS_CTRL_GP1),
+            .IODELAY_GRP            (IODELAY_GRP),
+            .IDELAY_VALUE           (IDELAY_VALUE),
+            .REFCLK_FREQUENCY       (SENS_REFCLK_FREQUENCY),
+            .HIGH_PERFORMANCE_MODE  (SENS_HIGH_PERFORMANCE_MODE),
+            .SENS_PHASE_WIDTH       (SENS_PHASE_WIDTH),
+//            .SENS_PCLK_PERIOD       (SENS_PCLK_PERIOD),
+            .SENS_BANDWIDTH         (SENS_BANDWIDTH),
+            .CLKIN_PERIOD_SENSOR    (CLKIN_PERIOD_SENSOR),
+            .CLKFBOUT_MULT_SENSOR   (CLKFBOUT_MULT_SENSOR),
+            .CLKFBOUT_PHASE_SENSOR  (CLKFBOUT_PHASE_SENSOR),
+            .IPCLK_PHASE            (IPCLK_PHASE),
+            .IPCLK2X_PHASE          (IPCLK2X_PHASE),
+            .BUF_IPCLK              (BUF_IPCLK),
+            .BUF_IPCLK2X            (BUF_IPCLK2X),
+            .SENS_DIVCLK_DIVIDE     (SENS_DIVCLK_DIVIDE),
+            .SENS_REF_JITTER1       (SENS_REF_JITTER1),
+            .SENS_REF_JITTER2       (SENS_REF_JITTER2),
+            .SENS_SS_EN             (SENS_SS_EN),
+            .SENS_SS_MODE           (SENS_SS_MODE),
+            .SENS_SS_MOD_PERIOD     (SENS_SS_MOD_PERIOD),
+            .HISPI_MSB_FIRST        (HISPI_MSB_FIRST),
+            .HISPI_NUMLANES         (HISPI_NUMLANES),
+            .HISPI_CAPACITANCE      (HISPI_CAPACITANCE),
+            .HISPI_DIFF_TERM        (HISPI_DIFF_TERM),
+            .HISPI_DQS_BIAS         (HISPI_DQS_BIAS),
+            .HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
+            .HISPI_IBUF_LOW_PWR     (HISPI_IBUF_LOW_PWR),
+            .HISPI_IFD_DELAY_VALUE  (HISPI_IFD_DELAY_VALUE),
+            .HISPI_IOSTANDARD       (HISPI_IOSTANDARD),
+            .PXD_DRIVE              (PXD_DRIVE),
+            .PXD_IBUF_LOW_PWR       (PXD_IBUF_LOW_PWR),
+            .PXD_IOSTANDARD         (PXD_IOSTANDARD),
+            .PXD_SLEW               (PXD_SLEW),
+            .PXD_CAPACITANCE        (PXD_CAPACITANCE),
+            .PXD_CLK_DIV            (PXD_CLK_DIV),
+            .PXD_CLK_DIV_BITS       (PXD_CLK_DIV_BITS)
+        ) sens_10398_i (
+            .pclk             (pclk),                   // input
+            .prst             (prst),                   // input
+            .mclk             (mclk),                   // input
+            .mrst             (mrst),                   // input
+            .cmd_ad           (cmd_ad),                 // input[7:0] 
+            .cmd_stb          (cmd_stb),                // input
+            .status_ad        (sens_phys_status_ad),    // output[7:0] 
+            .status_rq        (sens_phys_status_rq),    // output
+            .status_start     (sens_phys_status_start), // input
+            .trigger_mode     (trigger_mode),           // input
+            .trig             (trig),                   // input
+            .sns_dp           (sns_dp[3:0]),            // input[3:0] 
+            .sns_dn           (sns_dn[3:0]),            // input[3:0] 
+            .sns_clkp         (sns_clkp),               // input
+            .sns_clkn         (sns_clkn),               // input
+            .sens_ext_clk_p   (sns_dp[6]),              // output
+            .sens_ext_clk_n   (sns_dn[6]),              // output
+            .sns_pgm          (sns_pg),                 // inout
+            .sns_ctl_tck      (sns_ctl),                // output
+            .sns_mrst         (sns_dp[7]),              // output
+            .sns_arst_tms     (sns_dn[7]),              // output
+            .sns_gp0_tdi      (sns_dp[5]),              // output
+            .sns_gp1          (sns_dn[5]),              // output
+            .sns_flash_tdo    (sns_dp[4]),              // input
+            .sns_shutter_done (sns_dn[4]),              // input
+            .pxd              (pxd),                    // output[11:0] 
+            .hact             (hact),                   // output
+            .sof              (sof),                    // output
+            .eof              (eof)                     // output
+        );
+
+`else    
         sens_parallel12 #(
             .SENSIO_ADDR           (SENSIO_ADDR),
             .SENSIO_ADDR_MASK      (SENSIO_ADDR_MASK),
@@ -666,8 +801,9 @@ module  sensor_channel#(
             .SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
             .SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
             .SENS_PHASE_WIDTH      (SENS_PHASE_WIDTH),
-        .SENS_PCLK_PERIOD      (SENS_PCLK_PERIOD),
+//            .SENS_PCLK_PERIOD      (SENS_PCLK_PERIOD),
             .SENS_BANDWIDTH        (SENS_BANDWIDTH),
+            .CLKIN_PERIOD_SENSOR   (CLKIN_PERIOD_SENSOR),
             .CLKFBOUT_MULT_SENSOR  (CLKFBOUT_MULT_SENSOR),
             .CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
             .IPCLK_PHASE           (IPCLK_PHASE),
@@ -707,9 +843,9 @@ module  sensor_channel#(
             .mclk                 (mclk),                   // input
             .cmd_ad               (cmd_ad),                 // input[7:0] 
             .cmd_stb              (cmd_stb),                // input
-        .status_ad            (sens_par12_status_ad),   // output[7:0] 
-        .status_rq            (sens_par12_status_rq),   // output
-        .status_start         (sens_par12_status_start) // input
+            .status_ad            (sens_phys_status_ad),   // output[7:0] 
+            .status_rq            (sens_phys_status_rq),   // output
+            .status_start         (sens_phys_status_start) // input
         );
     
         sensor_fifo #(
@@ -717,7 +853,7 @@ module  sensor_channel#(
             .SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
             .SENSOR_FIFO_DELAY  (SENSOR_FIFO_DELAY)
         ) sensor_fifo_i (
-//        .rst         (rst),        // input
+    //        .rst         (rst),        // input
             .iclk        (ipclk),        // input
             .pclk        (pclk),         // input
             .prst        (prst),         // input
@@ -730,7 +866,7 @@ module  sensor_channel#(
             .sof         (sof),          // output @posedge pclk
             .eof         (eof)           // output @posedge pclk
         );
-
+`endif
     sens_sync #(
         .SENS_SYNC_ADDR       (SENS_SYNC_ADDR),
         .SENS_SYNC_MASK       (SENS_SYNC_MASK),
@@ -893,10 +1029,7 @@ module  sensor_channel#(
                 .debug_di     (debug_ring[1])          // input
 `endif         
             );
-//`ifdef DEBUG_RING       
-//            assign debug_ring[0] = debug_ring[1]; // just bypass
-//            assign tmp1 = debug_ring[1]; // just bypass
-//`endif
+
     endgenerate
     
     

sensor/sensors393.v

@@ -136,11 +136,20 @@ module  sensors393 #(
         parameter SENS_CTRL_ARST =        2,  //  3: 2
         parameter SENS_CTRL_ARO =         4,  //  5: 4
         parameter SENS_CTRL_RST_MMCM =    6,  //  7: 6
+`ifdef HISPI
+        parameter SENS_CTRL_IGNORE_EMBED =8,  //  9: 8
+`else        
         parameter SENS_CTRL_EXT_CLK =     8,  //  9: 8
+`endif        
         parameter SENS_CTRL_LD_DLY =     10,  // 10
+`ifdef HISPI
+        parameter SENS_CTRL_GP0=      12,  // 13:12
+        parameter SENS_CTRL_GP1=      14,  // 15:14
+`else        
         parameter SENS_CTRL_QUADRANTS =  12,  // 17:12, enable - 20
         parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
         parameter SENS_CTRL_QUADRANTS_EN =   20,  // 17:12, enable - 20 (2 bits reserved)
+`endif        
       parameter SENSIO_STATUS =         'h1,
       parameter SENSIO_JTAG =           'h2,
         // SENSIO_JTAG register bits
@@ -149,7 +158,9 @@ module  sensors393 #(
         parameter SENS_JTAG_TCK =         4,
         parameter SENS_JTAG_TMS =         2,
         parameter SENS_JTAG_TDI =         0,
+`ifndef HISPI
       parameter SENSIO_WIDTH =          'h3, // 1.. 2^16, 0 - use HACT
+`endif      
       parameter SENSIO_DELAYS =         'h4, // 'h4..'h7
         // 4 of 8-bit delays per register
     // sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
@@ -173,10 +184,12 @@ module  sensors393 #(
     parameter SENSI2C_IOSTANDARD =       "DEFAULT",
     parameter SENSI2C_SLEW =             "SLOW",
     
+`ifndef HISPI
     //sensor_fifo parameters
     parameter SENSOR_DATA_WIDTH =      12,
     parameter SENSOR_FIFO_2DEPTH =     4,
     parameter SENSOR_FIFO_DELAY =      5, // 7,
+`endif    
     // other parameters for histogram_saxi module
     parameter HIST_SAXI_ADDR_MASK =      'h7f0,
       parameter HIST_SAXI_MODE_WIDTH =   8,
@@ -206,15 +219,29 @@ module  sensors393 #(
     parameter PXD_SLEW =                 "SLOW",
     parameter real SENS_REFCLK_FREQUENCY =    300.0,
     parameter SENS_HIGH_PERFORMANCE_MODE =    "FALSE",
-    
+`ifdef HISPI
+    parameter PXD_CAPACITANCE =          "DONT_CARE",
+    parameter PXD_CLK_DIV =              10, // 220MHz -> 22MHz
+    parameter PXD_CLK_DIV_BITS =          4,
+`endif    
     parameter SENS_PHASE_WIDTH=               8,      // number of bits for te phase counter (depends on divisors)
     parameter SENS_PCLK_PERIOD =              10.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter SENS_BANDWIDTH =                "OPTIMIZED",  //"OPTIMIZED", "HIGH","LOW"
 
+    // parameters for the sensor-synchronous clock PLL
+`ifdef HISPI    
+    parameter CLKIN_PERIOD_SENSOR =      3.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+    parameter CLKFBOUT_MULT_SENSOR =     3,      // 330 MHz --> 990 MHz
+    parameter CLKFBOUT_PHASE_SENSOR =    0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
+    parameter IPCLK_PHASE =              0.000,
+    parameter IPCLK2X_PHASE =            0.000,
+`else    
+    parameter CLKIN_PERIOD_SENSOR =      10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
     parameter CLKFBOUT_MULT_SENSOR =     8,      // 100 MHz --> 800 MHz
     parameter CLKFBOUT_PHASE_SENSOR =    0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
     parameter IPCLK_PHASE =              0.000,
     parameter IPCLK2X_PHASE =            0.000,
+`endif
 //    parameter BUF_IPCLK =                "BUFR",
 //    parameter BUF_IPCLK2X =              "BUFR",  
     parameter BUF_IPCLK_SENS0 =          "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
@@ -236,6 +263,18 @@ module  sensors393 #(
     parameter SENS_SS_EN         =       "FALSE",      // Enables Spread Spectrum mode
     parameter SENS_SS_MODE       =       "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
     parameter SENS_SS_MOD_PERIOD =       10000        // integer 4000-40000 - SS modulation period in ns
+`ifdef HISPI
+   ,parameter HISPI_MSB_FIRST =            0,
+    parameter HISPI_NUMLANES =             4,
+    parameter HISPI_CAPACITANCE =         "DONT_CARE",
+    parameter HISPI_DIFF_TERM =           "TRUE",
+    parameter HISPI_DQS_BIAS =            "TRUE",
+    parameter HISPI_IBUF_DELAY_VALUE =    "0",
+    parameter HISPI_IBUF_LOW_PWR =        "TRUE",
+    parameter HISPI_IFD_DELAY_VALUE =     "AUTO",
+    parameter HISPI_IOSTANDARD =          "DEFAULT"
+`endif    
+    
 `ifdef DEBUG_RING
         ,parameter DEBUG_CMD_LATENCY = 2 
 `endif        
@@ -262,11 +301,21 @@ module  sensors393 #(
     // I/O pads, pin names match circuit diagram (each sensor)
     inout  [31:0] sns_dp,
     inout  [31:0] sns_dn,
+`ifdef HISPI    
+    inout   [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
+    inout   [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
+`else
     inout   [3:0] sns_clkp,
     inout   [3:0] sns_clkn,
+`endif    
     inout   [3:0] sns_scl,
     inout   [3:0] sns_sda,
+    
+`ifdef HISPI    
+    inout   [3:0] sns_ctl, // SuppressThisWarning all - output-only in HiSPi mode
+`else    
     inout   [3:0] sns_ctl,
+`endif    
     inout   [3:0] sns_pg,
     
     // Memory interface (4 channels)
@@ -453,11 +502,20 @@ module  sensors393 #(
                 .SENS_CTRL_ARST                (SENS_CTRL_ARST),
                 .SENS_CTRL_ARO                 (SENS_CTRL_ARO),
                 .SENS_CTRL_RST_MMCM            (SENS_CTRL_RST_MMCM),
+`ifdef HISPI                
+                .SENS_CTRL_IGNORE_EMBED        (SENS_CTRL_IGNORE_EMBED),
+`else                
                 .SENS_CTRL_EXT_CLK             (SENS_CTRL_EXT_CLK),
+`endif                
                 .SENS_CTRL_LD_DLY              (SENS_CTRL_LD_DLY),
+`ifdef HISPI
+                .SENS_CTRL_GP0                 (SENS_CTRL_GP0),
+                .SENS_CTRL_GP1                 (SENS_CTRL_GP1),
+`else        
                 .SENS_CTRL_QUADRANTS           (SENS_CTRL_QUADRANTS),
                 .SENS_CTRL_QUADRANTS_WIDTH     (SENS_CTRL_QUADRANTS_WIDTH),
                 .SENS_CTRL_QUADRANTS_EN        (SENS_CTRL_QUADRANTS_EN),
+`endif                
                 .SENSIO_STATUS                 (SENSIO_STATUS),
                 .SENSIO_JTAG                   (SENSIO_JTAG),
                 .SENS_JTAG_PGMEN               (SENS_JTAG_PGMEN),
@@ -465,7 +523,9 @@ module  sensors393 #(
                 .SENS_JTAG_TCK                 (SENS_JTAG_TCK),
                 .SENS_JTAG_TMS                 (SENS_JTAG_TMS),
                 .SENS_JTAG_TDI                 (SENS_JTAG_TDI),
+`ifndef HISPI
                 .SENSIO_WIDTH                  (SENSIO_WIDTH),
+`endif                
                 .SENSIO_DELAYS                 (SENSIO_DELAYS),
                 .SENSI2C_ABS_RADDR             (SENSI2C_ABS_RADDR),
                 .SENSI2C_REL_RADDR             (SENSI2C_REL_RADDR),
@@ -477,14 +537,15 @@ module  sensors393 #(
                 .HISTOGRAM_ADDR_MASK           (HISTOGRAM_ADDR_MASK),
                 .HISTOGRAM_LEFT_TOP            (HISTOGRAM_LEFT_TOP),
                 .HISTOGRAM_WIDTH_HEIGHT        (HISTOGRAM_WIDTH_HEIGHT),
-                
                 .SENSI2C_DRIVE                 (SENSI2C_DRIVE),
                 .SENSI2C_IBUF_LOW_PWR          (SENSI2C_IBUF_LOW_PWR),
                 .SENSI2C_IOSTANDARD            (SENSI2C_IOSTANDARD),
                 .SENSI2C_SLEW                  (SENSI2C_SLEW),
+`ifndef HISPI
                 .SENSOR_DATA_WIDTH             (SENSOR_DATA_WIDTH),
                 .SENSOR_FIFO_2DEPTH            (SENSOR_FIFO_2DEPTH),
                 .SENSOR_FIFO_DELAY             (SENSOR_FIFO_DELAY),
+`endif                
                 .IODELAY_GRP                   ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
                 .IDELAY_VALUE                  (IDELAY_VALUE),
                 .PXD_DRIVE                     (PXD_DRIVE),
@@ -493,9 +554,15 @@ module  sensors393 #(
                 .PXD_SLEW                      (PXD_SLEW),
                 .SENS_REFCLK_FREQUENCY         (SENS_REFCLK_FREQUENCY),
                 .SENS_HIGH_PERFORMANCE_MODE    (SENS_HIGH_PERFORMANCE_MODE),
+`ifdef HISPI
+                .PXD_CAPACITANCE               (PXD_CAPACITANCE),
+                .PXD_CLK_DIV                   (PXD_CLK_DIV),
+                .PXD_CLK_DIV_BITS              (PXD_CLK_DIV_BITS),
+`endif
                 .SENS_PHASE_WIDTH              (SENS_PHASE_WIDTH),
                 .SENS_PCLK_PERIOD              (SENS_PCLK_PERIOD),
                 .SENS_BANDWIDTH                (SENS_BANDWIDTH),
+                .CLKIN_PERIOD_SENSOR        (CLKIN_PERIOD_SENSOR),
                 .CLKFBOUT_MULT_SENSOR          (CLKFBOUT_MULT_SENSOR),
                 .CLKFBOUT_PHASE_SENSOR         (CLKFBOUT_PHASE_SENSOR),
                 .IPCLK_PHASE                   (IPCLK_PHASE),
@@ -508,11 +575,22 @@ module  sensors393 #(
                 .SENS_SS_EN                    (SENS_SS_EN),
                 .SENS_SS_MODE                  (SENS_SS_MODE),
                 .SENS_SS_MOD_PERIOD            (SENS_SS_MOD_PERIOD)
+`ifdef HISPI
+               ,.HISPI_MSB_FIRST               (HISPI_MSB_FIRST),
+                .HISPI_NUMLANES                (HISPI_NUMLANES),
+                .HISPI_CAPACITANCE             (HISPI_CAPACITANCE),
+                .HISPI_DIFF_TERM               (HISPI_DIFF_TERM),
+                .HISPI_DQS_BIAS                (HISPI_DQS_BIAS),
+                .HISPI_IBUF_DELAY_VALUE        (HISPI_IBUF_DELAY_VALUE),
+                .HISPI_IBUF_LOW_PWR            (HISPI_IBUF_LOW_PWR),
+                .HISPI_IFD_DELAY_VALUE         (HISPI_IFD_DELAY_VALUE),
+                .HISPI_IOSTANDARD              (HISPI_IOSTANDARD)
+`endif    
+                
 `ifdef DEBUG_RING
                 ,.DEBUG_CMD_LATENCY   (DEBUG_CMD_LATENCY) 
 `endif        
             ) sensor_channel_i (
-//                .rst          (rst),                 // input
                 .pclk         (pclk),                  // input
                 .pclk2x       (pclk2x),                // input
                 .mrst         (mrst),                  // input

simulation_modules/par12_hispi_psp4l.v

@@ -26,7 +26,7 @@ module  par12_hispi_psp4l#(
     parameter LANE0_DLY =      1.3,
     parameter LANE1_DLY =      2.7,
     parameter LANE2_DLY =      0.2,
-    parameter LANE3_DLY =      3.3,
+    parameter LANE3_DLY =      1.8,
     parameter CLK_DLY =        2.3,
     parameter EMBED_LINES =    2,   // number of first lines containing embedded (non-image) data
     parameter MSB_FIRST =      0,
@@ -69,7 +69,9 @@ module  par12_hispi_psp4l#(
     
         vact_d <= vact;
         hact_d <= hact;
-        pxd_d <=  {pxd_d[35:0],pxd};
+//        pxd_d <=  {pxd_d[35:0],pxd};
+        pxd_d <=  {pxd, pxd_d[47:12]};
+        
         
         if     (!vact) lane_pcntr <= 0;
         else if (hact) lane_pcntr <= lane_pcntr + 1;

simulation_modules/simul_clk_mult_div.v

@@ -48,7 +48,7 @@ module  simul_clk_mult_div#(
             sim_clk_div #(
                 .DIVISOR   (DIVISOR)
             ) sim_clk_div_i (
-                .clk_in   (clk_in), // input
+                .clk_in   (clk_int), // input
                 .en       (en), // input
                 .clk_out  (clk_out) // output
             );

system_defines.vh

@@ -3,7 +3,7 @@
   `define SYSTEM_DEFINES
   `define PRELOAD_BRAMS
   // if HISPI is not defined, parallel sensor interface is used for all channels
-//  `define HISPI
+  `define HISPI
 //  `define DEBUG_RING 1
   `define MEMBRIDGE_DEBUG_WRITE 1
 // Enviroment-dependent options

wrap/iserdes_mem.v

@@ -23,7 +23,8 @@
 module  iserdes_mem #
 (
     parameter DYN_CLKDIV_INV_EN="FALSE",
-    parameter IOBDELAY = "IFD"  // "NONE", "IBUF", "IFD", "BOTH"
+    parameter IOBDELAY = "IFD",  // "NONE", "IBUF", "IFD", "BOTH"
+    parameter MSB_FIRST = 0      // 0 - lowest bit is received first, 1 - highest is received first
 ) (
     input        iclk,     // source-synchronous clock
     input        oclk,     // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
@@ -35,7 +36,8 @@ module  iserdes_mem #
     output [3:0] dout,
     output       comb_out  // combinatorial output copies selected input to be used in the fabric     
 );
-
+    wire   [3:0] dout_le;
+    assign dout = MSB_FIRST ? {dout_le[0], dout_le[1], dout_le[2], dout_le[3]} : dout_le;
 `ifndef OPEN_SOURCE_ONLY  // Not using simulator - instanciate actual ISERDESE2 (can not be simulated because of encrypted )           
      ISERDESE2 #(
          .DATA_RATE                  ("DDR"),
@@ -60,10 +62,10 @@ module  iserdes_mem #
          iserdes_i
          (
          .O                          (comb_out),
-         .Q1                         (dout[3]),
-         .Q2                         (dout[2]),
-         .Q3                         (dout[1]),
-         .Q4                         (dout[0]),
+         .Q1                         (dout_le[3]),
+         .Q2                         (dout_le[2]),
+         .Q3                         (dout_le[1]),
+         .Q4                         (dout_le[0]),
          .Q5                         (),
          .Q6                         (),
          .Q7                         (),
@@ -111,10 +113,10 @@ module  iserdes_mem #
          iserdes_i
          (
          .O                          (comb_out),
-         .Q1                         (dout[3]),
-         .Q2                         (dout[2]),
-         .Q3                         (dout[1]),
-         .Q4                         (dout[0]),
+         .Q1                         (dout_le[3]),
+         .Q2                         (dout_le[2]),
+         .Q3                         (dout_le[1]),
+         .Q4                         (dout_le[0]),
          .Q5                         (),
          .Q6                         (),
          .SHIFTOUT1                  (),

x393.v

@@ -1487,11 +1487,20 @@ assign axi_grst = axi_rst_pre;
         .SENS_CTRL_ARST             (SENS_CTRL_ARST),
         .SENS_CTRL_ARO              (SENS_CTRL_ARO),
         .SENS_CTRL_RST_MMCM         (SENS_CTRL_RST_MMCM),
+`ifdef HISPI                
+        .SENS_CTRL_IGNORE_EMBED     (SENS_CTRL_IGNORE_EMBED),
+`else                
         .SENS_CTRL_EXT_CLK          (SENS_CTRL_EXT_CLK),
+`endif                
         .SENS_CTRL_LD_DLY           (SENS_CTRL_LD_DLY),
+`ifdef HISPI
+        .SENS_CTRL_GP0              (SENS_CTRL_GP0),
+        .SENS_CTRL_GP1              (SENS_CTRL_GP1),
+`else        
         .SENS_CTRL_QUADRANTS        (SENS_CTRL_QUADRANTS),
         .SENS_CTRL_QUADRANTS_WIDTH  (SENS_CTRL_QUADRANTS_WIDTH),
         .SENS_CTRL_QUADRANTS_EN     (SENS_CTRL_QUADRANTS_EN),
+`endif                
         .SENSIO_STATUS              (SENSIO_STATUS),
         .SENSIO_JTAG                (SENSIO_JTAG),
         .SENS_JTAG_PGMEN            (SENS_JTAG_PGMEN),
@@ -1499,7 +1508,9 @@ assign axi_grst = axi_rst_pre;
         .SENS_JTAG_TCK              (SENS_JTAG_TCK),
         .SENS_JTAG_TMS              (SENS_JTAG_TMS),
         .SENS_JTAG_TDI              (SENS_JTAG_TDI),
+`ifndef HISPI
         .SENSIO_WIDTH               (SENSIO_WIDTH),
+`endif        
         .SENSIO_DELAYS              (SENSIO_DELAYS),
         .SENSI2C_ABS_RADDR          (SENSI2C_ABS_RADDR),
         .SENSI2C_REL_RADDR          (SENSI2C_REL_RADDR),
@@ -1515,9 +1526,11 @@ assign axi_grst = axi_rst_pre;
         .SENSI2C_IBUF_LOW_PWR       (SENSI2C_IBUF_LOW_PWR),
         .SENSI2C_IOSTANDARD         (SENSI2C_IOSTANDARD),
         .SENSI2C_SLEW               (SENSI2C_SLEW),
+`ifndef HISPI
         .SENSOR_DATA_WIDTH          (SENSOR_DATA_WIDTH),
         .SENSOR_FIFO_2DEPTH         (SENSOR_FIFO_2DEPTH),
         .SENSOR_FIFO_DELAY         (SENSOR_FIFO_DELAY),
+`endif                
         .HIST_SAXI_ADDR_MASK        (HIST_SAXI_ADDR_MASK),
         .HIST_SAXI_MODE_WIDTH       (HIST_SAXI_MODE_WIDTH),
         .HIST_SAXI_EN               (HIST_SAXI_EN),
@@ -1538,9 +1551,15 @@ assign axi_grst = axi_rst_pre;
         .PXD_SLEW                   (PXD_SLEW),
         .SENS_REFCLK_FREQUENCY      (SENS_REFCLK_FREQUENCY),
         .SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
+`ifdef HISPI
+        .PXD_CAPACITANCE            (PXD_CAPACITANCE),
+        .PXD_CLK_DIV                (PXD_CLK_DIV),
+        .PXD_CLK_DIV_BITS           (PXD_CLK_DIV_BITS),
+`endif
         .SENS_PHASE_WIDTH           (SENS_PHASE_WIDTH),
         .SENS_PCLK_PERIOD           (SENS_PCLK_PERIOD),
         .SENS_BANDWIDTH             (SENS_BANDWIDTH),
+        .CLKIN_PERIOD_SENSOR        (CLKIN_PERIOD_SENSOR),
         .CLKFBOUT_MULT_SENSOR       (CLKFBOUT_MULT_SENSOR),
         .CLKFBOUT_PHASE_SENSOR      (CLKFBOUT_PHASE_SENSOR),
         .IPCLK_PHASE                (IPCLK_PHASE),
@@ -1559,6 +1578,17 @@ assign axi_grst = axi_rst_pre;
         .SENS_SS_EN                 (SENS_SS_EN),
         .SENS_SS_MODE               (SENS_SS_MODE),
         .SENS_SS_MOD_PERIOD         (SENS_SS_MOD_PERIOD)
+`ifdef HISPI
+       ,.HISPI_MSB_FIRST               (HISPI_MSB_FIRST),
+        .HISPI_NUMLANES                (HISPI_NUMLANES),
+        .HISPI_CAPACITANCE             (HISPI_CAPACITANCE),
+        .HISPI_DIFF_TERM               (HISPI_DIFF_TERM),
+        .HISPI_DQS_BIAS                (HISPI_DQS_BIAS),
+        .HISPI_IBUF_DELAY_VALUE        (HISPI_IBUF_DELAY_VALUE),
+        .HISPI_IBUF_LOW_PWR            (HISPI_IBUF_LOW_PWR),
+        .HISPI_IFD_DELAY_VALUE         (HISPI_IFD_DELAY_VALUE),
+        .HISPI_IOSTANDARD              (HISPI_IOSTANDARD)
+`endif    
 `ifdef DEBUG_RING
         ,.DEBUG_CMD_LATENCY         (DEBUG_CMD_LATENCY) 
 `endif        

x393_testbench02.tf

@@ -250,7 +250,7 @@ parameter EXTERNAL_TIMESTAMP =    0; // 1 ;    // embed local timestamp, 1 - emb
     localparam HISPI_CLK_MULT =      10; // from pixel clock to serial output pixel rate TODO: Set real ones, adjsut sensor clock too
 
     localparam HISPI_EMBED_LINES =    2; // first lines will be marked as "embedded" (non-image data)
-    localparam HISPI_MSB_FIRST =      2; // 0 - serialize LSB first, 1 - MSB first
+//    localparam HISPI_MSB_FIRST =      0; // 0 - serialize LSB first, 1 - MSB first
     localparam HISPI_FIFO_LOGDEPTH = 12; // 49-bit wide FIFO address bits (>log (line_length + 2)
 `endif    
     
@@ -2096,7 +2096,7 @@ simul_axi_hp_wr #(
         .LANE0_DLY     (1.3),
         .LANE1_DLY     (2.7),
         .LANE2_DLY     (0.2),
-        .LANE3_DLY     (3.3),
+        .LANE3_DLY     (1.8),
         .CLK_DLY       (2.3),
         .EMBED_LINES   (HISPI_EMBED_LINES),
         .MSB_FIRST     (HISPI_MSB_FIRST),
@@ -2119,7 +2119,7 @@ simul_axi_hp_wr #(
         .LANE0_DLY     (1.3),
         .LANE1_DLY     (2.7),
         .LANE2_DLY     (0.2),
-        .LANE3_DLY     (3.3),
+        .LANE3_DLY     (1.8),
         .CLK_DLY       (2.3),
         .EMBED_LINES   (HISPI_EMBED_LINES),
         .MSB_FIRST     (HISPI_MSB_FIRST),
@@ -2142,7 +2142,7 @@ simul_axi_hp_wr #(
         .LANE0_DLY     (1.3),
         .LANE1_DLY     (2.7),
         .LANE2_DLY     (0.2),
-        .LANE3_DLY     (3.3),
+        .LANE3_DLY     (1.8),
         .CLK_DLY       (2.3),
         .EMBED_LINES   (HISPI_EMBED_LINES),
         .MSB_FIRST     (HISPI_MSB_FIRST),
@@ -2165,7 +2165,7 @@ simul_axi_hp_wr #(
         .LANE0_DLY     (1.3),
         .LANE1_DLY     (2.7),
         .LANE2_DLY     (0.2),
-        .LANE3_DLY     (3.3),
+        .LANE3_DLY     (1.8),
         .CLK_DLY       (2.3),
         .EMBED_LINES   (HISPI_EMBED_LINES),
         .MSB_FIRST     (HISPI_MSB_FIRST),

x393_testbench03.sav

+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Sun Oct 18 07:16:52 2015
+[*]
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151018002800912.fst"
+[dumpfile_mtime] "Sun Oct 18 06:48:31 2015"
+[dumpfile_size] 96834585
+[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
+[timestart] 69485000
+[size] 1823 1180
+[pos] 1917 0
+*-14.719048 69557100 68900514 68903540 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] x393_testbench03.
+[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
+[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
+[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.
+[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[1].
+[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[2].
+[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[3].
+[treeopen] x393_testbench03.simul_sensor12bits_2_i.
+[treeopen] x393_testbench03.x393_i.
+[treeopen] x393_testbench03.x393_i.sensors393_i.
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.
+[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].
+[sst_width] 202
+[signals_width] 258
+[sst_expanded] 1
+[sst_vpaned_height] 670
+@800200
+-x393_top
+@28
+x393_testbench03.x393_i.mclk
+x393_testbench03.x393_i.pclk
+@200
+-
+@1000200
+-x393_top
+@800200
+-sens_10398
+@28
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pclk
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_ext_clk_p
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.rst_mmcm
+@800200
+-sens_hispi12l4
+@28
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk2x
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.irst
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.prst
+@22
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.irst_r[4:0]
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eof[3:0]
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eol[3:0]
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sof[3:0]
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sol[3:0]
+@28
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hact_out
+@c00022
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
+@28
+(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
+(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
+(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
+(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
+@1401200
+-group_end
+@22
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dn[3:0]
+@c00022
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+@28
+(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(9)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(10)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(11)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(12)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(13)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(14)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+(15)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
+@1401200
+-group_end
+@28
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_clkp
+@22
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_aligned[47:0]
+@200
+-lanes
+@c00022
+[color] 3
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
+@28
+(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
+(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
+(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
+(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
+@1401200
+-group_end
+@22
+[color] 2
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.shift_val[1:0]
+[color] 3
+x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dout[11:0]
+[color] 3
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+@c00022
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+(13)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
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+(21)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(22)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(23)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(24)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
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+(26)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(27)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(28)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(29)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
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+(31)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
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+(34)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(35)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(36)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(37)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(38)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+(39)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
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+(42)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
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+(47)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
+@1401200
+-group_end
+@22
+x393_testbench03.par12_hispi_psp4l0_i.rdy[3:0]
+@28
+x393_testbench03.par12_hispi_psp4l0_i.rst
+@22
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+@28
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+x393_testbench03.par12_hispi_psp4l0_i.vact
+x393_testbench03.par12_hispi_psp4l0_i.vact_d
+@1401200
+-par_hspi_0
+[pattern_trace] 1
+[pattern_trace] 0