Commit 71cc5ef4 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Built with parallel sensors, compatible with serial (single parameter switch)

parent 3f49ecae

.project

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@@ -62,52 +62,52 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160329103342970.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160329103342970.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160329103342970.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160329103342970.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160329103342970.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160329103342970.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160329102811515.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160329103342970.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160329102811515.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160329102811515.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160330184559950.log</location>

		</link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>
@@ -127,7 +127,7 @@ 
		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20160329102811515.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20160330184559950.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

fpga_version.vh

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@@ -32,7 +32,9 @@ 
 * with at least one of the Free Software programs.

 *******************************************************************************/

 

      parameter FPGA_VERSION =          32'h0393007f;    // More constraints files tweaking

      parameter FPGA_VERSION =          32'h03930081;    // re-started parallel

//      parameter FPGA_VERSION =          32'h03930080;    // serial, failed timing, >84%

//      parameter FPGA_VERSION =          32'h0393007f;    // More constraints files tweaking

//      parameter FPGA_VERSION =          32'h0393007e;    // Trying .tcl constraints instead of xdc - timing met

//      parameter FPGA_VERSION =          32'h0393007d;    // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers. Timing met

//      parameter FPGA_VERSION =          32'h0393007c;    // fixed cmdseqmux - reporting interrupt status and mask correctly

sensor/sensor_channel.v

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@@ -467,7 +467,10 @@ module sensor_channel#( 
    

    

`ifdef DEBUG_RING

//    reg vact_to_fifo_r;

    `ifdef HISPI

    `else

        reg vact_to_fifo_r;    

    `endif

    reg hact_to_fifo_r;

    reg [15:0] debug_line_cntr;

    reg [15:0] debug_lines;

system_defines.vh

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@@ -48,7 +48,7 @@ 
  `define PRELOAD_BRAMS

  `define DISPLAY_COMPRESSED_DATA  

  // if HISPI is not defined, parallel sensor interface is used for all channels

  `define HISPI

 // `define HISPI

//    `define USE_OLD_XDCT393  

//  `define USE_PCLK2X

//  `define USE_XCLK2X

x393.bit

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