Commit 6ff31a13 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

porting delay scan/adjustment functions from the eddr3 Python code

parent 652c47ec

.project

+2 −2
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@@ -97,7 +97,7 @@ 
		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150311172942225.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150313235008423.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
@@ -107,7 +107,7 @@ 
		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150311172942225.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150314001725869.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

includes/x393_localparams.vh

+8 −4
Original line number Diff line number Diff line
@@ -74,6 +74,8 @@ DLY_PHASE= 0x2c # 0x1c # mmcm fine phase shift, 1/4 tCK 


*/  

`ifdef TARGET_MODE

    localparam T_RFC=50;  // t_rfc=50 for tCK=2.5ns

    localparam T_REFI=48; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)

  `ifdef use200Mhz

    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
@@ -113,19 +115,21 @@ DLY_PHASE= 0x2c # 0x1c # mmcm fine phase shift, 1/4 tCK 
  `endif   

    localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK

`else

    localparam T_RFC=50;  // t_rfc=50 for tCK=2.5ns

    localparam T_REFI=16; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)

  `ifdef use200Mhz

    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

    localparam DLY_LANE0_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]

    localparam DLY_LANE0_ODELAY= 80'h4c784b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]

    localparam DLY_LANE0_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0

    localparam DLY_LANE1_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]

    localparam DLY_LANE1_ODELAY= 80'h4c784b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]

    localparam DLY_LANE1_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0

    localparam DLY_CMDA=  256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0

// alternative to set same type delays to the same value    

    localparam DLY_DQ_IDELAY =  'h20 ;// 'h60;

    localparam DLY_DQ_ODELAY =  'ha0; // 'h48;

    localparam DLY_DQS_IDELAY = 'h40; // 'ha0;

    localparam DLY_DQS_ODELAY = 'h4c; // 

    localparam DLY_DQS_ODELAY = 'h78; // 

    localparam DLY_DM_ODELAY =  'ha0; // 'h48;

    localparam DLY_CMDA_ODELAY ='h50; // 'h30;

  `else

includes/x393_tasks_mcntrl_timing.vh

+6 −0
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@@ -41,6 +41,10 @@ 


    task axi_set_dqs_odelay_nominal; //SuppressThisWarning VEditor : may be unused

     begin

        $display("axi_set_dqs_odelay_nominal(0x%x,0x%x) @ %t",

        (DLY_LANE0_ODELAY >> (8<<3)) & 32'hff,

        (DLY_LANE1_ODELAY >> (8<<3)) & 32'hff,

        $time);

//        axi_set_dqs_idelay(

        write_contol_register(LD_DLY_LANE0_ODELAY + 8,      (DLY_LANE0_ODELAY >> (8<<3)) & 32'hff);

        write_contol_register(LD_DLY_LANE1_ODELAY + 8,      (DLY_LANE1_ODELAY >> (8<<3)) & 32'hff);
@@ -68,6 +72,8 @@ 
    task axi_set_delays; // set all individual delays

     integer i;

     begin

         $display("axi_set_delays @ %t",$time);

     

        for (i=0;i<10;i=i+1) begin

            write_contol_register(LD_DLY_LANE0_ODELAY + i,     (DLY_LANE0_ODELAY >> (i<<3)) & 32'hff);

        end

includes/x393_tasks_pio_sequences.vh

+1 −1
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@@ -210,7 +210,7 @@ task set_read_pattern; 
        end

// nop - all 3 below are the same? - just repeat?

        //                          skip     done        bank         ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD      B_RST

        data <=  func_encode_skip(   0,       0,          0,           0,  0,  1,  0,    0,    0,    1,  1,   0,        0);

        data <=  func_encode_skip(   0,       0,          0,           0,  0,  1,  0,    0,    0,    1,  0,   0,        0); // was BUF WR

        @(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;

// nop

        //                          skip     done        bank         ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD      B_RST

memctrl/phy/phy_cmd.v

+1 −1
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@@ -70,7 +70,7 @@ module phy_cmd#( 
// clocks, reset

    input                        clk_in,

    input                        rst_in,

    output                       mclk,     // global clock, half DDR3 clock, synchronizes all I/O thorough the command port

    output                       mclk,     // global clock, half DDR3 clock, synchronizes all I/O through the command port

// inteface to control I/O delays and mmcm

    input                  [7:0] dly_data, // delay value (3 LSB - fine delay)

    input                  [6:0] dly_addr, // select which delay to program