Added IODELAY_GROUP synthesis attribute (6ad657e2) · Commits · Elphel / x393

phy/wrap/idelay_ctrl.v

+5 −1

Original line number	Original line	Diff line number	Diff line
	@@ -20,12 +20,16 @@
	*******************************************************************************/		*******************************************************************************/
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module idelay_ctrl(		module idelay_ctrl
			//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
			# ( parameter IODELAY_GRP = "IODELAY_MEMORY"
			) (
	input refclk,		input refclk,
	input rst,		input rst,
	output rdy		output rdy
	);		);

			(* IODELAY_GROUP = IODELAY_GRP *)
	IDELAYCTRL idelay_ctrl_i(		IDELAYCTRL idelay_ctrl_i(
	.RDY(rdy),		.RDY(rdy),
	.REFCLK(refclk),		.REFCLK(refclk),

phy/wrap/idelay_fine_pipe.v

+8 −5

Original line number	Original line	Diff line number	Diff line
	@@ -20,7 +20,13 @@
	*******************************************************************************/		*******************************************************************************/
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module idelay_fine_pipe(		module idelay_fine_pipe
			//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
			# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
			parameter integer DELAY_VALUE = 0,
			parameter real REFCLK_FREQUENCY = 200.0,
			parameter HIGH_PERFORMANCE_MODE = "FALSE"
			) (
	input clk,		input clk,
	input rst,		input rst,
	input set,		input set,
	@@ -29,9 +35,6 @@ module idelay_fine_pipe(
	input data_in,		input data_in,
	output data_out		output data_out
	);		);
	parameter integer DELAY_VALUE = 0;
	parameter real REFCLK_FREQUENCY = 200.0;
	parameter HIGH_PERFORMANCE_MODE = "FALSE";

	reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];		reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
	always @ (posedge clk or posedge rst) begin		always @ (posedge clk or posedge rst) begin
	@@ -40,7 +43,7 @@ module idelay_fine_pipe(
	if (rst) fdly <= DELAY_VALUE[2:0];		if (rst) fdly <= DELAY_VALUE[2:0];
	else if (set) fdly <= fdly_pre;		else if (set) fdly <= fdly_pre;
	end		end
	IDELAYE2_FINEDELAY		(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2_FINEDELAY
	#(		#(
	.CINVCTRL_SEL("FALSE"),		.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("IDATAIN"),		.DELAY_SRC("IDATAIN"),

phy/wrap/odelay_fine_pipe.v

+9 −7

Original line number	Original line	Diff line number	Diff line
	@@ -10,7 +10,7 @@
	* the Free Software Foundation, either version 3 of the License, or		* the Free Software Foundation, either version 3 of the License, or
	* (at your option) any later version.		* (at your option) any later version.
	*		*
	* idelay_fine_pipe.v is distributed in the hope that it will be useful,		* odelay_fine_pipe.v is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of		* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.		* GNU General Public License for more details.
	@@ -20,7 +20,13 @@
	*******************************************************************************/		*******************************************************************************/
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module odelay_fine_pipe(		module odelay_fine_pipe
			//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
			# ( parameter IODELAY_GRP = "IODELAY_MEMORY",
			parameter integer DELAY_VALUE = 0,
			parameter real REFCLK_FREQUENCY = 200.0,
			parameter HIGH_PERFORMANCE_MODE = "FALSE"
			) (
	input clk,		input clk,
	input rst,		input rst,
	input set,		input set,
	@@ -29,10 +35,6 @@ module odelay_fine_pipe(
	input data_in,		input data_in,
	output data_out		output data_out
	);		);
	parameter integer DELAY_VALUE = 0;
	parameter real REFCLK_FREQUENCY = 200.0;
	parameter HIGH_PERFORMANCE_MODE = "FALSE";

	reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];		reg [2:0] fdly_pre=DELAY_VALUE[2:0], fdly=DELAY_VALUE[2:0];
	always @ (posedge clk or posedge rst) begin		always @ (posedge clk or posedge rst) begin
	if (rst) fdly_pre <= DELAY_VALUE[2:0];		if (rst) fdly_pre <= DELAY_VALUE[2:0];
	@@ -41,7 +43,7 @@ module odelay_fine_pipe(
	else if (set) fdly <= fdly_pre;		else if (set) fdly <= fdly_pre;
	end		end

	ODELAYE2_FINEDELAY		(* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2_FINEDELAY
	#(		#(
	.CINVCTRL_SEL("FALSE"),		.CINVCTRL_SEL("FALSE"),
	.DELAY_SRC("ODATAIN"),		.DELAY_SRC("ODATAIN"),

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