added variable-length shift register for longer than 16 cysles delay

/*!

 * <b>Module:</b>dly01_var

 * @file dly01_var.v

 * @date 2014-05-30  

 * @author Andrey Filippov

 *

 * @brief Synchronous delay by 1-2^N clock cycles with reset (will map to primitive)

 *

 * @copyright Copyright (c) 2016 Elphel, Inc.

 *

 * <b>License:</b>

 *

 * dly01_var.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 *  dly01_var.v is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *

 * Additional permission under GNU GPL version 3 section 7:

 * If you modify this Program, or any covered work, by linking or combining it

 * with independent modules provided by the FPGA vendor only (this permission

 * does not extend to any 3-rd party modules, "soft cores" or macros) under

 * different license terms solely for the purpose of generating binary "bitstream"

 * files and/or simulating the code, the copyright holders of this Program give

 * you the right to distribute the covered work without those independent modules

 * as long as the source code for them is available from the FPGA vendor free of

 * charge, and there is no dependence on any encrypted modules for simulating of

 * the combined code. This permission applies to you if the distributed code

 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

`timescale 1ns/1ps

module  dly01_var#(

    parameter WIDTH = 4 

)(

    input             clk,

    input             rst,

    input [WIDTH-1:0] dly,

    input             din,

    output            dout

);

    localparam LENGTH = (1 << WIDTH); 

    reg [LENGTH -1:0] sr=0;

`ifdef SHREG_SEQUENTIAL_RESET

    always @ (posedge clk) begin

        sr <= {sr[LENGTH-2:0], din & ~rst}; 

    end

`else 

//    always @ (posedge rst or posedge clk) begin

    always @ (posedge clk) begin

       if (rst) sr <=0;

       else     sr <= {sr[LENGTH-2:0],din}; 

    end

`endif

`ifdef SIMULATION

    assign dout = (|sr) ? ((&sr) ? 1'b1 : sr[dly]) :  1'b0 ;

`else

    assign dout =sr[dly];

`endif        

endmodule

/*!

 * <b>Module:</b>dly_var

 * @file dly_var.v

 * @author Andrey Filippov

 *

 * @brief Synchronous delay by 1-16 clock cycles with reset (will map to primitives)

 *

 * @copyright Copyright (c) 2016 Elphel, Inc.

 *

 * <b>License:</b>

 *

 * dly_var.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 *  dly_var.v is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *

 * Additional permission under GNU GPL version 3 section 7:

 * If you modify this Program, or any covered work, by linking or combining it

 * with independent modules provided by the FPGA vendor only (this permission

 * does not extend to any 3-rd party modules, "soft cores" or macros) under

 * different license terms solely for the purpose of generating binary "bitstream"

 * files and/or simulating the code, the copyright holders of this Program give

 * you the right to distribute the covered work without those independent modules

 * as long as the source code for them is available from the FPGA vendor free of

 * charge, and there is no dependence on any encrypted modules for simulating of

 * the combined code. This permission applies to you if the distributed code

 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

`timescale 1ns/1ps

module  dly_var #(

    parameter WIDTH =     1,

    parameter DLY_WIDTH = 4

)(

    input                 clk,

    input                 rst,

    input [DLY_WIDTH-1:0] dly,

    input     [WIDTH-1:0] din,

    output    [WIDTH-1:0] dout

);

  generate

    genvar i;

    for (i=0; i < WIDTH; i=i+1) begin: bit_block

        dly01_var #(

            .WIDTH (DLY_WIDTH)

         ) dly01_var_i ( 

            .clk(clk), // input

            .rst(rst), // input

            .dly(dly), // input[3:0] 

            .din(din[i]), // input

            .dout(dout[i]) // output reg 

        );

    end

  endgenerate

endmodule