Commit 5335d3b3 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

temporary long delay before/after power on to power up w/o subcamera 

synchronization
parent cc0accd7

py393/hargs-eyesis

+2 −0
Original line number Diff line number Diff line
@@ -5,7 +5,9 @@ 
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle

-c bitstream_set_path /usr/local/verilog/x393_parallel.bit

-c setupSensorsPower  "PAR12"  all  0  0.2

-c sleep_ms 5000

-c setEyesisPower 1

-c sleep_ms 5000

-c sleep_ms 20

-c measure_all "*DI"

-c setSensorClock 24.0 "2V5_LVDS"