creating Python program to pass Verilog parameters to Python FPGA tests

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`timescale 1ns/1ps

`include "system_defines.vh" 

`define use200Mhz 1

//`define use200Mhz 1

//`define DEBUG_FIFO 1 

module  memctrl16 #(

//command interface parameters

<?xml version="1.0" encoding="UTF-8"?>

<projectDescription>

	<name>py393</name>

	<comment></comment>

	<projects>

	</projects>

	<buildSpec>

		<buildCommand>

			<name>org.python.pydev.PyDevBuilder</name>

			<arguments>

			</arguments>

		</buildCommand>

	</buildSpec>

	<natures>

		<nature>org.python.pydev.pythonNature</nature>

	</natures>

</projectDescription>

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

<?eclipse-pydev version="1.0"?><pydev_project>

<pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property>

<pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property>

<pydev_pathproperty name="org.python.pydev.PROJECT_SOURCE_PATH">

<path>/${PROJECT_DIR_NAME}</path>

</pydev_pathproperty>

</pydev_project>

eclipse.preferences.version=1

encoding/import_verilog_parameters.py=utf-8

encoding/test1.py=utf-8