Started bug fixing after hardware testing (4a69ce71) · Commits · Elphel / x393

compressor_jp/cmprs_cmd_decode.v

+1 −1

Original line number	Diff line number	Diff line
		@@ -235,7 +235,7 @@ module cmprs_cmd_decode#(
		reg [23:0] color_sat_xclk; // color saturation values (only 10 LSB in each 12 are used
		reg [ 2:0] coring_xclk; // color saturation values (only 10 LSB in each 12 are used

		wire frame_start_xclk;
		// wire frame_start_xclk;
		assign cmprs_en_mclk = cmprs_en_mclk_r;

		always @ (posedge mclk) begin

compressor_jp/compressor393.v

+2 −0

Original line number	Diff line number	Diff line
		@@ -663,6 +663,8 @@ module compressor393 # (
		assign afi1_wstrb = 0;
		assign afi1_bready = 0;
		assign afi1_wrissuecap1en = 0;
		assign status_rq_mux[5] = 0;
		assign status_ad_mux[40 +: 8] = 8'b0;
		end
		endgenerate

status_read.v

+6 −2

Original line number	Diff line number	Diff line
		@@ -32,7 +32,8 @@ module status_read#(
		parameter STATUS_ADDR = 'h0800, // AXI read address of status read registers
		parameter STATUS_ADDR_MASK = 'h3c00, // AXI write address of status registers
		parameter AXI_RD_ADDR_BITS = 14,
		parameter integer STATUS_DEPTH= 8 // 256 cells, maybe just 16..64 are enough?
		parameter integer STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough?
		parameter FPGA_VERSION = 32'h03930001
		)(
		input mrst, // @posedge mclk - sync reset
		input arst, // @posedge axi_clk - sync reset
		@@ -79,6 +80,9 @@ module status_read#(
		assign start=rq && !rq_r;
		assign axird_rdata=axi_status_rdata_r;
		assign axird_selected = select_r;
		initial begin
		ram [DATA_2DEPTH] = FPGA_VERSION;
		end
		always @ (posedge axi_clk) begin
		if (arst) select_r <= 0;
		else if (axird_start_burst) select_r <= select_w;

x393.v

+3 −1

Original line number	Diff line number	Diff line
		@@ -91,6 +91,7 @@ module x393 #(
		,output DUMMY_TO_KEEP

		);
		`include "fpga_version.vh"
		assign DUMMY_TO_KEEP = frst[2] && fclk[1];

		// localparam ADDRESS_NUMBER=15;
		@@ -823,7 +824,8 @@ assign axi_grst = axi_rst_pre;
		.STATUS_ADDR (STATUS_ADDR),
		.STATUS_ADDR_MASK (STATUS_ADDR_MASK),
		.AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),
		.STATUS_DEPTH (STATUS_DEPTH)
		.STATUS_DEPTH (STATUS_DEPTH),
		.FPGA_VERSION (FPGA_VERSION)
		) status_read_i (
		.mrst (mrst), // input
		.arst (arst), // input

x393.xdc

+9 −9

Original line number	Diff line number	Diff line
		@@ -423,12 +423,12 @@ set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}]
		# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
		# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

		set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
		set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
		set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
		set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]

		set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
		set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
		set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
		set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
		No newline at end of file
		#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
		#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
		#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
		#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]

		#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
		#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
		#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
		#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
		No newline at end of file

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