Continue debugging 256-cycle Bayer MCLT (46f1a6c9) · Commits · Elphel / x393

dsp/dtt_iv_8x8_ad.v

+3 −1

Original line number	Diff line number	Diff line
		@@ -76,6 +76,7 @@ module dtt_iv_8x8_ad#(
		output reg out_we, //!< output data valid (write to external buffer
		output reg sub16, //!< Subtract 16 from the full output address when true
		output reg inc16, //!< increment full output address by 16
		output reg start16, //!< reset/copy page address
		output reg start_out); //!< may start output readout, 1 entry per clock, vertically

		// 1. Two 16xINPUT_WIDTH memories to feed two of the 'horizontal' 1-dct - they should provide outputs shifted by 1 clock
		@@ -384,6 +385,7 @@ module dtt_iv_8x8_ad#(
		inc16 <= out_cntr[3:0] == 'he;
		out_we <= dctv_out_we[1];
		start_out <= start_out_w;
		start16 <= dctv_phin [6:0] == 'h11;
		end

		always @ (posedge clk) begin

dsp/mclt16x16_bayer.v

+4 −4

Original line number	Diff line number	Diff line
		@@ -292,7 +292,8 @@ module mclt16x16_bayer#(

		always @(posedge clk) begin
		if (rst) dtt_out_ram_cntr <= 0;
		else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;
		else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1; // make it copy input page?

		dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;

		dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;
		@@ -368,8 +369,6 @@ module mclt16x16_bayer#(
		.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0]
		);



		dtt_iv_8x8_ad #(
		.INPUT_WIDTH (DTT_IN_WIDTH),
		.OUT_WIDTH (OUT_WIDTH),
		@@ -394,6 +393,7 @@ module mclt16x16_bayer#(
		.out_we (dtt_out_we), // output reg
		.sub16 (dtt_sub16), // output reg
		.inc16 (dtt_inc16), // output reg
		.start16 (), // output reg
		.start_out (dtt_start_fill) // output[24:0] signed
		);
		//[DTT_IN_WIDTH-1:0

dsp/mclt16x16_bayer3.v

+200 −66

Original line number	Diff line number	Diff line
		@@ -48,7 +48,7 @@ module mclt16x16_bayer3#(
		parameter OUT_WIDTH = 25, // bits in dtt output
		parameter DTT_IN_WIDTH = 25, // bits in DTT input
		parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)
		parameter OUT_RSHIFT = 2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
		parameter OUT_RSHIFT1 = 2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
		parameter OUT_RSHIFT2 = 0, // overall right shift for the second (vertical) pass
		parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
		parameter DSP_A_WIDTH = 25,
		@@ -58,6 +58,7 @@ module mclt16x16_bayer3#(
		input clk, //!< system clock, posedge
		input rst, //!< sync reset
		input start, //!< start convertion of the next 256 samples
		input page, //!< parameter page number (valid @ start)
		input [1:0] tile_size, //!< o: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
		input [1:0] color_wa, //!< color index to apply parameters to (0 - R, 1 - B, 2 - G)
		input inv_checker, //!< 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
		@@ -78,10 +79,18 @@ module mclt16x16_bayer3#(
		input [PIXEL_WIDTH-1:0] pix_d, //!< pixel data, latency = 2 from pixel address
		output pre_busy, //!< start should come each 256-th cycle (next after pre_last_in), and not after pre_busy)
		output pre_last_in, //!< may increment page
		output pre_first_out,//!< next will output first of DCT/DCT coefficients
		output pre_last_out, //!< next will be last output of DST/DST coefficients
		output [7:0] out_addr, //!< address to save coefficients, 2 MSBs - mode (CC,SC,CS,SS), others - down first
		output dv, //!< output data valid
		output pre_first_out_r,//!< next will output first of DCT/DCT coefficients
		output pre_first_out_b,//!< next will output first of DCT/DCT coefficients
		output pre_first_out_g,//!< next will output first of DCT/DCT coefficients
		output pre_last_out_r, //!< next will be last output of DST/DST coefficients
		output pre_last_out_b, //!< next will be last output of DST/DST coefficients
		output pre_last_out_g, //!< next will be last output of DST/DST coefficients
		output [8:0] out_addr_r, //!< address to save coefficients: page, 2 bits - mode (CC,SC,CS,SS), others - down first
		output [8:0] out_addr_b, //!< address to save coefficients: page, 2 bits - mode (CC,SC,CS,SS), others - down first
		output [8:0] out_addr_g, //!< address to save coefficients: page, 2 bits - mode (CC,SC,CS,SS), others - down first
		output dv_r, //!< output data valid
		output dv_b, //!< output data valid
		output dv_g, //!< output data valid
		output signed [OUT_WIDTH - 1 : 0] dout_r, //!<frequency domain data output for red color components
		output signed [OUT_WIDTH - 1 : 0] dout_b, //!<frequency domain data output for blue color components
		output signed [OUT_WIDTH - 1 : 0] dout_g //!<frequency domain data output for green color components
		@@ -90,8 +99,13 @@ module mclt16x16_bayer3#(
		// When defined, use 2 DSP multipleierts
		// `define DSP_ACCUM_FOLD 1

		localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
		localparam DTT_IN_DELAY = 63; // 69; // wa -ra min = 1
		// localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
		// May be tweaked so outputs will appear simultaneously
		localparam DTT_OUT_DELAY_R = 64; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
		localparam DTT_OUT_DELAY_B = 64; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
		localparam DTT_OUT_DELAY_G = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?

		reg [7:0] in_cntr; //
		reg run_r;

		@@ -124,7 +138,7 @@ module mclt16x16_bayer3#(
		reg valid_odd_ram[0:3]; //
		reg [SHIFT_WIDTH-1:0] x_shft_ram[0:3]; //
		reg [SHIFT_WIDTH-1:0] y_shft_ram[0:3]; //
		reg reg_rot_page; // odd/even register sets for long latency (rotator)
		// reg reg_rot_page; // odd/even register sets for long latency (rotator)
		reg [1:0] regs_wa;
		reg inv_checker_rot_ram[0:7]; //
		reg valid_odd_rot_ram[0:7]; //
		@@ -136,6 +150,12 @@ module mclt16x16_bayer3#(
		reg valid_odd_ram_reg; //
		reg [SHIFT_WIDTH-1:0] x_shft_ram_reg; //
		reg [SHIFT_WIDTH-1:0] y_shft_ram_reg; //
		reg [1:0] rot_ram_copy;
		reg [2:0] rot_ram_page;
		reg inv_checker_rot_ram_reg; //
		reg valid_odd_rot_ram_reg; //
		reg [SHIFT_WIDTH-1:0] x_shft_rot_ram_reg; //
		reg [SHIFT_WIDTH-1:0] y_shft_rot_ram_reg; //
		// todo: add registers to read into rotators


		@@ -155,8 +175,8 @@ module mclt16x16_bayer3#(
		y_shft_rf_ram_reg <= y_shft_rf_ram[in_cntr[1:0]];
		end

		if (rst) reg_rot_page <= 1;
		else if (start) reg_rot_page <= ~reg_rot_page;
		// if (rst) reg_rot_page <= 1;
		// else if (start) reg_rot_page <= ~reg_rot_page;

		if (copy_regs[1]) begin
		inv_checker_ram[regs_wa] <= inv_checker_rf_ram_reg;
		@@ -165,10 +185,10 @@ module mclt16x16_bayer3#(
		x_shft_ram[regs_wa] <= x_shft_rf_ram_reg;
		y_shft_ram[regs_wa] <= y_shft_rf_ram_reg;

		inv_checker_rot_ram[{reg_rot_page,regs_wa}] <= inv_checker_rf_ram_reg;
		valid_odd_rot_ram[{reg_rot_page,regs_wa}] <= valid_odd_rf_ram_reg;
		x_shft_rot_ram[{reg_rot_page,regs_wa}] <= x_shft_rf_ram_reg;
		y_shft_rot_ram[{reg_rot_page,regs_wa}] <= y_shft_rf_ram_reg;
		inv_checker_rot_ram[{page,regs_wa}] <= inv_checker_rf_ram_reg;
		valid_odd_rot_ram[{page,regs_wa}] <= valid_odd_rf_ram_reg;
		x_shft_rot_ram[{page,regs_wa}] <= x_shft_rf_ram_reg;
		y_shft_rot_ram[{page,regs_wa}] <= y_shft_rf_ram_reg;
		end

		start_block_r <= {start_block_r[0], ((in_cntr[5:0] == 1) && (in_cntr[7:6] != 3))?1'b1:1'b0};
		@@ -180,6 +200,15 @@ module mclt16x16_bayer3#(
		y_shft_ram_reg <= y_shft_ram[in_cntr[7:6]];
		end

		if (rot_ram_copy[1]) begin
		inv_checker_rot_ram_reg <= inv_checker_rot_ram[rot_ram_page];
		valid_odd_rot_ram_reg <= valid_odd_rot_ram[rot_ram_page];
		x_shft_rot_ram_reg <= x_shft_rot_ram[rot_ram_page];
		y_shft_rot_ram_reg <= y_shft_rot_ram[rot_ram_page];
		end

		//rot_ram_page rot_ram_copy

		end

		`ifdef DSP_ACCUM_FOLD
		@@ -204,7 +233,7 @@ module mclt16x16_bayer3#(


		// assign pre_last_out = pre_last_out_r;
		// assign pre_busy = pre_busy_r \|\| start \|\| (!pre_last_in_w && phases[0]);
		assign pre_busy = pre_busy_r \|\| start \|\| (!pre_last_in_w && phases[0]);
		assign pre_last_in = pre_last_in_w;

		mclt_bayer_fold_rgb #(
		@@ -307,14 +336,22 @@ module mclt16x16_bayer3#(
		wire dtt_out_we;
		wire dtt_sub16;
		wire dtt_inc16;
		wire dtt_start16;
		wire dtt_start_red = (dtt_start16 & dtt_r_cntr[7:6] == 1); // after
		wire dtt_start_blue = (dtt_start16 & dtt_r_cntr[7:6] == 2); // after
		wire dtt_start_green = (dtt_start16 & dtt_r_cntr[7:6] == 3); // after
		reg [4:0] dtt_out_ram_cntr;
		reg [4:0] dtt_out_ram_wah;
		reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to
		reg [1:0] dtt_out_ram_wpage2; // later by 1 DTT
		// reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to
		// reg dtt_out_ram_wpage; // one of 2 pages (256 samples long) being written to
		// reg [1:0] dtt_out_ram_wpage2; // later by 1 DTT
		// reg dtt_out_ram_wpage2; // later by 1 DTT
		wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
		reg dtt_start_first_fill;
		reg dtt_start_second_fill;
		reg [1:0] dtt_start_out; // start read out to sin/cos rotator
		// reg dtt_start_first_fill;
		reg dtt_start_red_fill;
		reg dtt_start_blue_fill;
		reg dtt_start_green_fill;
		// reg dtt_start_second_fill;

		wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};

		@@ -325,13 +362,11 @@ module mclt16x16_bayer3#(
		wire dtt_out_we_b = dtt_out_we & ~dtt_out_ram_wa[7] & dtt_out_ram_wa[6];
		wire dtt_out_we_g = dtt_out_we & dtt_out_ram_wa[7];

		reg [7:0] dtt_dly_cntr;
		reg [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator

		reg [8:0] dtt_rd_ra0;
		reg [8:0] dtt_rd_ra1;
		wire [1:0] dtt_rd_regen_r; // dtt output buffer mem read, register enable, data valid
		wire [1:0] dtt_rd_regen_g; // dtt output buffer mem read, register enable, data valid
		wire [1:0] dtt_rd_regen_b; // dtt output buffer mem read, register enable, data valid

		reg [3:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid
		wire [35:0] dtt_rd_data_r_w; // high bits are not used
		wire [35:0] dtt_rd_data_b_w; // high bits are not used
		wire [35:0] dtt_rd_data_g_w; // high bits are not used
		@@ -340,10 +375,27 @@ module mclt16x16_bayer3#(
		wire signed [OUT_WIDTH-1:0] dtt_rd_data_b = dtt_rd_data_b_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
		wire signed [OUT_WIDTH-1:0] dtt_rd_data_g = dtt_rd_data_g_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]

		wire dtt_first_quad_out = ~dtt_out_ram_cntr[2];
		// wire dtt_first_quad_out = ~dtt_out_ram_cntr[2];
		wire dtt_red_quad_out = dtt_out_ram_cntr[3:2] == 0;
		wire dtt_blue_quad_out = dtt_out_ram_cntr[3:2] == 1;
		wire dtt_green_quad_out = dtt_out_ram_cntr[3:2] == 2;
		// wire dtt_last_quad_out = dtt_out_ram_cntr[3:2] == 3;

		wire ram_wpage_r = dtt_out_ram_cntr[4]; // dtt_out_ram_wah[4];
		reg ram_wpage_b;
		reg ram_wpage_g;

		wire [6:0] dtt_rd_ra_r;
		wire [6:0] dtt_rd_ra_b;
		wire [7:0] dtt_rd_ra_g;


		always @ (posedge clk) begin
		rot_ram_copy <= {rot_ram_copy[0], dtt_start16};
		if (rot_ram_copy[0]) rot_ram_page <= dtt_out_ram_cntr[4:2];

		//rot_ram_page

		// reading memory and running DTT
		start_dtt <= dtt_in_precntr == DTT_IN_DELAY;
		// if (start_dtt) dtt_r_page <= dtt_in_wa[7];// dtt_in_page;
		@@ -362,7 +414,7 @@ module mclt16x16_bayer3#(
		dtt_iv_8x8_ad #(
		.INPUT_WIDTH (DTT_IN_WIDTH),
		.OUT_WIDTH (OUT_WIDTH),
		.OUT_RSHIFT1 (OUT_RSHIFT),
		.OUT_RSHIFT1 (OUT_RSHIFT1),
		.OUT_RSHIFT2 (OUT_RSHIFT2),
		.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
		.DSP_B_WIDTH (DSP_B_WIDTH),
		@@ -383,48 +435,32 @@ module mclt16x16_bayer3#(
		.out_we (dtt_out_we), // output reg
		.sub16 (dtt_sub16), // output reg
		.inc16 (dtt_inc16), // output reg
		.start16 (dtt_start16), // output reg
		.start_out (dtt_start_fill) // output[24:0] signed
		);


		always @(posedge clk) begin
		if (rst) dtt_out_ram_cntr <= 0;
		// if (rst) dtt_out_ram_cntr <= 0;
		if (dtt_start_red) dtt_out_ram_cntr <= {page,4'b0};
		else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;
		dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;

		dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;

		dtt_start_second_fill<= dtt_start_fill & ~dtt_first_quad_out;

		if (dtt_start_first_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3];

		if (dtt_start_second_fill) dtt_out_ram_wpage2 <= dtt_out_ram_wpage;

		if (rst) dtt_dly_cntr <= 0;
		else if (dtt_start_first_fill) dtt_dly_cntr <= DTT_OUT_DELAY;
		else if (\|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1;
		dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;

		dtt_start_out <= {dtt_start_out[0],(dtt_dly_cntr == 1) ? 1'b1 : 1'b0};
		// dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;
		dtt_start_red_fill <= dtt_start_fill & dtt_red_quad_out;
		dtt_start_blue_fill <= dtt_start_fill & dtt_blue_quad_out;
		dtt_start_green_fill <= dtt_start_fill & dtt_green_quad_out;

		if (rst) dtt_rd_regen_dv[0] <= 0;
		else if (dtt_start_out[0]) dtt_rd_regen_dv[0] <= 1;
		else if (&dtt_rd_cntr_pre[6:0]) dtt_rd_regen_dv[0] <= 0;
		// dtt_start_second_fill<= dtt_start_fill & ~dtt_first_quad_out;

		if (rst) dtt_rd_regen_dv[3:1] <= 0;
		else dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];
		// if (dtt_start_first_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3];
		/// if (dtt_start_red_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3];
		// if (dtt_start_red_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4];

		// if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number
		if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage2, 7'b0}; //copy page number
		else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
		if (dtt_start_blue) ram_wpage_b <= ram_wpage_r;
		if (dtt_start_green) ram_wpage_g <= ram_wpage_b;

		dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],
		dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
		dtt_rd_cntr_pre[0]? (~dtt_rd_cntr_pre[6:2]) : dtt_rd_cntr_pre[6:2],
		dtt_rd_cntr_pre[0]};
		dtt_rd_ra1 <= {dtt_rd_cntr_pre[8:7],
		dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
		dtt_rd_cntr_pre[0]? (~dtt_rd_cntr_pre[6:2]) : dtt_rd_cntr_pre[6:2],
		~dtt_rd_cntr_pre[0]};

		end

		@@ -438,9 +474,9 @@ module mclt16x16_bayer3#(
		.LOG2WIDTH_RD(5)
		) ram18p_var_w_var_r_dtt_out_r_i (
		.rclk (clk), // input
		.raddr (dtt_rd_ra0), // input[8:0]
		.ren (dtt_rd_regen_dv[1]), // input
		.regen (dtt_rd_regen_dv[2]), // input
		.raddr ({2'b0,dtt_rd_ra_r}), // input[8:0]
		.ren (dtt_rd_regen_r[0]), // input
		.regen (dtt_rd_regen_r[1]), // input
		.data_out (dtt_rd_data_r_w), // output[35:0]
		.wclk (clk), // input
		.waddr (dtt_out_ram_wa_rb), // input[8:0]
		@@ -455,9 +491,9 @@ module mclt16x16_bayer3#(
		.LOG2WIDTH_RD(5)
		) ram18p_var_w_var_r_dtt_out_b_i (
		.rclk (clk), // input
		.raddr (dtt_rd_ra1), // input[8:0]
		.ren (dtt_rd_regen_dv[1]), // input
		.regen (dtt_rd_regen_dv[2]), // input
		.raddr ({2'b0,dtt_rd_ra_b}), // input[8:0]
		.ren (dtt_rd_regen_b[0]), // input
		.regen (dtt_rd_regen_b[1]), // input
		.data_out (dtt_rd_data_b_w), // output[35:0]
		.wclk (clk), // input
		.waddr (dtt_out_ram_wa_rb), // input[8:0]
		@@ -472,9 +508,9 @@ module mclt16x16_bayer3#(
		.LOG2WIDTH_RD(5)
		) ram18p_var_w_var_r_dtt_out_g_i (
		.rclk (clk), // input
		.raddr (dtt_rd_ra1), // input[8:0]
		.ren (dtt_rd_regen_dv[1]), // input
		.regen (dtt_rd_regen_dv[2]), // input
		.raddr ({1'b0,dtt_rd_ra_g}), // input[8:0]
		.ren (dtt_rd_regen_g[0]), // input
		.regen (dtt_rd_regen_g[1]), // input
		.data_out (dtt_rd_data_g_w), // output[35:0]
		.wclk (clk), // input
		.waddr (dtt_out_ram_wa_g), // input[8:0]
		@@ -484,7 +520,105 @@ module mclt16x16_bayer3#(
		);


		phase_rotator_rgb #(
		.FD_WIDTH (OUT_WIDTH),
		.SHIFT_WIDTH (SHIFT_WIDTH),
		.DSP_B_WIDTH (DSP_B_WIDTH),
		.DSP_A_WIDTH (DSP_A_WIDTH),
		.DSP_P_WIDTH (DSP_P_WIDTH),
		// .COEFF_WIDTH(COEFF_WIDTH),
		.GREEN (0),
		.START_DELAY (DTT_OUT_DELAY_R)
		) phase_rotator_r_i (
		.clk (clk), // input
		.rst (rst), // input
		.start (dtt_start_red_fill), // input
		.wpage (ram_wpage_r), // input
		.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
		.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
		.inv_checker (inv_checker_rot_ram_reg), // input
		.inv_rows (valid_odd_rot_ram_reg), // input
		.in_addr (dtt_rd_ra_r), // output[7:0]
		.in_re (dtt_rd_regen_r), // output[1:0]
		.fd_din (dtt_rd_data_r), // input[24:0] signed
		.fd_out (dout_r), // output[24:0] signed
		.pre_first_out (pre_first_out_r), // output
		.pre_last_out (pre_last_out_r), // output reg
		.fd_dv (dv_r), // output
		.fd_wa (out_addr_r) // output[8:0]

		);

		phase_rotator_rgb #(
		.FD_WIDTH (OUT_WIDTH),
		.SHIFT_WIDTH (SHIFT_WIDTH),
		.DSP_B_WIDTH (DSP_B_WIDTH),
		.DSP_A_WIDTH (DSP_A_WIDTH),
		.DSP_P_WIDTH (DSP_P_WIDTH),
		// .COEFF_WIDTH(COEFF_WIDTH),
		.GREEN (0),
		.START_DELAY (DTT_OUT_DELAY_B)
		) phase_rotator_b_i (
		.clk (clk), // input
		.rst (rst), // input
		.start (dtt_start_blue_fill), // input
		.wpage (ram_wpage_b), // input
		.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
		.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
		.inv_checker (inv_checker_rot_ram_reg), // input
		.inv_rows (valid_odd_rot_ram_reg), // input
		.in_addr (dtt_rd_ra_b), // output[7:0]
		.in_re (dtt_rd_regen_b), // output[1:0]
		.fd_din (dtt_rd_data_b), // input[24:0] signed
		.fd_out (dout_b), // output[24:0] signed
		.pre_first_out (pre_first_out_b), // output
		.pre_last_out (pre_last_out_b), // output reg
		.fd_dv (dv_b), // output
		.fd_wa (out_addr_b) // output[8:0]
		);

		phase_rotator_rgb #(
		.FD_WIDTH (OUT_WIDTH),
		.SHIFT_WIDTH (SHIFT_WIDTH),
		.DSP_B_WIDTH (DSP_B_WIDTH),
		.DSP_A_WIDTH (DSP_A_WIDTH),
		.DSP_P_WIDTH (DSP_P_WIDTH),
		// .COEFF_WIDTH(COEFF_WIDTH),
		.GREEN (1),
		.START_DELAY (DTT_OUT_DELAY_G)
		) phase_rotator_g_i (
		.clk (clk), // input
		.rst (rst), // input
		.start (dtt_start_green_fill), // input
		.wpage (ram_wpage_g), // input
		.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
		.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
		.inv_checker (inv_checker_rot_ram_reg), // input
		.inv_rows (valid_odd_rot_ram_reg), // input
		.in_addr (dtt_rd_ra_g), // output[7:0]
		.in_re (dtt_rd_regen_g), // output[1:0]
		.fd_din (dtt_rd_data_g), // input[24:0] signed
		.fd_out (dout_g), // output[24:0] signed
		.pre_first_out (pre_first_out_g), // output
		.pre_last_out (pre_last_out_g), // output reg
		.fd_dv (dv_g), // output
		.fd_wa (out_addr_g) // output[8:0]
		);


		reg [3:0] dead_cntr;
		reg pre_busy_r;


		always @ (posedge clk) begin

		if (rst) pre_busy_r <= 0;
		else if (pre_last_in_w) pre_busy_r <= 1;
		else if (dead_cntr == 0) pre_busy_r <= 0;

		if (~pre_busy_r) dead_cntr <= DEAD_CYCLES;
		else dead_cntr <= dead_cntr - 1;
		end

		endmodule

dsp/mclt_baeyer_fold_accum_rgb.v

+4 −2

Original line number	Diff line number	Diff line
		@@ -108,7 +108,8 @@ module mclt_baeyer_fold_accum_rgb # (
		reg [1:0] ced2;
		wire neg_m1, neg_m2, en_a2;
		wire accum1= !var_pre2_first;
		wire accum2= !var_pre_first && green_r[2];
		// wire accum2= !var_pre_first && green_r[2];
		wire accum2= !var_pre_first && green_r[3];
		wire [DSP_P_WIDTH-1:0] pout1;
		wire [DSP_P_WIDTH-1:0] pout2;
		wire signed [DTT_IN_WIDTH-1:0] dtt_in_dsp_w = (var_last ?
		@@ -205,7 +206,8 @@ module mclt_baeyer_fold_accum_rgb # (
		.rst (rst), // input
		.dly (4'h1), // input[3:0]
		// .din (pix_sgn[1]), // input[0:0]
		.din (green_r[0]? pix_sgn[1]:pix_sgn[0]), // input[0:0]
		// .din (green_r[0]? pix_sgn[1]:pix_sgn[0]), // input[0:0]
		.din (green_r[1]? pix_sgn[1]:pix_sgn[0]), // input[0:0]
		.dout (neg_m2) // output[0:0]
		);

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