fixing delay setup for par12 and hispi, ran for par12

 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

            parameter FPGA_VERSION =          32'h0393021f;         // (ext resistor) low_pwr, DIFF_SSTL18_I pclk phase 0.0 mmcm phase -22.5 (multiple of 1.5) 

   parameter FPGA_VERSION = 32'h03931001; // parallel, fixing delays  

// parameter FPGA_VERSION = 32'h03930220; // pull down ot serial in to detect sensor presense NOT created 

// parameter FPGA_VERSION = 32'h0393021f; // (ext resistor) low_pwr, DIFF_SSTL18_I pclk phase 0.0 mmcm phase -22.5 (multiple of 1.5) 

// parameter FPGA_VERSION = 32'h0393021e; // internal 100ohm,  low_pwr, LVDS_25 pclk phase 0.0 mmcm phase -22.5 (multiple of 1.5) 

// parameter FPGA_VERSION = 32'h0393021d; // (ext resistor) low_pwr, DIFF_SSTL18_I pclk phase 0.0 mmcm phase -22.5 (multiple of 1.5) 

// parameter FPGA_VERSION = 32'h0393021c; // untuned_60 DIFF_SSTL18_I pclk phase 0.0 mmcm phase -21.0 (multiple of 1.5) set TWEAKING_IOSTANDARD 1

// parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm 

// parameter FPGA_VERSION = 32'h03930138; // Fixing output trigger in free running mode 

// parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output 

//        parameter FPGA_VERSION =          32'h03930136;      // Fiixing spi_seq 

// parameter FPGA_VERSION = 32'h03930136; // Fixing spi_seq 

// parameter FPGA_VERSION = 32'h03930135; // Adding multi-cam reset 

// parameter FPGA_VERSION = 32'h0393014;  // Adding multi-cam reset - buggy 

// parameter FPGA_VERSION = 32'h03930133; // Works with linux kernel rocko commit of 05/01/2019 bd61276e05f7343415929112ae368230a9c472f0

    input [7:0] dly_data,

    input [3:0] din,

    input [3:0] tin,

    input       set_odelay,

    input       ld_odelay,

    input       set_odelay, // apply loaded pipeline register data

    input       ld_odelay,  // load  pipeline register data

    input       set_idelay,

    input       ld_idelay

);

    .IBUFDISABLE(1'b0),

    .I(dqs_data_dly), //dqs_data),

    .T(dqs_tri));

idelay_nofine # (

    .IODELAY_GRP(IODELAY_GRP),

    .DELAY_VALUE(IDELAY_VALUE>>3),

    input        rst,            // reset

    input        mclk,           // clock for setting delay values

    input  [7:0] dly_data,       // delay value (3 LSB - fine delay) - @posedge mclk

    input        set_idelay,     // mclk synchronous load idelay value

    input        ld_idelay       // mclk synchronous set idealy value

    input        set_idelay,     // mclk synchronous apply loaded delay values

    input        ld_idelay       // mclk synchronous load delay value to pipeline register

);

    wire pxclk_iobuf;

    ) pxclk_dly_i(

        .clk          (mclk),

        .rst          (rst),

        .set          (set_idelay),

        .ld           (ld_idelay),

        .set          (set_idelay), // apply loaded delay values

        .ld           (ld_idelay),  // load delay value to pipeline register

        .delay        (dly_data[7:3]),

        .data_in      (pxclk_iobuf),

        .data_out     (pxclk_in)

    input        irst,         // reset @ posedge iclk

    input        mclk,         // clock for setting delay values

    input  [7:0] dly_data,     // delay value (3 LSB - fine delay) - @posedge mclk

    input        set_idelay,   // mclk synchronous load idelay value

    input        ld_idelay,    // mclk synchronous set idealy value

    input        set_idelay,   // mclk synchronous apply loaded delay values

    input        ld_idelay,    // mclk synchronous load delay value to pipeline register

    input  [1:0] quadrant      // select one of 4 90-degree shifts for the data (MT9P0xx) have VACT, HACT shifted from PXD

);

    wire pxd_iobuf;

    ) pxd_dly_i(

        .clk          (mclk),

        .rst          (mrst),

        .set          (set_idelay),

        .ld           (ld_idelay),

        .set          (set_idelay), // apply loaded delay values

        .ld           (ld_idelay),  // load delay value to pipeline register

        .delay        (dly_data[7:3]),

        .data_in      (pxd_iobuf),

        .data_out     (pxd_delayed)

    reg         iarst = 0;

    reg         imrst = 0;  // active low 

    reg         rst_mmcm=1; // rst and command - en/dis 

    reg         ld_idelay=0;

    reg         apply_idelay=0;

    reg         ignore_embed=0; // do not process sensor data marked as "embedded"

//    wire [14:0] status;

        if      (mrst)                                               ignore_embed <= 0;

        else if (set_ctrl_r && data_r[SENS_CTRL_IGNORE_EMBED + 1])   ignore_embed <= data_r[SENS_CTRL_IGNORE_EMBED]; 

        if  (mrst) ld_idelay <= 0;

        else       ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY]; 

        if  (mrst) apply_idelay <= 0;

        else       apply_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY]; 

        if      (mrst)                                      gp_r[1:0] <= 0;

        else if (set_ctrl_r && data_r[SENS_CTRL_GP0 + 2])   gp_r[1:0] <= data_r[SENS_CTRL_GP0+:2]; 

        .set_lanes_map          (set_lanes_map),          // input 

        .set_fifo_dly           (set_fifo_dly),           // input

        .set_idelay             ({4{set_idelays}}),       // input[3:0] 

        .ld_idelay              (ld_idelay),              // input

        .apply_idelay           (apply_idelay),           // input

        .set_clk_phase          (set_iclk_phase),         // input

        .rst_mmcm               (rst_mmcm),               // input

        .ignore_embedded        (ignore_embed),           // input