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Commit 3ed89577 authored by Andrey Filippov's avatar Andrey Filippov
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Added progremmable interrupts from multi_saxi (used for IMU/GPS logger) and related export to C

parent 4a4984a7
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Showing with 215 additions and 178 deletions
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ 3ed89577
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
VivadoBitstream_@_rawfile=x393_parallel
VivadoBitstream_@_rawfile=x393_hispi
com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
VERSION
View file @ 3ed89577
......@@ -4,4 +4,4 @@
# a. 3
# b. 3.2 (preferred)
# c. 3.2.4
1.155
1.157
axi/mult_saxi_wr.v
View file @ 3ed89577
......@@ -43,7 +43,11 @@
module mult_saxi_wr #(
parameter MULT_SAXI_ADDR = 'h730, // ..'h737
parameter MULT_SAXI_CNTRL_ADDR = 'h738, // ..'h739
parameter MULT_SAXI_IRQLEN_ADDR = 'h738, // ..'h73b
parameter MULT_SAXI_CNTRL_ADDR = 'h73c, // ..'h73e
parameter MULT_SAXI_CNTRL_MODE = 'h0, // 'h73c offset for mode register
parameter MULT_SAXI_CNTRL_STATUS = 'h1, // 'h73d offset for status control register
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
......@@ -51,7 +55,8 @@ module mult_saxi_wr #(
parameter MULT_SAXI_BSLOG2 = 4,
parameter MULT_SAXI_BSLOG3 = 4,
parameter MULT_SAXI_MASK = 'h7f8, // 4 address/length pairs. In bytes, but lower bits are set to 0?
parameter MULT_SAXI_CNTRL_MASK = 'h7fe, // mode and status - 2 locations
parameter MULT_SAXI_IRQLEN_MASK = 'h7fc, // number of address bits to change for interrupt - 4 locations
parameter MULT_SAXI_CNTRL_MASK = 'h7fc, // mode, status, irq - 3 locations
parameter MULT_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
parameter MULT_SAXI_ADV_WR = 4, // number of clock cycles before end of write to genearte adv_wr_done
parameter MULT_SAXI_ADV_RD = 3 // number of clock cycles before end of write to genearte adv_wr_done
......@@ -92,6 +97,8 @@ module mult_saxi_wr #(
output read_burst3, // request to read a burst of data from channel 0
input [31:0] data_in_chn3, // data read from channel 0 (with some latency)
input pre_valid_chn3,// data valid (same latency)
output [3:0] irq, // per channel IRQ (generated after each 2^n DWORDS are transferred)
// S_AXI inerface w/o read channel
// write address
......@@ -169,7 +176,13 @@ module mult_saxi_wr #(
wire we_ctrl;
wire cmd_we_sa_len;
wire irq_log_we; // write number of address bits to change to generate interrupt
wire [3:0] irqs_src; // IRQ pulses to be used for IRQ generation
reg [3:0] irq_r = 0; // IRQ request (before mask)
reg [3:0] irq_m = 0; // IRQ enable
wire irq_we;
assign irq = irq_r & irq_m;
assign saxi_bready=1'b1;
assign {en_chn3, en_chn2, en_chn1, en_chn0} = en_chn_mclk;
......@@ -180,11 +193,35 @@ module mult_saxi_wr #(
assign en_chn_mclk = mode_reg[3:0];
assign run_chn_mclk = mode_reg[7:4];
assign irq_we = we_ctrl && (cmd_a[1:0] == MULT_SAXI_CNTRL_IRQ);
always @ (posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (we_ctrl && !cmd_a[0]) mode_reg <= cmd_data[7:0];
if (mrst) mode_reg <= 0;
else if (we_ctrl && (cmd_a[1:0] == MULT_SAXI_CNTRL_MODE)) mode_reg <= cmd_data[7:0];
/*
if (mrst) irq_r <= 0;
else irq_r <= irqs_src | (irq_r & (irq_we?{cmd_data[7:6] != 1,
cmd_data[5:4] != 1,
cmd_data[3:2] != 1,
cmd_data[1:0] != 1}:4'hf));
*/
end
generate
genvar i;
for (i=0; i<4; i=i+1) begin: irq_ctrl_block
always @ (posedge mclk) begin
if (mrst) irq_m[i] <= 0;
else if (irq_we && cmd_data[2*i+1]) irq_m[i] <= cmd_data[2*i];
if (mrst) irq_r[i] <= 0;
else if (irqs_src[i]) irq_r[i] <= 1;
else if (irq_we && (cmd_data[2*i +: 2] == 1)) irq_r[i] <= 0;
end
end
endgenerate
// Arbiter requests on copying from one of the input channels to the internal buffer
......@@ -394,6 +431,7 @@ module mult_saxi_wr #(
.sa_len_di (cmd_data[29:0]), // input[29:0]
.sa_len_wa (cmd_a[2:0]), // input[2:0]
.sa_len_we (cmd_we_sa_len), // input
.irq_log_we (irq_log_we), // input
.chn (re_cur_chn), // input[1:0]
.start (grant_rd_any), // input make sure 1 cycle
.busy (axi_ptr_busy), // output OR this busy with write data channel busy for en_out_arb
......@@ -401,7 +439,9 @@ module mult_saxi_wr #(
.axi_len (axi_len), // output[3:0] reg
.pntr_wd (pntr_wd), // output[29:0]
.pntr_wa (pntr_wa), // output[1:0]
.pntr_we (pntr_we) // output
.pntr_we (pntr_we), // output
.irqs (irqs_src) // output[3:0]
);
// interface axi_aw channel
......@@ -498,17 +538,17 @@ module mult_saxi_wr #(
.DATA_WIDTH (32),
.ADDR1 (MULT_SAXI_CNTRL_ADDR),
.ADDR_MASK1 (MULT_SAXI_CNTRL_MASK),
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_i2c_i (
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({cmd_we_sa_len,we_ctrl}) // output
.ADDR2 (MULT_SAXI_IRQLEN_ADDR),
.ADDR_MASK2 (MULT_SAXI_IRQLEN_MASK)
) cmd_deser_mult_saxi_wr_i (
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({cmd_we_sa_len,we_ctrl,irq_log_we}) // output
);
// now - converting all to parallel (TODO: use RAM for multi-word status data)
......@@ -542,7 +582,7 @@ module mult_saxi_wr #(
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (we_ctrl && cmd_a[0]), // input
.we (we_ctrl && (cmd_a[1:0] == MULT_SAXI_CNTRL_STATUS)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[128:0]
.ad (status_ad), // output[7:0]
......
axi/mult_saxi_wr_pointers.v
View file @ 3ed89577
......@@ -50,6 +50,7 @@ module mult_saxi_wr_pointers#(
input [29:0] sa_len_di, // input data to write pointers address/data
input [ 2:0] sa_len_wa, // channel address to write sa/lengths
input sa_len_we, // write enable sa/length data
input irq_log_we, // write log2 of number of written dwords to generate interrupt
input [ 1:0] chn, // selected channel number, valid with start
input start, // start address generation/pointer increment
output busy, // suspend new accesses (check latencies)
......@@ -60,7 +61,8 @@ module mult_saxi_wr_pointers#(
// alternatively - read out directly from ptr_ram?
output [29:0] pntr_wd, // @aclk
output [1:0] pntr_wa,
output pntr_we
output pntr_we,
output [3:0] irqs // @mclk, single-clock pulses to generate channel interrupts
);
reg [3:0] chn_en_mclk_r;
reg [3:0] chn_en_aclk;
......@@ -79,6 +81,10 @@ module mult_saxi_wr_pointers#(
reg [1:0] chn_r; // registered channel being processed (or reset)
reg [1:0] seq; // 1-hot sequence of address generation
wire [29:0] sa_len_ram_out;
reg [4:0] irq_log_r;
wire [29:0] irq_log_decoded_w;
reg gen_irq;
reg [3:0] irqs_aclk;
wire [29:0] ptr_ram_out;
wire [2:0] sa_len_ra;
reg ptr_we; // write to the pointer memory
......@@ -105,11 +111,13 @@ module mult_saxi_wr_pointers#(
// 8x30 RAM for address/length
reg [29:0] sa_len_ram[0:7]; // start chunk/num cunks in a buffer (write port @mclk)
// 4*5 RAM to store number of dword conters that need to chnage to generate interrupt
reg [4:0] irq_log_ram[0:3];
always @ (posedge mclk) begin
if (sa_len_we) sa_len_ram[sa_len_wa] <= sa_len_di;
if (sa_len_we) sa_len_ram[sa_len_wa] <= sa_len_di;
if (irq_log_we) irq_log_ram[sa_len_wa[1:0]] <= sa_len_di[4:0];
end
assign sa_len_ram_out = sa_len_ram[sa_len_ra];
// 4 x 30 RAM for current pointers
reg [29:0] ptr_ram[0:3]; // start chunk/num cunks in a buffer (write port @mclk)
always @ (posedge aclk) begin
......@@ -158,14 +166,28 @@ module mult_saxi_wr_pointers#(
ptr_we <= resetting[0] || seq[1];
if (seq[0]) irq_log_r <= irq_log_ram[chn_r];
gen_irq <= seq[1] && (|((ptr_inc ^ ptr_ram_out) & irq_log_decoded_w));
irqs_aclk <= gen_irq? {chn_r[1] & chn_r[0], chn_r[1] & ~chn_r[0], ~chn_r[1] & chn_r[0], ~chn_r[1] & ~chn_r[0]}:4'b0;
// add one extra register layer here?
end
generate
genvar i;
for (i = 0; i < 30; i = i+1) begin: decoder_block
assign irq_log_decoded_w[i] = i >= irq_log_r;
end
endgenerate
pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk0_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[0]), .out_pulse(rst_pntr_aclk[0]),.busy());
pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk1_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[1]), .out_pulse(rst_pntr_aclk[1]),.busy());
pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk2_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[2]), .out_pulse(rst_pntr_aclk[2]),.busy());
pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk3_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[3]), .out_pulse(rst_pntr_aclk[3]),.busy());
pulse_cross_clock irqs0_i (.rst(rst_aclk), .src_clk(aclk), .dst_clk(mclk), .in_pulse(irqs_aclk[0]), .out_pulse(irqs[0]),.busy());
pulse_cross_clock irqs1_i (.rst(rst_aclk), .src_clk(aclk), .dst_clk(mclk), .in_pulse(irqs_aclk[1]), .out_pulse(irqs[1]),.busy());
pulse_cross_clock irqs2_i (.rst(rst_aclk), .src_clk(aclk), .dst_clk(mclk), .in_pulse(irqs_aclk[2]), .out_pulse(irqs[2]),.busy());
pulse_cross_clock irqs3_i (.rst(rst_aclk), .src_clk(aclk), .dst_clk(mclk), .in_pulse(irqs_aclk[3]), .out_pulse(irqs[3]),.busy());
endmodule
fpga_version.vh
View file @ 3ed89577
......@@ -35,7 +35,9 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h0393009b; // parallel, bug fixed in dct_chen 79.58, timing met (2015.3)
parameter FPGA_VERSION = 32'h0393009d; // hispi, adding IRQ from multi_saxi 80.95%, timing not met (-0.034 )
// parameter FPGA_VERSION = 32'h0393009c; // parallel, adding IRQ from multi_saxi 79.31% , timing met (2015.3)
// parameter FPGA_VERSION = 32'h0393009b; // parallel, bug fixed in dct_chen 79.58, timing met (2015.3)
// parameter FPGA_VERSION = 32'h0393009a; // serial, bug fixed in dct_chen 80.94%, timing met (2015.3)
// parameter FPGA_VERSION = 32'h03930099; // parallel, with dct_chen, all met, 79.2%
// parameter FPGA_VERSION = 32'h03930098; // serial, trying dct_chen - works, removing old completely, constraints met80.?%
......
includes/x393_parameters.vh
View file @ 3ed89577
......@@ -829,7 +829,11 @@
parameter MULT_SAXI_WLOG = 4, // number of bits for the input data ( 3 - 8 bit, 4 - 16-bit, 5 - 32-bit
parameter MULT_SAXI_ADDR = 'h730, // ..'h737
parameter MULT_SAXI_CNTRL_ADDR = 'h738, // ..'h739
parameter MULT_SAXI_IRQLEN_ADDR = 'h738, // ..'h73b
parameter MULT_SAXI_CNTRL_ADDR = 'h73c, // ..'h73e
parameter MULT_SAXI_CNTRL_MODE = 'h0, // 'h73c offset for mode register
parameter MULT_SAXI_CNTRL_STATUS = 'h1, // 'h73d offset for status control register
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
......@@ -837,7 +841,8 @@
parameter MULT_SAXI_BSLOG2 = 4,
parameter MULT_SAXI_BSLOG3 = 4,
parameter MULT_SAXI_MASK = 'h7f8, // 4 address/length pairs. In bytes, but lower bits are set to 0?
parameter MULT_SAXI_CNTRL_MASK = 'h7fe, // mode and status - 2 locations
parameter MULT_SAXI_IRQLEN_MASK = 'h7fc, // number of address bits to change for interrupt - 4 locations
parameter MULT_SAXI_CNTRL_MASK = 'h7fc, // mode, status, irq - 3 locations
parameter MULT_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
parameter MULT_SAXI_ADV_WR = 4, // number of clock cycles before end of write to genearte adv_wr_done
parameter MULT_SAXI_ADV_RD = 3, // number of clock cycles before end of write to genearte adv_wr_done
......
py393/vrlg.py
View file @ 3ed89577
......@@ -180,7 +180,7 @@ NUM_CYCLES_20__TYPE = str
SENS_JTAG_PGMEN = int
NUM_CYCLES_03__TYPE = str
CMPRS_CBIT_RUN_BITS__TYPE = str
SENSOR12BITS_TDDO1 = int
LD_DLY_LANE1_IDELAY__TYPE = str
TILED_EXTRA_PAGES__RAW = str
CMPRS_NUM_AFI_CHN = int
CAMSYNC_TRIG_SRC__RAW = str
......@@ -222,22 +222,18 @@ MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
CLKFBOUT_MULT = int
RTC_STATUS_REG_ADDR__RAW = str
SENS_LENS_C_MASK__RAW = str
SIMULATE_CMPRS_CMODE0__RAW = str
NUM_CYCLES_11__TYPE = str
DEBUG_ADDR__TYPE = str
CMPRS_CBIT_QBANK_BITS__TYPE = str
SENS_GAMMA_MODE_TRIG = int
RTC_SET_USEC = int
RTC_BITC_PREDIV__TYPE = str
SIMULATE_CMPRS_CMODE0__TYPE = str
LD_DLY_CMDA = int
DLY_SET__RAW = str
SENSI2C_CMD_TABLE = int
MCNTRL_PS_ADDR__RAW = str
WOI_WIDTH__TYPE = str
NUM_FRAME_BITS__RAW = str
SENSI2C_CMD_ACIVE__RAW = str
HISTOGRAM_TOP__RAW = str
LOGGER_CONF_GPS__TYPE = str
HIST_SAXI_EN__RAW = str
SENSOR_16BIT_BIT__RAW = str
......@@ -261,7 +257,6 @@ NUM_CYCLES_30 = int
HISPI_DELAY_CLK0__TYPE = str
CMPRS_CBIT_QBANK__RAW = str
SENS_SYNC_MASK__TYPE = str
MEMCLK_PERIOD__TYPE = str
MCONTR_BUF0_RD_ADDR__RAW = str
HISPI_MMCM1 = str
SENS_PHASE_WIDTH = int
......@@ -273,6 +268,7 @@ CAMSYNC_PRE_MAGIC__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
DEBUG_LOAD = int
CMPRS_JP4DIFF__TYPE = str
MULT_SAXI_CNTRL_IRQ__TYPE = str
LOGGER_CONF_DBG__RAW = str
FRAME_START_ADDRESS_INC__TYPE = str
DLY_DQS_IDELAY__TYPE = str
......@@ -284,7 +280,6 @@ DLY_LANE1_DQS_WLV_IDELAY__RAW = str
SENS_LENS_RADDR = int
SENSI2C_CMD_TABLE__TYPE = str
PXD_IOSTANDARD = str
SENSOR12BITS_TMD__RAW = str
MAX_TILE_HEIGHT = int
BUF_CLK1X_PCLK = str
LOGGER_CONF_DBG_BITS = int
......@@ -308,7 +303,6 @@ MAX_TILE_WIDTH__TYPE = str
MULTICLK_DIV_DLYREF__TYPE = str
MULTICLK_MULT = int
SENS_LENS_POST_SCALE_MASK = int
MEMCLK_PERIOD = float
BUF_IPCLK2X_SENS1__RAW = str
SENSOR_MODE_WIDTH__RAW = str
SENS_LENS_FAT0_OUT_MASK = int
......@@ -330,19 +324,18 @@ RTC_STATUS_REG_ADDR = int
SENS_LENS_BY_MASK__TYPE = str
CMPRS_CBIT_CMODE__RAW = str
TILED_EXTRA_PAGES__TYPE = str
AXI_RDADDR_LATENCY = int
AFI_MUX_BUF_LATENCY = int
WINDOW_WIDTH = int
CLK_CNTRL__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS = int
MCONTR_LINTILE_RST_FRAME__TYPE = str
HISTOGRAM_TOP = int
FCLK1_PERIOD = float
LAST_BUF_FRAME__RAW = str
CMPRS_AFIMUX_RADDR1__RAW = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
CMPRS_CBIT_DCSUB_BITS__RAW = str
SENS_CTRL_LD_DLY__RAW = str
HIST_SAXI_MODE_ADDR_REL__TYPE = str
MULT_SAXI_CNTRL_STATUS__RAW = str
CMPRS_CBIT_CMODE_JP46__TYPE = str
NUM_CYCLES_17__RAW = str
DFLT_WBUF_DELAY__RAW = str
......@@ -356,9 +349,8 @@ LAST_FRAME_BITS__RAW = str
SENS_DIVCLK_DIVIDE = int
SENSI2C_CMD_SOFT_SDA__TYPE = str
SENS_LENS_COEFF__RAW = str
GPIO_MASK = int
CMPRS_CONTROL_REG = int
GPIO_STATUS_REG_ADDR = int
AXI_TASK_HOLD__RAW = str
MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
CMPRS_AFIMUX_RADDR0__TYPE = str
MCNTRL_TILED_WINDOW_WH__RAW = str
......@@ -418,7 +410,6 @@ NUM_CYCLES_21 = int
FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
FCLK0_PERIOD = float
CMDFRAMESEQ_REL__TYPE = str
MAX_TILE_WIDTH__RAW = str
PICKLE = str
......@@ -429,6 +420,7 @@ SENSI2C_SLEW = str
DFLT_WBUF_DELAY__TYPE = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
SENSI2C_STATUS_REG_INC__TYPE = str
MULT_SAXI_CNTRL_STATUS__TYPE = str
CMPRS_FRMT_MBRM1_BITS__RAW = str
SCANLINE_EXTRA_PAGES = int
LD_DLY_LANE1_ODELAY__RAW = str
......@@ -444,7 +436,6 @@ MCONTR_LINTILE_SKIP_LATE__TYPE = str
DEBUG_ADDR__RAW = str
CONTROL_ADDR__RAW = str
TILED_STARTY__RAW = str
RTC_BITC_PREDIV = int
CMPRS_FRMT_MBCM1_BITS__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str
HISPI_DELAY_CLK1__TYPE = str
......@@ -462,7 +453,7 @@ MULTICLK_DIV_SYNC__RAW = str
CMPRS_CORING_MODE = int
LOGGER_STATUS__TYPE = str
DFLT_REFRESH_PERIOD__TYPE = str
FFCLK1_IOSTANDARD = str
SENS_JTAG_TMS__TYPE = str
MCNTRL_TILED_MASK = int
MULTICLK_DIV_AXIHP = int
SENSIO_JTAG__RAW = str
......@@ -474,14 +465,14 @@ CAMSYNC_DELAY__RAW = str
LOGGER_CONF_DBG_BITS__RAW = str
FRAME_HEIGHT_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int
SENS_SYNC_LATE__RAW = str
SENSI2C_TBL_NBRD_BITS__RAW = str
DLY_CMDA_ODELAY = long
GPIO_PORTEN__RAW = str
SENS_LENS_C = int
MCONTR_ARBIT_ADDR_MASK = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_WINDOW_WH = int
WBUF_DLY_WLV__RAW = str
SIMULATE_CMPRS_CMODE3__RAW = str
TABLE_HUFFMAN_INDEX = int
MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TEST01_CHN2_MODE__RAW = str
......@@ -494,7 +485,6 @@ CAMSYNC_EN_BIT__TYPE = str
LD_DLY_LANE0_IDELAY = int
NUM_CYCLES_01__TYPE = str
NUM_CYCLES_24__TYPE = str
FCLK0_PERIOD__RAW = str
MCLK_PHASE__TYPE = str
SENSI2C_DRIVE__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str
......@@ -507,12 +497,11 @@ MCNTRL_TILED_FRAME_FULL_WIDTH = int
CMDFRAMESEQ_DEPTH = int
SENS_LENS_POST_SCALE__TYPE = str
RTC_MHZ__RAW = str
SENSOR_PRIORITY__RAW = str
FRAME_HEIGHT_BITS = int
HIST_SAXI_ADDR_MASK__TYPE = str
SENS_CTRL_LD_DLY = int
SENS_LENS_FAT0_IN_MASK__RAW = str
SENS_LENS_AY_MASK__RAW = str
SENSOR_IMAGE_TYPE1__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_LINTILE_DIS_NEED__TYPE = str
DFLT_DQS_PATTERN__RAW = str
......@@ -523,7 +512,6 @@ REF_JITTER1__TYPE = str
FFCLK1_DIFF_TERM = str
MULTICLK_PHASE_AXIHP__TYPE = str
FFCLK0_IOSTANDARD__TYPE = str
WOI_WIDTH__RAW = str
STATUS_MSB_RSHFT = int
CMPRS_CONTROL_REG__RAW = str
CLKIN_PERIOD__TYPE = str
......@@ -560,9 +548,8 @@ NUM_CYCLES_11 = int
SENS_GAMMA_ADDR_MASK = int
NUM_CYCLES_10 = int
MEMCLK_IBUF_LOW_PWR__TYPE = str
HISTOGRAM_HEIGHT__TYPE = str
CMPRS_HIFREQ_REG_BASE__TYPE = str
FCLK0_PERIOD__TYPE = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
DQTRI_LAST__TYPE = str
MULTICLK_DIVCLK__TYPE = str
......@@ -583,6 +570,7 @@ NUM_CYCLES_16 = int
NUM_CYCLES_15 = int
NUM_CYCLES_21__TYPE = str
CMPRS_CBIT_BAYER = int
GPIO_PORTEN__RAW = str
SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int
HISPI_DIFF_TERM__TYPE = str
......@@ -594,7 +582,6 @@ SENSI2C_TBL_SA__TYPE = str
BUF_IPCLK_SENS3__TYPE = str
MCNTRL_TILED_MODE = int
MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
HISTOGRAM_HEIGHT = int
MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
LOGGER_CONF_SYN = int
MCNTRL_TILED_CHN4_ADDR__RAW = str
......@@ -606,10 +593,6 @@ PICKLE__RAW = str
DQSTRI_LAST__RAW = str
WRITELEV_OFFSET__TYPE = str
CMPRS_BASE_INC = int
SIMULATE_CMPRS_CMODE2 = int
SIMULATE_CMPRS_CMODE3 = int
SIMULATE_CMPRS_CMODE0 = int
SIMULATE_CMPRS_CMODE1 = int
MULT_SAXI_CNTRL_ADDR = int
MULTICLK_BUF_SYNC__TYPE = str
HIST_SAXI_ADDR_REL__RAW = str
......@@ -635,15 +618,13 @@ CAMSYNC_EN_BIT = int
MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str
SENS_REFCLK_FREQUENCY__TYPE = str
HISTOGRAM_TOP__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int
SIMULATE_CMPRS_CMODE2__TYPE = str
MULT_SAXI_ADV_WR__RAW = str
LOGGER_PAGE_GPS = int
HIST_SAXI_MODE_ADDR_MASK = int
CMPRS_AFIMUX_SA_LEN__RAW = str
WRITELEV_OFFSET = int
LOGGER_CONF_MSG = int
CMPRS_CSAT_CR__RAW = str
CMPRS_CBIT_RUN = int
......@@ -658,10 +639,9 @@ MULT_SAXI_HALF_BRAM_IN__RAW = str
SENSI2C_TBL_SA__RAW = str
CMPRS_CBIT_CMODE_JP4__RAW = str
MULTICLK_BUF_AXIHP__RAW = str
CLK_STATUS__TYPE = str
DFLT_DQM_PATTERN__RAW = str
GPIO_SET_STATUS__RAW = str
SENS_JTAG_TCK = int
CMPRS_COLOR20__TYPE = str
DEBUG_STATUS_REG_ADDR__TYPE = str
REFRESH_OFFSET__TYPE = str
SENS_CTRL_ARST__RAW = str
......@@ -738,6 +718,7 @@ SENS_CTRL_QUADRANTS_WIDTH = int
STATUS_PSHIFTER_RDY_MASK__RAW = str
WBUF_DLY_DFLT__RAW = str
SENS_GAMMA_MODE_BAYER__TYPE = str
MULT_SAXI_CNTRL_IRQ = int
TILE_WIDTH__TYPE = str
MCNTRL_TILED_FRAME_LAST__RAW = str
SENSI2C_CMD_RESET__RAW = str
......@@ -756,7 +737,7 @@ LOGGER_PERIOD__RAW = str
MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
SENS_LENS_AX_MASK = int
AXI_RD_ADDR_BITS__RAW = str
AXI_WRADDR_LATENCY = int
RTC_BITC_PREDIV = int
SENS_SS_MOD_PERIOD__TYPE = str
MCONTR_LINTILE_SKIP_LATE__RAW = str
SENS_JTAG_PGMEN__TYPE = str
......@@ -794,28 +775,26 @@ CMPRS_AFIMUX_MASK = int
DLY_PHASE = int
CONTROL_RBACK_DEPTH__RAW = str
MCONTR_LINTILE_NRESET__RAW = str
MULT_SAXI_CNTRL_MODE = int
PHASE_WIDTH = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
MCNTRL_SCANLINE_MASK = int
MULTICLK_DIVCLK = int
MCNTRL_TILED_TILE_WHS__TYPE = str
MULT_SAXI_BSLOG3__TYPE = str
SENSOR12BITS_NGPL__RAW = str
CLKFBOUT_MULT__RAW = str
CMPRS_STATUS_REG_INC__RAW = str
SIMULATE_CMPRS_CMODE1__TYPE = str
HISTOGRAM_RADDR0__RAW = str
HISPI_KEEP_IRST = int
STATUS_ADDR_MASK = int
PXD_CAPACITANCE = str
SENS_LENS_AY = int
CMPRS_CBIT_CMODE_MONO6__TYPE = str
MULTICLK_BUF_XCLK__RAW = str
HISTOGRAM_RAM_MODE__RAW = str
SENS_LENS_AX_MASK__RAW = str
SENSI2C_TBL_SA_BITS = int
CMPRS_FRMT_MBCM1__TYPE = str
CMPRS_TIMEOUT__TYPE = str
SENSOR_HIST_EN_BITS__RAW = str
MULT_SAXI_ADV_WR = int
NUM_CYCLES_10__TYPE = str
MCONTR_LINTILE_EXTRAPG__RAW = str
......@@ -835,7 +814,6 @@ MCONTR_BUF4_WR_ADDR = int
SENS_DIVCLK_DIVIDE__RAW = str
SENSOR_BASE_INC__RAW = str
CMPRS_CBIT_DCSUB_BITS = int
HISTOGRAM_LEFT__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK = int
PXD_IBUF_LOW_PWR__TYPE = str
MCONTR_LINTILE_REPEAT__TYPE = str
......@@ -891,7 +869,6 @@ MCONTR_LINTILE_NRESET__TYPE = str
PXD_CLK_DIV__RAW = str
SENS_NUM_SUBCHN__RAW = str
CMPRS_CBIT_RUN_ENABLE__RAW = str
AXI_RDADDR_LATENCY__TYPE = str
BUF_IPCLK_SENS3__RAW = str
CLK_STATUS__RAW = str
MULTICLK_BUF_AXIHP = str
......@@ -901,10 +878,10 @@ SENS_CTRL_RST_MMCM = int
HISPI_DQS_BIAS__TYPE = str
MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str
SENSOR12BITS_TDDO1__RAW = str
CMPRS_CSAT_CB__TYPE = str
HISPI_MMCM0__TYPE = str
TILE_WIDTH = int
CMPRS_CONTROL_REG = int
GPIO_MASK = int
DLY_LANE0_ODELAY = long
NUM_XFER_BITS = int
HISPI_NUMLANES__RAW = str
......@@ -913,7 +890,6 @@ DLY_DQS_ODELAY__TYPE = str
DLY_LANE0_ODELAY__RAW = str
MCONTR_BUF3_WR_ADDR__TYPE = str
SCANLINE_STARTX__TYPE = str
CAMSYNC_MASTER_BIT__TYPE = str
WRITE_BLOCK_OFFSET = int
FRAME_FULL_WIDTH__RAW = str
LOGGER_CONF_EN__TYPE = str
......@@ -921,16 +897,15 @@ LOGGER_PAGE_IMU__RAW = str
SENS_SYNC_MINPER__RAW = str
CMPRS_AFIMUX_MODE__RAW = str
SENSI2C_TBL_RAH_BITS = int
SENS_SYNC_LATE__RAW = str
MULT_SAXI_CNTRL_IRQ__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
CHNBUF_READ_LATENCY__TYPE = str
CMPRS_CBIT_CMODE_BITS__TYPE = str
LOGGER_BIT_DURATION__TYPE = str
HISPI_MMCM1__RAW = str
MULT_SAXI_CNTRL_STATUS = int
TEST_INITIAL_BURST__TYPE = str
SENSOR12BITS_NVLO = int
NUM_CYCLES_19__RAW = str
SIMULATE_CMPRS_CMODE2__RAW = str
MCNTRL_PS_MASK__RAW = str
CMPRS_CBIT_CMODE_JPEG20__TYPE = str
HISPI_IBUF_LOW_PWR__TYPE = str
......@@ -943,7 +918,6 @@ CMPRS_TIMEOUT_BITS__TYPE = str
SENS_GAMMA_MODE_WIDTH__RAW = str
PHASE_CLK2X_PCLK__TYPE = str
FFCLK1_DIFF_TERM__TYPE = str
WRITELEV_OFFSET = int
MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
MULT_SAXI_ADV_RD__RAW = str
SENS_SYNC_RADDR = int
......@@ -974,7 +948,6 @@ CMPRS_MONO16__TYPE = str
READ_PATTERN_OFFSET__RAW = str
SENSI2C_TBL_DLY__TYPE = str
MEMBRIDGE_SIZE64 = int
SENSOR_IMAGE_TYPE1__RAW = str
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
CMPRS_FRMT_MBCM1_BITS = int
HISTOGRAM_RAM_MODE__TYPE = str
......@@ -982,9 +955,8 @@ AFI_LO_ADDR64 = int
NUM_CYCLES_07__TYPE = str
SENS_LENS_FAT0_IN = int
CMPRS_FRMT_LMARG_BITS__TYPE = str
SENSOR12BITS_NGPL__TYPE = str
HISTOGRAM_RADDR1__TYPE = str
SIMUL_AXI_READ_WIDTH = int
CAMSYNC_MASTER_BIT__TYPE = str
HISTOGRAM_ADDR_MASK = int
MCONTR_BUF2_RD_ADDR__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
......@@ -1009,6 +981,7 @@ CMPRS_CSAT_CB_BITS__RAW = str
CMPRS_CBIT_RUN__RAW = str
SENS_GAMMA_RADDR__RAW = str
SENS_CTRL_EXT_CLK = int
MULT_SAXI_IRQLEN_ADDR__RAW = str
SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
......@@ -1042,7 +1015,6 @@ MCONTR_TOP_STATUS_REG_ADDR = int
SENSI2C_STATUS_REG_INC__RAW = str
SDCLK_PHASE = float
SLEW_CMDA = str
SENSOR_IMAGE_TYPE0__RAW = str
MCNTRL_SCANLINE_MODE__TYPE = str
GPIO_N__RAW = str
TEST01_NEXT_PAGE__TYPE = str
......@@ -1059,13 +1031,13 @@ CAMSYNC_DELAY = int
BUF_IPCLK2X_SENS2__TYPE = str
MCNTRL_TEST01_CHN1_MODE__RAW = str
MULTICLK_PHASE_AXIHP__RAW = str
QUADRANTS_PXD_HACT_VACT = int
FFCLK0_IOSTANDARD__RAW = str
MULTICLK_DIV_XCLK__RAW = str
DFLT_DQS_TRI_ON_PATTERN__TYPE = str
MCONTR_PHY_0BIT_DLY_RST__TYPE = str
TILED_KEEP_OPEN__RAW = str
AXI_WRADDR_LATENCY__TYPE = str
MULTICLK_BUF_XCLK__RAW = str
MULT_SAXI_IRQLEN_ADDR = int
MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE = str
CLKFBOUT_PHASE_SENSOR__RAW = str
......@@ -1076,12 +1048,9 @@ MCNTRL_SCANLINE_FRAME_SIZE = int
STATUS_DEPTH = int
NUM_CYCLES_20__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
CAMSYNC_EXTERNAL_BIT__RAW = str
HISTOGRAM_WIDTH = int
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
MCNTRL_PS_STATUS_REG_ADDR = int
SENSI2C_TBL_NBRD__TYPE = str
SENSI2C_CMD_ACIVE_SDA = int
MCONTR_PHY_0BIT_ADDR__TYPE = str
......@@ -1108,7 +1077,7 @@ CMPRS_CBIT_FOCUS_BITS = int
LOGGER_CONF_SYN__RAW = str
CMPRS_COLOR20 = int
SENSI2C_CMD_TABLE__RAW = str
LAST_BUF_FRAME__RAW = str
SENSIO_DELAYS__TYPE = str
ADDRESS_NUMBER__TYPE = str
WSEL__TYPE = str
CMPRS_AFIMUX_CYCBITS__RAW = str
......@@ -1134,6 +1103,7 @@ MULT_SAXI_WLOG__TYPE = str
STATUS_2LSB_SHFT = int
HISPI_IFD_DELAY_VALUE = str
CMPRS_CBIT_CMODE_JP4DC = int
MULT_SAXI_IRQLEN_MASK = int
NUM_CYCLES_08__TYPE = str
NUM_CYCLES_LOW_BIT__RAW = str
SENSI2C_TBL_NBRD_BITS__TYPE = str
......@@ -1165,7 +1135,6 @@ NUM_CYCLES_29__RAW = str
GPIO_SET_STATUS__TYPE = str
SENSIO_STATUS_REG_REL__RAW = str
FFCLK0_CAPACITANCE__RAW = str
SENSOR12BITS_TDDO1__TYPE = str
CMDFRAMESEQ_ABS = int
CMPRS_MONO8 = int
MULT_SAXI_ADDR__RAW = str
......@@ -1175,7 +1144,6 @@ MCNTRL_SCANLINE_MASK__RAW = str
MULT_SAXI_STATUS_REG__RAW = str
MCONTR_LINTILE_EN__RAW = str
SENSI2C_ADDR_MASK__TYPE = str
SENSOR12BITS_NVLO__RAW = str
CAMSYNC_EXTERNAL_BIT__TYPE = str
CMPRS_BASE_INC__RAW = str
SENS_SYNC_FBITS = int
......@@ -1186,7 +1154,6 @@ MEMBRIDGE_CTRL__TYPE = str
TILED_KEEP_OPEN__TYPE = str
CMPRS_CBIT_RUN_RST__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
SENSOR12BITS_TDDO__TYPE = str
MULTICLK_DIV_SYNC = int
CLK_STATUS_REG_ADDR = int
CLK_DIV_PHASE__TYPE = str
......@@ -1196,7 +1163,6 @@ CLKFBOUT_USE_FINE_PS__RAW = str
CMPRS_FRMT_LMARG__RAW = str
CMDFRAMESEQ_IRQ_BIT__RAW = str
LOGGER_BIT_DURATION = int
FCLK1_PERIOD__TYPE = str
CAMSYNC_MODE__TYPE = str
CHNBUF_READ_LATENCY__RAW = str
NUM_CYCLES_12__RAW = str
......@@ -1214,7 +1180,6 @@ PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str
CLK_CNTRL__TYPE = str
HISTOGRAM_WIDTH__RAW = str
GPIO_MASK__RAW = str
DFLT_REFRESH_ADDR__TYPE = str
SENS_GAMMA_MODE_REPET__TYPE = str
......@@ -1229,13 +1194,13 @@ MEMBRIDGE_SIZE64__TYPE = str
HISPI_IOSTANDARD = str
LOGGER_CONF_IMU__RAW = str
CMPRS_CBIT_CMODE_JP4DC__RAW = str
MULT_SAXI_IRQLEN_MASK__RAW = str
MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN1_MODE__TYPE = str
SENS_SYNC_FBITS__TYPE = str
HISPI_UNTUNED_SPLIT = str
MCONTR_TOP_0BIT_ADDR_MASK = int
HISPI_IBUF_DELAY_VALUE__TYPE = str
SENSOR12BITS_NGPL = int
CMDFRAMESEQ_REL = int
CAMSYNC_POST_MAGIC__TYPE = str
NUM_CYCLES_29__TYPE = str
......@@ -1253,7 +1218,6 @@ MEMCLK_CAPACITANCE__TYPE = str
MCONTR_BUF0_WR_ADDR__RAW = str
SENS_GAMMA_MODE_WIDTH = int
SENS_SS_MODE = str
SENSOR12BITS_TDDO = int
CAMSYNC_TRIG_DST = int
DLY_LANE1_ODELAY__TYPE = str
CMPRS_AFIMUX_WIDTH__TYPE = str
......@@ -1269,7 +1233,6 @@ CMPRS_COLOR18 = int
LOGGER_CONF_MSG__TYPE = str
MCNTRL_TILED_MASK__RAW = str
MULTICLK_DIV_AXIHP__RAW = str
SENSI2C_CMD_SOFT_SDA__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
SENSI2C_STATUS_REG_BASE = int
MCNTRL_TILED_STATUS_CNTRL__RAW = str
......@@ -1305,7 +1268,6 @@ SENS_REF_JITTER1 = float
SENS_REF_JITTER2 = float
MCNTRL_TILED_FRAME_SIZE__RAW = str
MULT_SAXI_HALF_BRAM__RAW = str
SIMUL_AXI_READ_WIDTH__TYPE = str
DFLT_DQS_TRI_ON_PATTERN__RAW = str
SLEW_DQ = str
SENS_GAMMA_MODE_REPET__RAW = str
......@@ -1315,7 +1277,6 @@ SLEW_DQS__TYPE = str
SENSIO_ADDR_MASK = int
SCANLINE_STARTY = int
SCANLINE_STARTX = int
SIMULATE_CMPRS_CMODE1__RAW = str
FFCLK0_DIFF_TERM__TYPE = str
HISPI_UNTUNED_SPLIT__TYPE = str
LD_DLY_CMDA__TYPE = str
......@@ -1327,9 +1288,7 @@ SENSI2C_IOSTANDARD__TYPE = str
REFCLK_FREQUENCY__TYPE = str
CLKOUT_DIV_PCLK2X__TYPE = str
MEMBRIDGE_CTRL = int
SENSOR_IMAGE_TYPE3__TYPE = str
HISTOGRAM_LEFT = int
MULT_SAXI_HALF_BRAM__TYPE = str
CMPRS_TIMEOUT__TYPE = str
MCONTR_PHY_STATUS_CNTRL = int
SENSOR_GROUP_ADDR = int
NUM_CYCLES_14 = int
......@@ -1358,7 +1317,6 @@ HISTOGRAM_RADDR1 = int
HISTOGRAM_RADDR2 = int
HISTOGRAM_RADDR3 = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
HISTOGRAM_LEFT__TYPE = str
SENS_LENS_AY_MASK__TYPE = str
SENS_CTRL_IGNORE_EMBED__RAW = str
READ_BLOCK_OFFSET__TYPE = str
......@@ -1370,12 +1328,10 @@ MCNTRL_TEST01_CHN2_MODE = int
MCNTRL_TILED_WINDOW_WH__TYPE = str
SS_MOD_PERIOD__RAW = str
CMPRS_NUM_AFI_CHN__RAW = str
SENSOR_IMAGE_TYPE3 = str
MULTICLK_DIV_AXIHP__TYPE = str
HISPI_DELAY_CLK2__TYPE = str
MULT_SAXI_ADV_RD = int
WSEL__RAW = str
SENSOR_PRIORITY = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
DLY_PHASE__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
......@@ -1385,6 +1341,7 @@ BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS1 = str
SENSI2C_TBL_NABRD = int
SLEW_CMDA__TYPE = str
MULT_SAXI_CNTRL_MODE__TYPE = str
NUM_CYCLES_19__TYPE = str
CMPRS_CORING_MODE__RAW = str
MEMBRIDGE_ADDR = int
......@@ -1399,9 +1356,7 @@ WBUF_DLY_DFLT = int
SENS_JTAG_PROG = int
MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
FFCLK0_IOSTANDARD = str
AXI_TASK_HOLD__TYPE = str
SENS_GAMMA_ADDR_MASK__RAW = str
SENSOR_IMAGE_TYPE3__RAW = str
DLY_LANE1_IDELAY__TYPE = str
SENS_LENS_BY_MASK = int
DEBUG_MASK__RAW = str
......@@ -1423,15 +1378,12 @@ DLY_CMDA = long
SENS_GAMMA_MODE_BAYER = int
LAST_BUF_FRAME__TYPE = str
CMPRS_HIFREQ_REG_BASE = int
FCLK1_PERIOD__RAW = str
MCONTR_ARBIT_ADDR = int
MEMBRIDGE_CTRL__RAW = str
CMPRS_CBIT_RUN_RST__RAW = str
TABLE_QUANTIZATION_INDEX = int
NUM_CYCLES_04__TYPE = str
SENSOR_IMAGE_TYPE2 = str
SENSOR_IMAGE_TYPE1 = str
SENSOR_IMAGE_TYPE0 = str
WSEL__RAW = str
SENS_CTRL_IGNORE_EMBED = int
RTC_MASK__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS = int
......@@ -1444,11 +1396,9 @@ CAMSYNC_TRIG_DELAY1__TYPE = str
HIGH_PERFORMANCE_MODE = str
DQTRI_LAST__RAW = str
MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
SIMULATE_CMPRS_CMODE3__TYPE = str
DFLT_DQM_PATTERN = int
HISPI_NUMLANES = int
SENSI2C_CMD_RUN = int
AXI_WRDATA_LATENCY__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
NUM_CYCLES_04 = int
SENS_LENS_C__TYPE = str
......@@ -1508,8 +1458,9 @@ INITIALIZE_OFFSET__TYPE = str
SENSOR_FIFO_DELAY__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str
IDELAY_VALUE__TYPE = str
SENSOR_IMAGE_TYPE2__RAW = str
CMPRS_CBIT_CMODE_JP4DC__TYPE = str
MULT_SAXI_IRQLEN_ADDR__TYPE = str
MULT_SAXI_IRQLEN_MASK__TYPE = str
PICKLE__TYPE = str
SENSI2C_TBL_NBWR__RAW = str
TABLE_FOCUS_INDEX__RAW = str
......@@ -1526,7 +1477,6 @@ SENSI2C_CTRL = int
SENS_SYNC_MULT = int
CLK_ADDR__RAW = str
SENSIO_CTRL__RAW = str
HISTOGRAM_WIDTH__TYPE = str
MCNTRL_TILED_TILE_WHS = int
NUM_CYCLES_03__RAW = str
MULT_SAXI_HALF_BRAM = int
......@@ -1543,14 +1493,12 @@ MCONTR_TOP_0BIT_ADDR = int
NUM_CYCLES_05__RAW = str
MEMBRIDGE_MODE = int
MCNTRL_TILED_FRAME_LAST__TYPE = str
QUADRANTS_PXD_HACT_VACT__RAW = str
MCONTR_CMPRS_STATUS_INC__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR = int
TABLE_CORING_INDEX__RAW = str
SENSI2C_CMD_RESET__TYPE = str
MCONTR_ARBIT_ADDR__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str
AXI_TASK_HOLD = float
ADDRESS_NUMBER = int
SENS_SYNC_LATE__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
......@@ -1599,8 +1547,6 @@ CMPRS_CBIT_BAYER_BITS = int
PXD_SLEW__RAW = str
MULT_SAXI_STATUS_REG = int
CLKIN_PERIOD_SENSOR__TYPE = str
QUADRANTS_PXD_HACT_VACT__TYPE = str
SENSOR_PRIORITY__TYPE = str
SENS_LENS_BY__RAW = str
MCNTRL_PS_CMD__TYPE = str
SENS_SYNC_MASK__RAW = str
......@@ -1643,11 +1589,11 @@ GPIO_SLEW__RAW = str
MULTICLK_PHASE_DLYREF__TYPE = str
TEST01_START_FRAME__RAW = str
CMDFRAMESEQ_ABS__RAW = str
FRAME_WIDTH_ROUND_BITS__TYPE = str
CMPRS_AFIMUX_SA_LEN__RAW = str
BUF_IPCLK2X_SENS0__RAW = str
MCONTR_BUF4_WR_ADDR__RAW = str
DFLT_DQM_PATTERN__RAW = str
CMPRS_CSAT_CB__TYPE = str
CLK_STATUS__TYPE = str
CMPRS_COLOR20__TYPE = str
T_REFI__TYPE = str
MCONTR_CMD_WR_ADDR__TYPE = str
SENSI2C_CMD_SOFT_SCL__TYPE = str
......@@ -1659,7 +1605,6 @@ MCNTRL_TEST01_MASK = int
TEST01_NEXT_PAGE__RAW = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
SENSOR12BITS_NVLO__TYPE = str
MCONTR_LINTILE_EXTRAPG__TYPE = str
NUM_CYCLES_06__TYPE = str
SCANLINE_STARTX__RAW = str
......@@ -1676,9 +1621,8 @@ WRITELEV_OFFSET__RAW = str
READ_PATTERN_OFFSET = int
CLK_PHASE__TYPE = str
SENSOR_16BIT_BIT = int
SENSIO_DELAYS__TYPE = str
MCNTRL_PS_STATUS_REG_ADDR = int
SENS_CTRL_EXT_CLK__RAW = str
WOI_HEIGHT = int
LOGGER_PAGE_GPS__TYPE = str
T_REFI = int
HIST_CONFIRM_WRITE__TYPE = str
......@@ -1718,7 +1662,6 @@ HIGH_PERFORMANCE_MODE__RAW = str
DFLT_DQM_PATTERN__TYPE = str
STATUS_ADDR__TYPE = str
MCONTR_PHY_0BIT_CMDA_EN = int
WOI_WIDTH = int
CMPRS_AFIMUX_WIDTH__RAW = str
BUF_CLK1X_PCLK2X = str
MCNTRL_TEST01_CHN4_MODE = int
......@@ -1734,7 +1677,6 @@ INITIALIZE_OFFSET__RAW = str
CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str
CMPRS_AFIMUX_RST__RAW = str
SENSOR12BITS_TDDO__RAW = str
CAMSYNC_TRIG_DST__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
CAMSYNC_TRIG_DELAY3__TYPE = str
......@@ -1742,7 +1684,6 @@ FRAME_START_ADDRESS__RAW = str
IPCLK_PHASE = float
SENSI2C_CTRL_RADDR = int
HIST_SAXI_MODE_ADDR_REL__RAW = str
AXI_WRDATA_LATENCY = int
SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MULTICLK_PHASE_FB__TYPE = str
......@@ -1760,12 +1701,11 @@ MEMCLK_IOSTANDARD = str
DLY_LANE1_ODELAY__RAW = str
SENSI2C_IBUF_LOW_PWR__RAW = str
SENSI2C_STATUS_REG_REL = int
AXI_RDADDR_LATENCY__RAW = str
MULT_SAXI_HALF_BRAM__TYPE = str
SENSOR_CTRL_ADDR_MASK = int
NUM_CYCLES_16__TYPE = str
MEMBRIDGE_LO_ADDR64__TYPE = str
CMDFRAMESEQ_MASK__RAW = str
SENSOR12BITS_TMD__TYPE = str
SENS_CTRL_LD_DLY__TYPE = str
MCONTR_TOP_16BIT_ADDR__TYPE = str
PXD_SLEW = str
......@@ -1824,10 +1764,8 @@ LOGGER_STATUS_MASK = int
MULTICLK_PHASE_XCLK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN__RAW = str
HISPI_CAPACITANCE = str
HISTOGRAM_START_PAGE__RAW = str
CONTROL_ADDR_MASK = int
LOGGER_PERIOD = int
MEMCLK_PERIOD__RAW = str
MCONTR_BUF0_WR_ADDR = int
MCNTRL_PS_STATUS_REG_ADDR__RAW = str
LOGGER_STATUS_MASK__RAW = str
......@@ -1850,7 +1788,6 @@ SENS_REF_JITTER2__RAW = str
SCANLINE_EXTRA_PAGES__RAW = str
CMDSEQMUX_STATUS__RAW = str
MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
SENSOR_IMAGE_TYPE0__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str
DIVCLK_DIVIDE_PCLK = int
MCNTRL_PS_MASK = int
......@@ -1880,7 +1817,6 @@ SENS_LENS_SCALES__TYPE = str
SENS_LENS_COEFF__TYPE = str
LOGGER_STATUS__RAW = str
SENS_JTAG_TMS__RAW = str
FRAME_WIDTH_ROUND_BITS__RAW = str
FFCLK0_IBUF_LOW_PWR__RAW = str
SENS_CTRL_MRST = int
MCNTRL_SCANLINE_FRAME_LAST__TYPE = str
......@@ -1888,7 +1824,6 @@ MCONTR_SENS_STATUS_BASE__RAW = str
MCNTRL_TEST01_CHN3_MODE__TYPE = str
MCONTR_BUF2_RD_ADDR__TYPE = str
SENS_SYNC_RADDR__RAW = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
CLKFBOUT_PHASE_SENSOR__TYPE = str
SENSOR_HIST_NRST_BITS__TYPE = str
......@@ -1897,14 +1832,12 @@ RTC_STATUS_REG_ADDR__TYPE = str
SENS_JTAG_TCK__TYPE = str
MCNTRL_TILED_FRAME_SIZE__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
WOI_HEIGHT__RAW = str
SENS_LENS_COEFF = int
MULTICLK_PHASE_XCLK__RAW = str
LOGGER_BIT_DURATION__RAW = str
MCONTR_WR_MASK__TYPE = str
SENS_LENS_C__RAW = str
CMDFRAMESEQ_ADDR_BASE__TYPE = str
AXI_WRDATA_LATENCY__TYPE = str
SENS_GAMMA_HEIGHT01 = int
RTC_SET_SEC__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
......@@ -1923,7 +1856,6 @@ CMPRS_INTERRUPTS = int
SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
MEMCLK_CAPACITANCE__RAW = str
DQTRI_FIRST = int
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
......@@ -1931,7 +1863,6 @@ CAMSYNC_TRIG_DELAY0 = int
CAMSYNC_TRIG_DELAY1 = int
MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
CAMSYNC_TRIG_DELAY3 = int
SIMUL_AXI_READ_WIDTH__RAW = str
MCONTR_SENS_STATUS_INC = int
CAMSYNC_TRIGGERED_BIT__TYPE = str
SENS_GAMMA_MODE_TRIG__TYPE = str
......@@ -1956,7 +1887,6 @@ TABLE_CORING_INDEX__TYPE = str
HISTOGRAM_RADDR1__RAW = str
SENSI2C_CMD_TAND__TYPE = str
MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
SENS_BANDWIDTH = str
MCNTRL_SCANLINE_MODE__RAW = str
LOGGER_BIT_HALF_PERIOD__TYPE = str
FRAME_START_ADDRESS_INC__RAW = str
......@@ -1970,6 +1900,7 @@ HISPI_FIFO_DEPTH = int
CLKFBOUT_PHASE = float
SENS_GAMMA_ADDR_DATA = int
HISPI_WAIT_ALL_LANES = int
MULT_SAXI_CNTRL_MODE__RAW = str
SENS_GAMMA_ADDR_DATA__TYPE = str
CAMSYNC_DELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
......@@ -2007,8 +1938,6 @@ SENS_PHASE_WIDTH__RAW = str
SENS_REF_JITTER2__TYPE = str
FFCLK0_IBUF_LOW_PWR = str
DFLT_DQ_TRI_ON_PATTERN__TYPE = str
FRAME_WIDTH_ROUND_BITS = int
LD_DLY_LANE1_IDELAY__TYPE = str
CMPRS_AFIMUX_MODE__TYPE = str
DQTRI_FIRST__TYPE = str
MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
......@@ -2066,7 +1995,7 @@ DLY_DQ_ODELAY__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
CMPRS_CORING_BITS = int
CMDFRAMESEQ_MASK__TYPE = str
SENS_JTAG_TMS__TYPE = str
FFCLK1_IOSTANDARD = str
CLK_PHASE__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
GPIO_MASK__TYPE = str
......@@ -2089,7 +2018,6 @@ CMPRS_JP4 = int
CAMSYNC_CHN_EN_BIT = int
SENSIO_STATUS_REG_REL__TYPE = str
MULTICLK_BUF_XCLK = str
HISTOGRAM_START_PAGE__TYPE = str
MCNTRL_SCANLINE_MODE = int
DLY_LANE0_IDELAY = long
MCNTRL_PS_CMD = int
......@@ -2117,7 +2045,6 @@ SENS_LENS_AY__RAW = str
SS_EN = str
SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE = str
SENSOR_IMAGE_TYPE2__TYPE = str
IBUF_LOW_PWR__TYPE = str
CLK_DIV_PHASE = float
MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
......@@ -2130,7 +2057,7 @@ NUM_CYCLES_11__RAW = str
FFCLK1_CAPACITANCE__RAW = str
SENSI2C_DRIVE__RAW = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENS_LENS_C = int
SENSI2C_CMD_SOFT_SDA__RAW = str
SENSOR_CTRL_ADDR_MASK__RAW = str
DFLT_CHN_EN__RAW = str
NUM_CYCLES_LOW_BIT = int
......@@ -2178,7 +2105,6 @@ DFLT_WBUF_DELAY = int
CONTROL_RBACK_ADDR_MASK__RAW = str
AXI_WR_ADDR_BITS__TYPE = str
RTC_SET_STATUS = int
SENSOR_HIST_EN_BITS__RAW = str
MULT_SAXI_ADV_WR__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
FRAME_FULL_WIDTH = int
......@@ -2230,14 +2156,13 @@ MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
CMPRS_INTERRUPTS__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
WOI_HEIGHT__TYPE = str
STATUS_SEQ_SHFT__TYPE = str
MCONTR_CMPRS_BASE = int
DEBUG_SET_STATUS__TYPE = str
HISTOGRAM_START_PAGE = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
RTC_SEC_USEC_ADDR__RAW = str
MCNTRL_PS_ADDR = int
HISTOGRAM_HEIGHT__RAW = str
SENS_BANDWIDTH = str
MEMCLK_IBUF_LOW_PWR = str
HISPI_DELAY_CLK3__RAW = str
CAMSYNC_TRIG_DST__TYPE = str
......@@ -2258,7 +2183,6 @@ SENSI2C_REL_RADDR__RAW = str
MCONTR_ARBIT_ADDR__RAW = str
MCONTR_LINTILE_EN__TYPE = str
SENSI2C_REL_RADDR__TYPE = str
AXI_WRADDR_LATENCY__RAW = str
GPIO_DRIVE = int
HISPI_MSB_FIRST__RAW = str
SENS_LENS_SCALES = int
......@@ -2278,14 +2202,12 @@ HISPI_DELAY_CLK2__RAW = str
SS_MOD_PERIOD__TYPE = str
TILE_HEIGHT = int
MULT_SAXI_MASK__RAW = str
SENSOR12BITS_TMD = int
MCONTR_CMPRS_STATUS_BASE__TYPE = str
NUM_CYCLES_10__RAW = str
SENS_LENS_FAT0_OUT__TYPE = str
DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str
SENS_NUM_SUBCHN = int
FRAME_HEIGHT_BITS = int
MCONTR_BUF0_WR_ADDR__TYPE = str
SENSOR_CHN_EN_BIT__TYPE = str
CMPRS_COLOR18__RAW = str
......
py393/x393_export_c.py
View file @ 3ed89577
......@@ -586,6 +586,18 @@ class X393ExportC(object):
data = self._enc_mult_saxi_addr(),
name = "x393_mult_saxi_al", typ="rw", # some - wo, others - ro
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULT_SAXI DMA DW address bit to change for interrupt to be generated",
data = self._enc_mult_saxi_irqlen(),
name = "x393_mult_saxi_irqlen", typ="rw", # some - wo, others - ro
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULT_SAXI DMA mode register (per channel enable/run)",
data = self._enc_mult_saxi_mode(),
name = "x393_mult_saxi_mode", typ="rw", # some - wo, others - ro
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULT_SAXI per-channel interrupt control",
data = self._enc_mult_saxi_interrupts(),
name = "x393_mult_saxi_interrupts", typ="wo", # some - wo, others - ro
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULTICLK reset/power down controls",
data = self._enc_multiclk_ctl(),
......@@ -1066,7 +1078,7 @@ class X393ExportC(object):
sdefines +=[
(('Event logger',)),
(('_Event logger configuration/data is writtent to the module ising two 32-bit register locations : data and address.',)),
(('_Event logger configuration/data is written to the module using two 32-bit register locations : data and address.',)),
(('_Address consists of 2 parts - 2-bit page (configuration, imu, gps, message) and a 5-bit sub-address autoincremented when writing data.',)),
(('_Register pages:',)),
(("X393_LOGGER_PAGE_CONF", "", 0 , 0, None, None, "", "Logger configuration page")),
......@@ -1091,10 +1103,13 @@ class X393ExportC(object):
c = "chn"
sdefines +=[
(('MULT SAXI DMA engine control. Of 4 channels only one (number 0) is currently used - for the event logger',)),
(("X393_MULT_SAXI_STATUS_CTRL", "", vrlg.MULT_SAXI_CNTRL_ADDR, 0, None, "x393_status_ctrl", "rw", "MULT_SAXI status control mode (status provides current DWORD pointer)")),
(("X393_MULT_SAXI_BUF_ADDRESS", c, vrlg.MULT_SAXI_ADDR + 0, 2, z3, "x393_mult_saxi_al", "wo", "MULT_SAXI buffer start address in DWORDS")),
(("X393_MULT_SAXI_BUF_LEN", c, vrlg.MULT_SAXI_ADDR + 1, 2, z3, "x393_mult_saxi_al", "wo", "MULT_SAXI buffer length in DWORDS")),
(("X393_MULT_SAXI_STATUS", c, vrlg.STATUS_ADDR + vrlg.MULT_SAXI_STATUS_REG, 1, z3, "x393_mult_saxi_al", "ro", "MULT_SAXI current DWORD pointer"))]
(("X393_MULT_SAXI_MODE", "", vrlg.MULT_SAXI_CNTRL_ADDR+vrlg.MULT_SAXI_CNTRL_MODE, 0, None, "x393_mult_saxi_mode", "rw","MULT_SAXI mode register (per-channel enable and run bits)")),
(("X393_MULT_SAXI_STATUS_CTRL", "", vrlg.MULT_SAXI_CNTRL_ADDR+vrlg.MULT_SAXI_CNTRL_STATUS, 0, None, "x393_status_ctrl", "rw","MULT_SAXI status control mode (status provides current DWORD pointers)")),
(("X393_MULT_SAXI_INTERRUPTS", "", vrlg.MULT_SAXI_CNTRL_ADDR+vrlg.MULT_SAXI_CNTRL_IRQ, 0, None, "x393_mult_saxi_interrupts", "wo","MULT_SAXI per-channel interrupts control (each dibit:nop/reset/disable/enable)")),
(("X393_MULT_SAXI_BUF_ADDRESS", c, vrlg.MULT_SAXI_ADDR + 0, 2, z3, "x393_mult_saxi_al", "wo","MULT_SAXI buffer start address in DWORDS")),
(("X393_MULT_SAXI_BUF_LEN", c, vrlg.MULT_SAXI_ADDR + 1, 2, z3, "x393_mult_saxi_al", "wo","MULT_SAXI buffer length in DWORDS")),
(("X393_MULT_SAXI_IRQLEN", c, vrlg.MULT_SAXI_IRQLEN_ADDR, 1, z3, "x393_mult_saxi_al", "wo","MULT_SAXI lower DWORD address bit to change to generate interrupt")),
(("X393_MULT_SAXI_STATUS", c, vrlg.STATUS_ADDR + vrlg.MULT_SAXI_STATUS_REG, 1, z3, "x393_mult_saxi_al", "ro","MULT_SAXI current DWORD pointer"))]
#MULTI_CLK global clock generation PLLs
ba = 0
......@@ -2329,9 +2344,33 @@ class X393ExportC(object):
def _enc_mult_saxi_addr(self):
dw=[]
dw.append(("addr32", 0, 30, 0, "SAXI sddress/length in DWORDs"))
dw.append(("addr32", 0, 30, 0, "SAXI address/length in DWORDs"))
return dw
def _enc_mult_saxi_irqlen(self):
dw=[]
dw.append(("irqlen", 0, 5, 0, "lowest DW address bit that has to change to generate interrupt"))
return dw
def _enc_mult_saxi_mode(self):
dw=[]
dw.append(("en0", 0, 1, 0, "Channel 0 enable (0 - reset)"))
dw.append(("en1", 1, 1, 0, "Channel 1 enable (0 - reset)"))
dw.append(("en2", 2, 1, 0, "Channel 2 enable (0 - reset)"))
dw.append(("en3", 3, 1, 0, "Channel 3 enable (0 - reset)"))
dw.append(("run0", 4, 1, 0, "Channel 0 run (0 - stop)"))
dw.append(("run1", 5, 1, 0, "Channel 1 run (0 - stop)"))
dw.append(("run2", 6, 1, 0, "Channel 2 run (0 - stop)"))
dw.append(("run3", 7, 1, 0, "Channel 3 run (0 - stop)"))
return dw
def _enc_mult_saxi_interrupts(self):
dw=[]
dw.append(("interrupt_cmd0", 0, 2, 0, "Channel 0 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
dw.append(("interrupt_cmd1", 2, 2, 0, "Channel 1 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
dw.append(("interrupt_cmd2", 4, 2, 0, "Channel 2 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
dw.append(("interrupt_cmd3", 6, 2, 0, "Channel 3 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
return dw
def _enc_multiclk_ctl(self):
dw=[]
dw.append(("rst_clk0", 0, 1, 0, "Reset PLL for xclk(240MHz), hclk(150MHz)"))
......
system_defines.vh
View file @ 3ed89577
......@@ -63,7 +63,7 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
......
x393.v
View file @ 3ed89577
......@@ -548,6 +548,7 @@ module x393 #(
wire [3:0] stuffer_done_mclk; // output// SuppressThisWarning VEditor - (yet) unused
wire [3:0] cmprs_irq; // compressor done, data confirmed written to memory)
wire [3:0] mult_saxi_irq; // interrupts from mult_saxi channels
// Compressor frame synchronization
......@@ -2323,7 +2324,11 @@ assign axi_grst = axi_rst_pre;
mult_saxi_wr #(
.MULT_SAXI_ADDR (MULT_SAXI_ADDR),
.MULT_SAXI_IRQLEN_ADDR (MULT_SAXI_IRQLEN_ADDR),
.MULT_SAXI_CNTRL_ADDR (MULT_SAXI_CNTRL_ADDR),
.MULT_SAXI_CNTRL_MODE (MULT_SAXI_CNTRL_MODE),
.MULT_SAXI_CNTRL_STATUS (MULT_SAXI_CNTRL_STATUS),
.MULT_SAXI_CNTRL_IRQ (MULT_SAXI_CNTRL_IRQ),
.MULT_SAXI_STATUS_REG (MULT_SAXI_STATUS_REG),
.MULT_SAXI_HALF_BRAM (MULT_SAXI_HALF_BRAM),
.MULT_SAXI_BSLOG0 (MULT_SAXI_BSLOG0),
......@@ -2331,6 +2336,7 @@ assign axi_grst = axi_rst_pre;
.MULT_SAXI_BSLOG2 (MULT_SAXI_BSLOG2),
.MULT_SAXI_BSLOG3 (MULT_SAXI_BSLOG3),
.MULT_SAXI_MASK (MULT_SAXI_MASK),
.MULT_SAXI_IRQLEN_MASK (MULT_SAXI_IRQLEN_MASK),
.MULT_SAXI_CNTRL_MASK (MULT_SAXI_CNTRL_MASK),
.MULT_SAXI_AWCACHE (MULT_SAXI_AWCACHE),
.MULT_SAXI_ADV_WR (MULT_SAXI_ADV_WR),
......@@ -2367,28 +2373,29 @@ assign axi_grst = axi_rst_pre;
.read_burst3 (), // output
.data_in_chn3 (32'b0), // input[31:0]
.pre_valid_chn3 (1'b0), // input
.irq (mult_saxi_irq[3:0]), // output[3:0]
.saxi_awaddr (saxi1_awaddr), // output[31:0]
.saxi_awvalid (saxi1_awvalid), // output
.saxi_awready (saxi1_awready), // input
.saxi_awid (saxi1_awid), // output[5:0]
.saxi_awlock (saxi1_awlock), // output[1:0]
.saxi_awcache (saxi1_awcache), // output[3:0]
.saxi_awprot (saxi1_awprot), // output[2:0]
.saxi_awlen (saxi1_awlen), // output[3:0]
.saxi_awsize (saxi1_awsize), // output[1:0]
.saxi_awburst (saxi1_awburst), // output[1:0]
.saxi_awqos (saxi1_awqos), // output[3:0]
.saxi_wdata (saxi1_wdata), // output[31:0]
.saxi_wvalid (saxi1_wvalid), // output
.saxi_wready (saxi1_wready), // input
.saxi_wid (saxi1_wid), // output[5:0]
.saxi_wlast (saxi1_wlast), // output
.saxi_wstrb (saxi1_wstrb), // output[3:0]
.saxi_bvalid (saxi1_bvalid), // input
.saxi_bready (saxi1_bready), // output
.saxi_bid (saxi1_bid), // input[5:0]
.saxi_bresp (saxi1_bresp) // input[1:0]
.saxi_awaddr (saxi1_awaddr), // output[31:0]
.saxi_awvalid (saxi1_awvalid), // output
.saxi_awready (saxi1_awready), // input
.saxi_awid (saxi1_awid), // output[5:0]
.saxi_awlock (saxi1_awlock), // output[1:0]
.saxi_awcache (saxi1_awcache), // output[3:0]
.saxi_awprot (saxi1_awprot), // output[2:0]
.saxi_awlen (saxi1_awlen), // output[3:0]
.saxi_awsize (saxi1_awsize), // output[1:0]
.saxi_awburst (saxi1_awburst), // output[1:0]
.saxi_awqos (saxi1_awqos), // output[3:0]
.saxi_wdata (saxi1_wdata), // output[31:0]
.saxi_wvalid (saxi1_wvalid), // output
.saxi_wready (saxi1_wready), // input
.saxi_wid (saxi1_wid), // output[5:0]
.saxi_wlast (saxi1_wlast), // output
.saxi_wstrb (saxi1_wstrb), // output[3:0]
.saxi_bvalid (saxi1_bvalid), // input
.saxi_bready (saxi1_bready), // output
.saxi_bid (saxi1_bid), // input[5:0]
.saxi_bresp (saxi1_bresp) // input[1:0]
);
clocks393m #(
......@@ -2943,7 +2950,7 @@ sata_ahci_top sata_top(
.DMA3DATYPE(), // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA3RSTN(), // DMAC 3 RESET output (reserved, do not use), output
// Interrupt signals
.IRQF2P({4'b0,
.IRQF2P({mult_saxi_irq[3:0], // [19:16] interrupts from mult_saxi channels
cmprs_irq[3:0], // [15:12] Compressor done interrupts
frseq_irq[3:0], // [11: 8] Frame sync interrupts
7'b0,
......
x393_hispi.bit
View file @ 3ed89577
No preview for this file type
x393_parallel.bit
View file @ 3ed89577
No preview for this file type
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