Commit 3647f8ed authored by Andrey Filippov's avatar Andrey Filippov
Browse files

added new gtkwave sav, changes to old files to satisfy newer Icarus. FPGA 0x03031003

parent e982c5ae

cocotb/x393_cocotb_lwir_07.sav

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+1501 −0

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cocotb/x393_cocotb_lwir_08.sav

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ddr3/ddr3.v

+5 −5
Original line number Diff line number Diff line
@@ -2534,7 +2534,7 @@ module ddr3 ( 
    end



    task cmd_addr_timing_check;

    input i;

    input [4:0]i;

    reg [4:0] i;

    begin

        if (rst_n_in && prev_cke) begin
@@ -2578,7 +2578,7 @@ module ddr3 ( 


    // Processes to check setup and hold of data signals

    task dm_timing_check;

    input i;

    input [4:0] i;

    reg [4:0] i;

    begin

        if (dqs_in_valid) begin
@@ -2629,7 +2629,7 @@ module ddr3 ( 
    always @(dm_in[31]) dm_timing_check(31);



    task dq_timing_check;

    input i;

    input [6:0] i;

    reg [6:0] i;

    begin

        if (dqs_in_valid) begin
@@ -2776,7 +2776,7 @@ module ddr3 ( 
    always @(dq_in[127]) dq_timing_check(127);

   

    task dqs_pos_timing_check;

    input i;

    input [5:0] i;

    reg [5:0] i;

    reg [4:0] j;

    begin
@@ -2911,7 +2911,7 @@ module ddr3 ( 
    always @(negedge dqs_in[63]) if (!dqs_in[63]) dqs_pos_timing_check(63);

   

    task dqs_neg_timing_check;

    input i;

    input [5:0] i;

    reg [5:0] i;

    reg [4:0] j;

    begin

x393_sata/wrapper/GTXE2_GPL.v

+6 −3
Original line number Diff line number Diff line
@@ -772,7 +772,9 @@ assign next_disparity = ^oword[word_count - 1] ? word_disparity[word_count - 1] 
endmodule



module gtxe2_chnl_tx_oob #(

    parameter width = 20

    parameter       width = 20,

    parameter [3:0] SATA_BURST_SEQ_LEN = 4'b0101,

    parameter       SATA_CPLL_CFG = "VCO_3000MHZ"

)

(

// top-level ifaces
@@ -787,8 +789,8 @@ module gtxe2_chnl_tx_oob #( 
    output  wire    [width - 1:0]   outdata,

    output  wire                    outval

);

parameter   [3:0]   SATA_BURST_SEQ_LEN = 4'b0101;

parameter           SATA_CPLL_CFG = "VCO_3000MHZ";

//parameter   [3:0]   SATA_BURST_SEQ_LEN = 4'b0101;

//parameter           SATA_CPLL_CFG = "VCO_3000MHZ";



localparam  burst_len_mult  = SATA_CPLL_CFG == "VCO_3000MHZ" ? 2 // assuming each usrclk cycle == 20 sata serial clk cycles

                            : SATA_CPLL_CFG == "VCO_1500MHZ" ? 4
@@ -1140,6 +1142,7 @@ wire [internal_data_width - 1:0] oob_data; 
wire                                oob_val;



assign  oob_active = oob_val;



gtxe2_chnl_tx_oob #(

    .width              (internal_data_width),

    .SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),