implemented optional skipping/fast forward of the data blocks when buffer is...

                  (window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},

                  start64, lo_addr64, size64, $time);

        mode=   func_encode_mode_scanline(

                    1'b0, // skip_too_late

                    disable_need,

                    repetitive,

                    single,

            end

        endcase

        mode=   func_encode_mode_scanline(

                    1'b0, // skip_too_late

                    disable_need,

                    repetitive,

                    single,

            end

        endcase

        mode=   func_encode_mode_scanline(

                    1'b0, // skip_too_late

                    disable_need,

                    repetitive,

                    single,

            end

        endcase

        mode=   func_encode_mode_tiled(

                    1'b0, // skip_too_late

                    disable_need,

                    repetitive,

                    single,

            end

        endcase

        mode=   func_encode_mode_tiled(

                    1'b0, // skip_too_late

                    disable_need,

                    repetitive,

                    single,

    parameter MCONTR_LINTILE_SINGLE =              9, // read/write a single page 

    parameter MCONTR_LINTILE_REPEAT =             10,  // read/write pages until disabled

    parameter MCONTR_LINTILE_DIS_NEED =           11,   // disable 'need' request 

    parameter MCONTR_LINTILE_SKIP_LATE =          12,  // skip actual R/W operation when it is too late, advance pointers

// Channel test module parameters

    parameter MCNTRL_TEST01_ADDR=                 'h0f0,

//`endif    

    parameter SENS_PHASE_WIDTH=          8,      // number of bits for te phase counter (depends on divisors)

    parameter SENS_PCLK_PERIOD =         10.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps

//    parameter SENS_PCLK_PERIOD =         10.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps

    parameter SENS_BANDWIDTH =           "OPTIMIZED",  //"OPTIMIZED", "HIGH","LOW"

    // parameters for the sensor-synchronous clock PLL

    parameter MCONTR_LINTILE_RST_FRAME =     8, // reset frame number 

    parameter MCONTR_LINTILE_SINGLE =        9, // read/write a single page 

    parameter MCONTR_LINTILE_REPEAT =       10,  // read/write pages until disabled 

    parameter MCONTR_LINTILE_DIS_NEED =     11   // disable 'need' request 

    parameter MCONTR_LINTILE_DIS_NEED =     11,   // disable 'need' request 

    parameter MCONTR_LINTILE_SKIP_LATE =    12  // skip actual R/W operation when it is too late, advance pointers

    ) (

    input                        rst_in,

    wire        want_rq0;

    wire        need_rq0;

    wire        channel_pgm_en0;

    wire        reject0 = 1'b0; 

    wire  [9:0] seq_data0; // only 10 bits used

//    wire        seq_wr0; // not used

    wire        seq_set0;

    wire        want_rq1;

    wire        need_rq1;

    wire        channel_pgm_en1; 

    wire        reject1; // = 1'b0; 

    wire        seq_done1;

// routed outside to membredge module    

/*

    wire        want_rq2;

    wire        need_rq2;

    wire        channel_pgm_en2; 

    wire        reject2 = 1'b0; 

    wire        seq_done2;

    wire        buf_wr_chn2;

    wire        buf_wpage_nxt_chn2;

    wire        want_rq3;

    wire        need_rq3;

    wire        channel_pgm_en3; 

    wire        reject3; // = 1'b0; 

    wire        seq_done3;

    wire        buf_wr_chn3;

    wire        buf_wpage_nxt_chn3;

    wire        want_rq4;

    wire        need_rq4;

    wire        channel_pgm_en4;

    wire        reject4 = 1'b0; 

    wire        seq_done4;

    wire        buf_wr_chn4;

    wire        buf_wpage_nxt_chn4;

    wire                   [3:0] cmprs_need;

    wire                   [3:0] sens_channel_pgm_en;

    wire                   [3:0] sens_reject; 

    wire                   [3:0] sens_start_wr;

    wire                  [11:0] sens_bank;   // output[2:0] 

    wire  [4*ADDRESS_NUMBER-1:0] sens_row;    // output[14:0] 

    wire                   [3:0] sens_seq_done; // input : sequence over

    wire                   [3:0] cmprs_channel_pgm_en;

    wire                   [3:0] cmprs_reject = 4'h0; 

    wire                   [3:0] cmprs_start_rd16;

    wire                   [3:0] cmprs_start_rd32;

    wire                  [11:0] cmprs_bank;   // output[2:0] 

                .MCONTR_LINTILE_RST_FRAME          (MCONTR_LINTILE_RST_FRAME),

                .MCONTR_LINTILE_SINGLE             (MCONTR_LINTILE_SINGLE),

                .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT),

                .MCONTR_LINTILE_DIS_NEED           (MCONTR_LINTILE_DIS_NEED) 

                .MCONTR_LINTILE_DIS_NEED           (MCONTR_LINTILE_DIS_NEED),

                .MCONTR_LINTILE_SKIP_LATE          (MCONTR_LINTILE_SKIP_LATE) 

            ) mcntrl_linear_wr_sensor_i (

                .mrst             (mrst),                       // input

                .mclk             (mclk),                       // input

                .xfer_want        (sens_want[i]),               // output

                .xfer_need        (sens_need[i]),               // output

                .xfer_grant       (sens_channel_pgm_en[i]),     // input

                .xfer_reject      (sens_reject[i]),             // output

                .xfer_start_rd    (),                           // output

                .xfer_start_wr    (sens_start_wr[i]),           // output

                .xfer_bank        (sens_bank[3 * i +: 3]),      // output[2:0] 

        .MCONTR_LINTILE_RST_FRAME          (MCONTR_LINTILE_RST_FRAME),

        .MCONTR_LINTILE_SINGLE             (MCONTR_LINTILE_SINGLE),

        .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT),

        .MCONTR_LINTILE_DIS_NEED           (MCONTR_LINTILE_DIS_NEED) 

        .MCONTR_LINTILE_DIS_NEED           (MCONTR_LINTILE_DIS_NEED),

        .MCONTR_LINTILE_SKIP_LATE          (MCONTR_LINTILE_SKIP_LATE) 

    ) mcntrl_linear_rw_chn1_i (

        .mrst             (mrst), // input

        .mclk             (mclk), // input

        .xfer_want        (want_rq1), // output

        .xfer_need        (need_rq1), // output

        .xfer_grant       (channel_pgm_en1), // input

        .xfer_reject      (reject1),              //input

        .xfer_start_rd    (lin_rw_chn1_start_rd), // output

        .xfer_start_wr    (lin_rw_chn1_start_wr), // output

        .xfer_bank        (lin_rw_chn1_bank), // output[2:0] 

        .MCONTR_LINTILE_RST_FRAME          (MCONTR_LINTILE_RST_FRAME),

        .MCONTR_LINTILE_SINGLE             (MCONTR_LINTILE_SINGLE),

        .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT),

        .MCONTR_LINTILE_DIS_NEED           (MCONTR_LINTILE_DIS_NEED) 

        .MCONTR_LINTILE_DIS_NEED           (MCONTR_LINTILE_DIS_NEED),

        .MCONTR_LINTILE_SKIP_LATE          (MCONTR_LINTILE_SKIP_LATE) 

    ) mcntrl_linear_rw_chn3_i (

        .mrst             (mrst), // input

        .mclk             (mclk), // input

        .xfer_want        (want_rq3), // output

        .xfer_need        (need_rq3), // output

        .xfer_grant       (channel_pgm_en3), // input

        .xfer_reject      (reject3),              //input

        .xfer_start_rd    (lin_rw_chn3_start_rd), // output

        .xfer_start_wr    (lin_rw_chn3_start_wr), // output

        .xfer_bank        (lin_rw_chn3_bank), // output[2:0] 

        .MCONTR_LINTILE_SINGLE         (MCONTR_LINTILE_SINGLE),

        .MCONTR_LINTILE_REPEAT         (MCONTR_LINTILE_REPEAT),

        .MCONTR_LINTILE_DIS_NEED       (MCONTR_LINTILE_DIS_NEED)

    ) mcntrl_tiled_rw_chn4_i ( 

        .mrst                 (mrst),                       // input

        .mclk                 (mclk),                       // input

        .want_rq0           (want_rq0),                   // input

        .need_rq0           (need_rq0),                   // input

        .channel_pgm_en0    (channel_pgm_en0),            // output reg 

        .reject0            (reject0),                    // input

        .seq_done0          (seq_done0),                  // output

        .page_nxt_chn0      (),                           //rpage_nxt_chn0), not used

        .buf_run0           (buf_run0),                   // output

        .want_rq1           (want_rq1),                   // input

        .need_rq1           (need_rq1),                   // input

        .channel_pgm_en1    (channel_pgm_en1),            // output reg 

        .reject1            (reject1),                    // input

        .seq_done1          (seq_done1),                  // output

        .page_nxt_chn1      (page_ready_chn1),            //rpage_nxt_chn0), not used

        .buf_run1           (),                           // output

        .want_rq2           (want_rq2),                   // input

        .need_rq2           (need_rq2),                   // input

        .channel_pgm_en2    (channel_pgm_en2),            // output reg 

        .reject2            (reject2),                    // input

        .seq_done2          (seq_done2),                  // output

        .page_nxt_chn2      (page_ready_chn2),            //rpage_nxt_chn0), not used

        .buf_run2           (),                           // output //buf_run2),

        .want_rq3           (want_rq3),                   // input

        .need_rq3           (need_rq3),                   // input

        .channel_pgm_en3    (channel_pgm_en3),            // output reg 

        .reject3            (reject3),                    // input

        .seq_done3          (seq_done3),                  // output

        .page_nxt_chn3      (page_ready_chn3),            //rpage_nxt_chn0), not used

        .buf_run3           (),                           // output//buf_run3),

        .want_rq4           (want_rq4),                   // input

        .need_rq4           (need_rq4),                   // input

        .channel_pgm_en4    (channel_pgm_en4),            // output reg 

        .reject4            (reject4),                    // input

        .seq_done4          (seq_done4),                  // output

        .page_nxt_chn4      (page_ready_chn4),            //rpage_nxt_chn0), not used

        .buf_run4           (),                           // output //buf_run4),

        .want_rq8           (sens_want[0]),                // input

        .need_rq8           (sens_need[0]),                // input

        .channel_pgm_en8    (sens_channel_pgm_en[0]),      // output reg 

        .reject8            (sens_reject[0]),              // input

        .seq_done8          (sens_seq_done[0]),            // output

        .page_nxt_chn8      (),                            // output ?

        .buf_run8           (),                            // output

        .want_rq9           (sens_want[1]),                // input

        .need_rq9           (sens_need[1]),                // input

        .channel_pgm_en9    (sens_channel_pgm_en[1]),      // output reg 

        .reject9            (sens_reject[1]),              // input

        .seq_done9          (sens_seq_done[1]),            // output

        .page_nxt_chn9      (),                            // output ?

        .buf_run9           (),                            // output

        .want_rq10          (sens_want[2]),                // input

        .need_rq10          (sens_need[2]),                // input

        .channel_pgm_en10   (sens_channel_pgm_en[2]),      // output reg 

        .reject10           (sens_reject[2]),              // input

        .seq_done10         (sens_seq_done[2]),            // output

        .page_nxt_chn10     (),                            // output

        .buf_run10          (),                            // output

        .want_rq11          (sens_want[3]),                // input

        .need_rq11          (sens_need[3]),                // input

        .channel_pgm_en11   (sens_channel_pgm_en[3]),      // output reg 

        .reject11           (sens_reject[3]),              // input

        .seq_done11         (sens_seq_done[3]),            // output

        .page_nxt_chn11     (),                            // output

        .buf_run11          (),                            // output

        .want_rq12          (cmprs_want[0]),               // input

        .need_rq12          (cmprs_need[0]),               // input

        .channel_pgm_en12   (cmprs_channel_pgm_en[0]),     // output reg 

        .reject12           (cmprs_reject[0]),             // input

        .seq_done12         (cmprs_seq_done[0]),           // output

        .page_nxt_chn12     (cmprs_page_ready[0]),         // output ???

        .buf_run12          (),                            // output

        .want_rq13          (cmprs_want[1]),               // input

        .need_rq13          (cmprs_need[1]),               // input

        .channel_pgm_en13   (cmprs_channel_pgm_en[1]),     // output reg 

        .reject13           (cmprs_reject[1]),             // input

        .seq_done13         (cmprs_seq_done[1]),           // output

        .page_nxt_chn13     (cmprs_page_ready[1]),         // output ???

        .buf_run13          (),                            // output

        .want_rq14          (cmprs_want[2]),               // input

        .need_rq14          (cmprs_need[2]),               // input

        .channel_pgm_en14   (cmprs_channel_pgm_en[2]),     // output reg 

        .reject14           (cmprs_reject[2]),             // input

        .seq_done14         (cmprs_seq_done[2]),           // output

        .page_nxt_chn14     (cmprs_page_ready[2]),         // output ???

        .buf_run14          (),                            // output

        .want_rq15          (cmprs_want[3]),               // input

        .need_rq15          (cmprs_need[3]),               // input

        .channel_pgm_en15   (cmprs_channel_pgm_en[3]),     // output reg 

        .reject15           (cmprs_reject[3]),             // input

        .seq_done15         (cmprs_seq_done[3]),           // output

        .page_nxt_chn15     (cmprs_page_ready[3]),         // output ???

        .buf_run15          (),                            // output

    parameter MCONTR_LINTILE_RST_FRAME =        8, // reset frame number 

    parameter MCONTR_LINTILE_SINGLE =           9, // read/write a single page 

    parameter MCONTR_LINTILE_REPEAT =          10, // read/write pages until disabled 

    parameter MCONTR_LINTILE_DIS_NEED =        11   // disable 'need' request 

    parameter MCONTR_LINTILE_DIS_NEED =        11, // disable 'need' request 

    parameter MCONTR_LINTILE_SKIP_LATE =       12  // skip actual R/W operation when it is too late, advance pointers

)(

    input                          mrst,

    input                          mclk,

    output                         xfer_want,     // "want" data transfer

    output                         xfer_need,     // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.

    input                          xfer_grant,    // sequencer programming access granted, deassert wait/need 

    output                         xfer_reject,   // reject granted access (when skipping)

    output                         xfer_start_rd, // initiate a transfer (next cycle after xfer_grant)

    output                         xfer_start_wr, // initiate a transfer (next cycle after xfer_grant)

    output                   [2:0] xfer_bank,     // bank address

//    wire                          cmd_wrmem; //=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory

    wire                    [1:0] cmd_extra_pages; // external module needs more than 1 page

    wire                          skip_too_late;

    wire                          disable_need; // do not assert need, only want

    wire                          repeat_frames; // mode bit

    wire                          single_frame_w; // pulse

    wire                          msw_zero=  !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit

    reg                    [11:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}

    reg                    [12:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}

    reg   [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0

    reg   [NUM_RC_BURST_BITS-1:0] frame_size;       // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0

    // Set parameter registers

    always @(posedge mclk) begin

        if      (mrst)               mode_reg <= 0;

        else if (set_mode_w)         mode_reg <= cmd_data[11:0]; // 4:0]; // [4:0];

        else if (set_mode_w)         mode_reg <= cmd_data[12:0]; // 4:0]; // [4:0];

        if (mrst) single_frame_r <= 0;

        else      single_frame_r <= single_frame_w;

    assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page

    assign repeat_frames=    mode_reg[MCONTR_LINTILE_REPEAT];

    assign disable_need =    mode_reg[MCONTR_LINTILE_DIS_NEED];

    assign skip_too_late =   mode_reg[MCONTR_LINTILE_SKIP_LATE];

    assign status_data= {frame_finished_r, busy_r};     // TODO: Add second bit?

    assign pgm_param_w=      cmd_we;

    localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;

    assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;

    integer i;

    wire xfer_limited_by_mem_page;

    wire xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_xfer};

    reg  xfer_limited_by_mem_page_r;

    assign xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_xfer};

//  skipping pages that did not make it

//    reg    skip_tail; // skip end of frame if the next frame started (TBD)

// Now skip if write and >=4 or read and >=5 (read starts with 4 and may end with 4)

// Also if the next page signal is used by the source/dest of data, it should use reject pulse to advance external

// page counter 

    wire   start_skip_w = skip_too_late && want_r && (page_cntr >= 4) && !xfer_grant && (cmd_wrmem || page_cntr[0]); //&& busy_r && skip_run;

    reg    start_skip_r;

    reg    skip_run = 0;    // run "skip" - advance addresses, but no actual read/write

    reg    xfer_reject_r;

    assign xfer_reject = xfer_reject_r;

    always @(posedge mclk) begin // Handling skip/reject

        if (mrst) xfer_reject_r <= 0;

        else      xfer_reject_r <= xfer_grant && !chn_rst && skip_run;

        if (mrst) xfer_start_r <= 0;

        else      xfer_start_r <= {xfer_start_r[1:0], (xfer_grant & ~chn_rst & ~skip_run) | start_skip_r};

        if (mrst) xfer_start_rd_r <= 0;

        else      xfer_start_rd_r <=  xfer_grant && !chn_rst && !cmd_wrmem && !skip_run;

        if (mrst) xfer_start_wr_r <= 0;

        else      xfer_start_wr_r <=  xfer_grant && !chn_rst && cmd_wrmem  && !skip_run;

        if (mrst || recalc_r[PAR_MOD_LATENCY-1]) skip_run <= 0;

        else if (start_skip_w)                   skip_run <= 1;

        if (mrst) start_skip_r <= 0;

        else      start_skip_r <= start_skip_w;

    end    

/// Recalcualting just after starting request - preparing for the next one. Also happens after parameter change.

/// Should dpepend only on the parameters updated separately (curr_x, curr_y)

/// Should dppend only on the parameters updated separately (curr_x, curr_y)

    always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?

        if (recalc_r[0]) begin // cycle 1

            frame_x <= curr_x + window_x0;

        else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0;

        else if (frame_done_r)                frame_finished_r <= 1;

        if (mrst) xfer_start_r <= 0;

        else      xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};

        if (mrst) xfer_start_rd_r <= 0;

        else      xfer_start_rd_r <=  xfer_grant && !chn_rst && !cmd_wrmem;

        if (mrst) xfer_start_wr_r <= 0;

        else      xfer_start_wr_r <=  xfer_grant && !chn_rst && cmd_wrmem;

        if (mrst || disable_need)                         need_r <= 0;

        else if (chn_rst || xfer_grant)                   need_r <= 0;