Loading .eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +9 −0 Original line number Original line Diff line number Diff line FPGA_project_0_SimulationTopFile=x393_testbench03.tf FPGA_project_1_SimulationTopModule=x393_testbench03 FPGA_project_2_DUTTopFile=cocotb/x393_dut.v FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_3_DUTTopModule=x393_dut FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_5_part=xc7z030fbg484-1 com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@-> eclipse.preferences.version=1 .eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs 0 → 100644 +4 −0 Original line number Original line Diff line number Diff line ISExst_170_constraints=ddrc_test01.xcf ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@-> com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@-> eclipse.preferences.version=1 .eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs 0 → 100644 +8 −0 Original line number Original line Diff line number Diff line VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@-> VivadoBitstream_105_force=true VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_124_force=true VivadoBitstream_124_rawfile=x393_hispi com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@-> eclipse.preferences.version=1 .eclipse_project_setup/.settings/com.elphel.vdt.VivadoOpt.prefs 0 → 100644 +4 −0 Original line number Original line Diff line number Diff line VivadoOpt_123_SkipSnapshotOpt=true VivadoOpt_124_SkipSnapshotOpt=true com.elphel.store.context.VivadoOpt=VivadoOpt_123_SkipSnapshotOpt<-@\#\#@->VivadoOpt_124_SkipSnapshotOpt<-@\#\#@-> eclipse.preferences.version=1 .eclipse_project_setup/.settings/com.elphel.vdt.VivadoOptPhys.prefs 0 → 100644 +4 −0 Original line number Original line Diff line number Diff line VivadoOptPhys_123_SkipSnapshotOptPhys=true VivadoOptPhys_124_SkipSnapshotOptPhys=true com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_123_SkipSnapshotOptPhys<-@\#\#@->VivadoOptPhys_124_SkipSnapshotOptPhys<-@\#\#@-> eclipse.preferences.version=1 Loading
.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +9 −0 Original line number Original line Diff line number Diff line FPGA_project_0_SimulationTopFile=x393_testbench03.tf FPGA_project_1_SimulationTopModule=x393_testbench03 FPGA_project_2_DUTTopFile=cocotb/x393_dut.v FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_3_DUTTopModule=x393_dut FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_5_part=xc7z030fbg484-1 com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@-> eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs 0 → 100644 +4 −0 Original line number Original line Diff line number Diff line ISExst_170_constraints=ddrc_test01.xcf ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@-> com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@-> eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs 0 → 100644 +8 −0 Original line number Original line Diff line number Diff line VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@-> VivadoBitstream_105_force=true VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_124_force=true VivadoBitstream_124_rawfile=x393_hispi com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@-> eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOpt.prefs 0 → 100644 +4 −0 Original line number Original line Diff line number Diff line VivadoOpt_123_SkipSnapshotOpt=true VivadoOpt_124_SkipSnapshotOpt=true com.elphel.store.context.VivadoOpt=VivadoOpt_123_SkipSnapshotOpt<-@\#\#@->VivadoOpt_124_SkipSnapshotOpt<-@\#\#@-> eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOptPhys.prefs 0 → 100644 +4 −0 Original line number Original line Diff line number Diff line VivadoOptPhys_123_SkipSnapshotOptPhys=true VivadoOptPhys_124_SkipSnapshotOptPhys=true com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_123_SkipSnapshotOptPhys<-@\#\#@->VivadoOptPhys_124_SkipSnapshotOptPhys<-@\#\#@-> eclipse.preferences.version=1