Loading .project +8 −8 Original line number Original line Diff line number Diff line Loading @@ -62,42 +62,42 @@ <link> <link> <name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151115000630414.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151115150613168.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> Loading fpga_version.vh +2 −1 Original line number Original line Diff line number Diff line Loading @@ -31,7 +31,8 @@ * contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it * with at least one of the Free Software programs. * with at least one of the Free Software programs. *******************************************************************************/ *******************************************************************************/ parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %) parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%) // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %) // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%) // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%) // parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023 // parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023 // parameter FPGA_VERSION = 32'h0393006d; // -1 with lane switch - does not work // parameter FPGA_VERSION = 32'h0393006d; // -1 with lane switch - does not work Loading includes/x393_parameters.vh +4 −1 Original line number Original line Diff line number Diff line Loading @@ -598,7 +598,10 @@ parameter HISPI_MMCM1 = "FALSE", parameter HISPI_MMCM1 = "FALSE", parameter HISPI_MMCM2 = "TRUE", parameter HISPI_MMCM2 = "TRUE", parameter HISPI_MMCM3 = "FALSE", parameter HISPI_MMCM3 = "FALSE", parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot) parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane parameter HISPI_FIFO_DEPTH = 4, parameter HISPI_FIFO_START = 7, parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE", parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE", parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE", Loading py393/dbg/x393_mcntrl.pickle +59523 −59772 File changed.Preview size limit exceeded, changes collapsed. Show changes py393/x393_jpeg.py +6 −0 Original line number Original line Diff line number Diff line Loading @@ -857,6 +857,8 @@ write_sensor_i2c 0 1 0 0x30700002 #test pattern - fading color bars #test pattern - fading color bars write_sensor_i2c 0 1 0 0x30700003 write_sensor_i2c 0 1 0 0x30700003 print_sensor_i2c 0 0x3070 0xff 0x10 0 print_sensor_i2c 0 0x3070 0xff 0x10 0 #test - running 8, 8-bit write_sensor_i2c 0 1 0 0x30700101 #Exposure 0x800 lines #Exposure 0x800 lines write_sensor_i2c 0 1 0 0x30120800 write_sensor_i2c 0 1 0 0x30120800 Loading @@ -878,6 +880,10 @@ print_sensor_i2c 0 0x31c6 0xff 0x10 0 compressor_control 0 2 compressor_control 0 2 jpeg_write "img.jpeg" 0 jpeg_write "img.jpeg" 0 #setup JP4 setup_compressor 0 5 2 0 1 1 0 0 None None None None 1 384 364 2 #setup JPEG setup_compressor 0 0 2 0 1 1 0 0 None None None None 1 384 364 2 #default gain = 0xa, set red and blue (outdoors) #default gain = 0xa, set red and blue (outdoors) write_sensor_i2c 0 1 0 0x30280014 write_sensor_i2c 0 1 0 0x30280014 Loading Loading
.project +8 −8 Original line number Original line Diff line number Diff line Loading @@ -62,42 +62,42 @@ <link> <link> <name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151115000630414.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151115150613168.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151115001220264.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151115151104872.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> Loading
fpga_version.vh +2 −1 Original line number Original line Diff line number Diff line Loading @@ -31,7 +31,8 @@ * contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it * with at least one of the Free Software programs. * with at least one of the Free Software programs. *******************************************************************************/ *******************************************************************************/ parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %) parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%) // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %) // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%) // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%) // parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023 // parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023 // parameter FPGA_VERSION = 32'h0393006d; // -1 with lane switch - does not work // parameter FPGA_VERSION = 32'h0393006d; // -1 with lane switch - does not work Loading
includes/x393_parameters.vh +4 −1 Original line number Original line Diff line number Diff line Loading @@ -598,7 +598,10 @@ parameter HISPI_MMCM1 = "FALSE", parameter HISPI_MMCM1 = "FALSE", parameter HISPI_MMCM2 = "TRUE", parameter HISPI_MMCM2 = "TRUE", parameter HISPI_MMCM3 = "FALSE", parameter HISPI_MMCM3 = "FALSE", parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot) parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane parameter HISPI_FIFO_DEPTH = 4, parameter HISPI_FIFO_START = 7, parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE", parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE", parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE", Loading
py393/dbg/x393_mcntrl.pickle +59523 −59772 File changed.Preview size limit exceeded, changes collapsed. Show changes
py393/x393_jpeg.py +6 −0 Original line number Original line Diff line number Diff line Loading @@ -857,6 +857,8 @@ write_sensor_i2c 0 1 0 0x30700002 #test pattern - fading color bars #test pattern - fading color bars write_sensor_i2c 0 1 0 0x30700003 write_sensor_i2c 0 1 0 0x30700003 print_sensor_i2c 0 0x3070 0xff 0x10 0 print_sensor_i2c 0 0x3070 0xff 0x10 0 #test - running 8, 8-bit write_sensor_i2c 0 1 0 0x30700101 #Exposure 0x800 lines #Exposure 0x800 lines write_sensor_i2c 0 1 0 0x30120800 write_sensor_i2c 0 1 0 0x30120800 Loading @@ -878,6 +880,10 @@ print_sensor_i2c 0 0x31c6 0xff 0x10 0 compressor_control 0 2 compressor_control 0 2 jpeg_write "img.jpeg" 0 jpeg_write "img.jpeg" 0 #setup JP4 setup_compressor 0 5 2 0 1 1 0 0 None None None None 1 384 364 2 #setup JPEG setup_compressor 0 0 2 0 1 1 0 0 None None None None 1 384 364 2 #default gain = 0xa, set red and blue (outdoors) #default gain = 0xa, set red and blue (outdoors) write_sensor_i2c 0 1 0 0x30280014 write_sensor_i2c 0 1 0 0x30280014 Loading