removed accidental directory

eclipse_settings/.project

-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>x393</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.python.pydev.PyDevBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>com.elphel.vdt.veditor.HdlNature</nature>
-		<nature>org.python.pydev.pythonNature</nature>
-	</natures>
-</projectDescription>

eclipse_settings/.project_dct

-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>x393_dct</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.python.pydev.PyDevBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>com.elphel.vdt.veditor.HdlNature</nature>
-		<nature>org.python.pydev.pythonNature</nature>
-	</natures>
-</projectDescription>

eclipse_settings/.settings/com.elphel.vdt.FPGA_project.prefs

-FPGA_project_@_DUTTopFile=cocotb/x393_dut.v
-FPGA_project_@_DUTTopModule=x393_dut
-FPGA_project_@_ImplementationTopFile=x393.v
-FPGA_project_@_SimulationTopFile=x393_testbench03.tf
-FPGA_project_@_SimulationTopModule=x393_testbench03
-FPGA_project_@_part=xc7z030fbg484-2
-com.elphel.store.context.FPGA_project=FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_part<-@\#\#@->FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->
-com.elphel.store.version.FPGA_project=1.0
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.FPGA_project_old.prefs

-FPGA_project_@_DUTTopFile=cocotb/x393_dut.v
-FPGA_project_@_DUTTopModule=x393_dut
-FPGA_project_@_ImplementationTopFile=x393.v
-FPGA_project_@_SimulationTopFile=x393_testbench03.tf
-FPGA_project_@_SimulationTopModule=x393_testbench03
-FPGA_project_@_part=xc7z030fbg484-1
-com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
-com.elphel.store.version.FPGA_project=1.0
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.ISExst.prefs

-ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
-ISExst_@_constraints=ddrc_test01.xcf
-com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoBitstream.prefs

-VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
-VivadoBitstream_@_force=true
-VivadoBitstream_@_rawfile=x393_parallel
-com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoOpt.prefs

-VivadoOpt_@_SkipSnapshotOpt=true
-com.elphel.store.context.VivadoOpt=VivadoOpt_@_SkipSnapshotOpt<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoOptPhys.prefs

-VivadoOptPhys_@_SkipSnapshotOptPhys=true
-com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_@_SkipSnapshotOptPhys<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoOptPower.prefs

-VivadoOptPower_@_SkipSnapshotOptPower=true
-com.elphel.store.context.VivadoOptPower=VivadoOptPower_@_SkipSnapshotOptPower<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoPlace.prefs

-VivadoPlace_@_SkipSnapshotPlace=true
-VivadoPlace_@_verbose_place=true
-com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->VivadoPlace_@_SkipSnapshotPlace<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoRoute.prefs

-VivadoRoute_@_SkipSnapshotRoute=true
-VivadoRoute_@_directive_route=MoreGlobalIterations
-com.elphel.store.context.VivadoRoute=VivadoRoute_@_SkipSnapshotRoute<-@\#\#@->VivadoRoute_@_directive_route<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoSynthesis.prefs

-VivadoSynthesis_@_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@->
-VivadoSynthesis_@_MaxMsg=20000
-VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
-VivadoSynthesis_@_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@->
-VivadoSynthesis_@_ResetProject=true
-VivadoSynthesis_@_ShowInfo=true
-VivadoSynthesis_@_parser_mode=1
-VivadoSynthesis_@_verbose=true
-com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_PreTCL<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_ResetProject<-@\#\#@->
-com.elphel.store.version.VivadoSynthesis=1.1
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs

-VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
-com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs

-VivadoTimingReportImplemented_@_DisableVivadoTiming=true
-VivadoTimingReportImplemented_@_rawfile=
-com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_@_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_@_rawfile<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs

-VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
-com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.cocotb.prefs

-cocotb_@_COCOTB_DEBUG=false
-cocotb_@_CocotbDutTopFile=cocotb/x393_dut.v
-cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
-cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
-cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->
-cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
-cocotb_@_GTKWaveSavFile=x393_cocotb_03.sav
-cocotb_@_GrepFindErr=error|ERROR
-cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING
-cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)
-cocotb_@_SaveLogsPreprocessor=true
-cocotb_@_SaveLogsSimulator=true
-com.elphel.store.context.cocotb=cocotb_@_CocotbExtraFiles<-@\#\#@->cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_CocotbDutTopFile<-@\#\#@->cocotb_@_CocotbTESTCASE<-@\#\#@->cocotb_@_GrepFindErrWarn<-@\#\#@->cocotb_@_SaveLogsPreprocessor<-@\#\#@->cocotb_@_SaveLogsSimulator<-@\#\#@->cocotb_@_GrepFindErr<-@\#\#@->cocotb_@_PatternInfo<-@\#\#@->cocotb_@_COCOTB_DEBUG<-@\#\#@->
-com.elphel.store.version.cocotb=0.8
-eclipse.preferences.version=1

eclipse_settings/.settings/com.elphel.vdt.iverilog.prefs

-com.elphel.store.context.iverilog=iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_ShowWarnings<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->
-com.elphel.store.version.iverilog=1.1
-eclipse.preferences.version=1
-iverilog_@_ExtraFiles=glbl.v<-@\#\#@->
-iverilog_@_GTKWaveSavFile=x393_testbench04.sav
-iverilog_@_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
-iverilog_@_SaveLogsPreprocessor=false
-iverilog_@_SaveLogsSimulator=true
-iverilog_@_ShowNoProblem=true
-iverilog_@_ShowWarnings=false
-iverilog_@_TopModulesOther=glbl<-@\#\#@->

eclipse_settings/.settings/com.elphel.vdt.prefs

-com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
-com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
-eclipse.preferences.version=1

eclipse_settings/.settings/org.eclipse.core.resources.prefs

-eclipse.preferences.version=1
-encoding//attic/gen_hist_test.py=utf-8
-encoding//helpers/convert_data_to_params.py=utf-8
-encoding//helpers/convert_pass_init_params.py=utf-8
-encoding//helpers/convert_zigzag_rom.py=utf-8
-encoding//py393/test_mcntrl.py=utf-8
-encoding//py393/x393_i2c.py.test=utf-8
-encoding//py393/x393_init_usb_hub.py=utf-8