Commit 0fc224f6 authored by Andrey Filippov's avatar Andrey Filippov

fixed timing measurement with the same start/end signal. v.03930102

parent c1295294
...@@ -36,7 +36,8 @@ ...@@ -36,7 +36,8 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h03930101; // serial - 17.4 - disabling SOF when setting interface parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix
// parameter FPGA_VERSION = 32'h03930101; // serial - 17.4 - disabling SOF when setting interface - met
// parameter FPGA_VERSION = 32'h03930100; // serial - 17.4 - disabling SOF when setting interface timing OK // parameter FPGA_VERSION = 32'h03930100; // serial - 17.4 - disabling SOF when setting interface timing OK
// parameter FPGA_VERSION = 32'h039300ff; // serial - 15.3 - same, suspected bitstream problems // parameter FPGA_VERSION = 32'h039300ff; // serial - 15.3 - same, suspected bitstream problems
// parameter FPGA_VERSION = 32'h039300fe; // serial - 17.4 - same, suspected bitstream problems no timing errors // parameter FPGA_VERSION = 32'h039300fe; // serial - 17.4 - same, suspected bitstream problems no timing errors
......
...@@ -174,7 +174,7 @@ module sens_hispi12l4#( ...@@ -174,7 +174,7 @@ module sens_hispi12l4#(
else if (tim_ibusy[0] && tim_f) tim_ibusy <= 2; else if (tim_ibusy[0] && tim_f) tim_ibusy <= 2;
else if (tim_ibusy[1] && tim_t) tim_ibusy <= 0; else if (tim_ibusy[1] && tim_t) tim_ibusy <= 0;
if (tim_ibusy[0] || tim_f) tim_icntr <= 0; // reset if repeated start (e.g. to measure last sol to eof) if (tim_ibusy[0] || (tim_f && !tim_t)) tim_icntr <= 0; // reset if repeated start (e.g. to measure last sol to eof)
else if (tim_ibusy[1]) tim_icntr <= tim_icntr + 1; else if (tim_ibusy[1]) tim_icntr <= tim_icntr + 1;
end end
always @ (posedge mclk) begin always @ (posedge mclk) begin
......
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