Loading simulation_modules/simul_sensor_spi.v +3 −3 Original line number Original line Diff line number Diff line Loading @@ -62,7 +62,7 @@ reg [7:0] reg_wr; assign pin_spi_out=spi_out; assign pin_spi_out=spi_out; assign clk = pin_spi_clk; assign clk = pin_spi_clk; assign reset = !pin_spi_reset || !pin_spi_en; assign reset = !pin_spi_reset || !pin_spi_en; //todo: asinchronous `ifndef ROOTPATH `ifndef ROOTPATH `include "IVERILOG_INCLUDE.v"// SuppressThisWarning VEditor - maybe not used `include "IVERILOG_INCLUDE.v"// SuppressThisWarning VEditor - maybe not used Loading Loading @@ -97,7 +97,7 @@ end `define S_FST_RD_A0 8'h03 `define S_FST_RD_A0 8'h03 `define S_FST_RD_D0 8'h04 `define S_FST_RD_D0 8'h04 always @ ( posedge clk ) begin always @ ( posedge clk or posedge reset ) begin if ( reset ) begin if ( reset ) begin sfst <= `S_FST_00000; sfst <= `S_FST_00000; reg_addr[6:0] <= 0; reg_addr[6:0] <= 0; Loading Loading @@ -150,7 +150,7 @@ end else begin end //if end //if end //always end //always always @ ( negedge clk ) begin always @ ( negedge clk or posedge reset ) begin if ( reset ) begin if ( reset ) begin spi_out <= 1'b0; spi_out <= 1'b0; end else begin end else begin Loading Loading
simulation_modules/simul_sensor_spi.v +3 −3 Original line number Original line Diff line number Diff line Loading @@ -62,7 +62,7 @@ reg [7:0] reg_wr; assign pin_spi_out=spi_out; assign pin_spi_out=spi_out; assign clk = pin_spi_clk; assign clk = pin_spi_clk; assign reset = !pin_spi_reset || !pin_spi_en; assign reset = !pin_spi_reset || !pin_spi_en; //todo: asinchronous `ifndef ROOTPATH `ifndef ROOTPATH `include "IVERILOG_INCLUDE.v"// SuppressThisWarning VEditor - maybe not used `include "IVERILOG_INCLUDE.v"// SuppressThisWarning VEditor - maybe not used Loading Loading @@ -97,7 +97,7 @@ end `define S_FST_RD_A0 8'h03 `define S_FST_RD_A0 8'h03 `define S_FST_RD_D0 8'h04 `define S_FST_RD_D0 8'h04 always @ ( posedge clk ) begin always @ ( posedge clk or posedge reset ) begin if ( reset ) begin if ( reset ) begin sfst <= `S_FST_00000; sfst <= `S_FST_00000; reg_addr[6:0] <= 0; reg_addr[6:0] <= 0; Loading Loading @@ -150,7 +150,7 @@ end else begin end //if end //if end //always end //always always @ ( negedge clk ) begin always @ ( negedge clk or posedge reset ) begin if ( reset ) begin if ( reset ) begin spi_out <= 1'b0; spi_out <= 1'b0; end else begin end else begin Loading
