Commit 0524b747 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

continue fighting with Vivado tools

parent f026775f

.project

+15 −15
Original line number Diff line number Diff line
@@ -62,77 +62,77 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150609094851488.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150720120920435.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150609094851488.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150720115714081.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150609094851488.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150720120920435.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150609094851488.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150720115714081.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150609094851488.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150720115714081.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150609094851488.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150720120920435.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150719200102645.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150720113641113.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150609094851488.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150720120920435.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150719200102645.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150720113641113.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150609094851488.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150720120920435.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150719200102645.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150720113641113.log</location>

		</link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150609094851488.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150720120920435.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-place.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-place-20150609094851488.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-place-20150720115714081.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-route.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-route-20150609094851488.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-route-20150720120920435.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150719200102645.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150720113641113.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

includes/x393_parameters.vh

+9 −3
Original line number Diff line number Diff line
@@ -415,9 +415,13 @@ 
    parameter integer IDELAY_VALUE =     0,

    parameter integer PXD_DRIVE =        12,

    parameter PXD_IBUF_LOW_PWR =         "TRUE",

    parameter PXD_IOSTANDARD =           "LVCMOS33",

    parameter PXD_IOSTANDARD =           "LVCMOS25",

    parameter PXD_SLEW =                 "SLOW",

    parameter real SENS_REFCLK_FREQUENCY = 300.0,

`ifdef use200Mhz

    parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY

`else

    parameter real SENS_REFCLK_FREQUENCY = 200.0,

`endif    

    parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",

    

    parameter SENS_PHASE_WIDTH=          8,      // number of bits for te phase counter (depends on divisors)
@@ -429,6 +433,8 @@ 
    parameter IPCLK_PHASE =              0.000,

    parameter IPCLK2X_PHASE =            0.000,



    parameter BUF_IPCLK =                "BUFG", // "BUFR",

    parameter BUF_IPCLK2X =              "BUFG", // "BUFR",  



    parameter SENS_DIVCLK_DIVIDE =       1,            // Integer 1..106. Divides all outputs with respect to CLKIN

    parameter SENS_REF_JITTER1   =       0.010,        // Expectet jitter on CLKIN1 (0.000..0.999)

sensor/pxd_clock.v

+17 −1
Original line number Diff line number Diff line
@@ -54,7 +54,8 @@ module pxd_clock #( 
        .I     (pxclk_out), // input

        .T     (!pxclk_en) // input

    );



/*

//finedelay not supported by HR banks?

    idelay_fine_pipe # (

        .IODELAY_GRP           (IODELAY_GRP),

        .DELAY_VALUE           (IDELAY_VALUE),
@@ -69,6 +70,21 @@ module pxd_clock #( 
        .data_in      (pxclk_iobuf),

        .data_out     (pxclk_in)

    );

*/

    idelay_nofine # (

        .IODELAY_GRP           (IODELAY_GRP),

        .DELAY_VALUE           (IDELAY_VALUE),

        .REFCLK_FREQUENCY      (REFCLK_FREQUENCY),

        .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)

    ) pxclk_dly_i(

        .clk          (mclk),

        .rst          (rst),

        .set          (set_idelay),

        .ld           (ld_idelay),

        .delay        (dly_data[7:3]),

        .data_in      (pxclk_iobuf),

        .data_out     (pxclk_in)

    );





endmodule

sensor/pxd_single.v

+18 −0
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ module pxd_single#( 
        .T     (!pxd_en) // input

    );



/*

//finedelay not supported by HR banks?

    idelay_fine_pipe # (

        .IODELAY_GRP           (IODELAY_GRP),

        .DELAY_VALUE           (IDELAY_VALUE),
@@ -84,6 +86,22 @@ module pxd_single#( 
        .data_out     (pxd_delayed)

    );

    

 */

    idelay_nofine # (

        .IODELAY_GRP           (IODELAY_GRP),

        .DELAY_VALUE           (IDELAY_VALUE),

        .REFCLK_FREQUENCY      (REFCLK_FREQUENCY),

        .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)

    ) pxd_dly_i(

        .clk          (mclk),

        .rst          (rst),

        .set          (set_idelay),

        .ld           (ld_idelay),

        .delay        (dly_data[7:3]),

        .data_in      (pxd_iobuf),

        .data_out     (pxd_delayed)

    );

    

    iserdes_mem #(

        .DYN_CLKDIV_INV_EN("FALSE")

    ) iserdes_pxd_i (

sensor/sens_parallel12.v

+21 −2
Original line number Diff line number Diff line
@@ -63,6 +63,8 @@ module sens_parallel12 #( 
    parameter CLKFBOUT_PHASE_SENSOR =  0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)

    parameter IPCLK_PHASE =            0.000,

    parameter IPCLK2X_PHASE =          0.000,

    parameter BUF_IPCLK =             "BUFR",

    parameter BUF_IPCLK2X =           "BUFR",  

    



    parameter SENS_DIVCLK_DIVIDE =     1,            // Integer 1..106. Divides all outputs with respect to CLKIN
@@ -622,9 +624,26 @@ module sens_parallel12 #( 
        .clkfb_stopped       (clkfb_pxd_stopped_mmcm) // output

         // output

    );

    generate

        if      (BUF_IPCLK == "BUFG")  BUFG  clk1x_i (.O(ipclk),   .I(ipclk_pre));

        else if (BUF_IPCLK == "BUFH")  BUFH  clk1x_i (.O(ipclk),   .I(ipclk_pre));

        else if (BUF_IPCLK == "BUFR")  BUFR  clk1x_i (.O(ipclk),   .I(ipclk_pre), .CE(1'b1), .CLR(rst));

        else if (BUF_IPCLK == "BUFMR") BUFMR clk1x_i (.O(ipclk),   .I(ipclk_pre));

        else if (BUF_IPCLK == "BUFIO") BUFIO clk1x_i (.O(ipclk),   .I(ipclk_pre));

        else assign ipclk = ipclk_pre;

    endgenerate



    generate

        if      (BUF_IPCLK2X == "BUFG")  BUFG  clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));

        else if (BUF_IPCLK2X == "BUFH")  BUFH  clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));

        else if (BUF_IPCLK2X == "BUFR")  BUFR  clk2x_i (.O(ipclk2x), .I(ipclk2x_pre), .CE(1'b1), .CLR(rst));

        else if (BUF_IPCLK2X == "BUFMR") BUFMR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));

        else if (BUF_IPCLK2X == "BUFIO") BUFIO clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));

        else assign ipclk2x = ipclk2x_pre;

    endgenerate



BUFR ipclk_bufr_i   (.O(ipclk),   .CE(), .CLR(), .I(ipclk_pre));

BUFR ipclk2x_bufr_i (.O(ipclk2x), .CE(), .CLR(), .I(ipclk2x_pre));

// BUFR ipclk_bufr_i   (.O(ipclk),   .CE(), .CLR(), .I(ipclk_pre));

// BUFR ipclk2x_bufr_i (.O(ipclk2x), .CE(), .CLR(), .I(ipclk2x_pre));





endmodule