diff --git a/.project b/.project
index 66be267eb29287cff07203a51b273df56bc6b96f..3b1ed8d11fea050f177dd2ef80c89047ff7656da 100644
--- a/.project
+++ b/.project
@@ -62,77 +62,77 @@
vivado_logs/VivadoBitstream.log
1
- /home/andrey/git/x393/vivado_logs/VivadoBitstream-20150609094851488.log
+ /home/andrey/git/x393/vivado_logs/VivadoBitstream-20150720120920435.log
vivado_logs/VivadoOpt.log
1
- /home/andrey/git/x393/vivado_logs/VivadoOpt-20150609094851488.log
+ /home/andrey/git/x393/vivado_logs/VivadoOpt-20150720115714081.log
vivado_logs/VivadoOptPhys.log
1
- /home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150609094851488.log
+ /home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150720120920435.log
vivado_logs/VivadoOptPower.log
1
- /home/andrey/git/x393/vivado_logs/VivadoOptPower-20150609094851488.log
+ /home/andrey/git/x393/vivado_logs/VivadoOptPower-20150720115714081.log
vivado_logs/VivadoPlace.log
1
- /home/andrey/git/x393/vivado_logs/VivadoPlace-20150609094851488.log
+ /home/andrey/git/x393/vivado_logs/VivadoPlace-20150720115714081.log
vivado_logs/VivadoRoute.log
1
- /home/andrey/git/x393/vivado_logs/VivadoRoute-20150609094851488.log
+ /home/andrey/git/x393/vivado_logs/VivadoRoute-20150720120920435.log
vivado_logs/VivadoSynthesis.log
1
- /home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150719200102645.log
+ /home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150720113641113.log
vivado_logs/VivadoTimimgSummaryReportImplemented.log
1
- /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150609094851488.log
+ /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150720120920435.log
vivado_logs/VivadoTimimgSummaryReportSynthesis.log
1
- /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150719200102645.log
+ /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150720113641113.log
vivado_logs/VivadoTimingReportImplemented.log
1
- /home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150609094851488.log
+ /home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150720120920435.log
vivado_logs/VivadoTimingReportSynthesis.log
1
- /home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150719200102645.log
+ /home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150720113641113.log
vivado_state/x393-opt-phys.dcp
1
- /home/andrey/git/x393/vivado_state/x393-opt-phys-20150609094851488.dcp
+ /home/andrey/git/x393/vivado_state/x393-opt-phys-20150720120920435.dcp
vivado_state/x393-place.dcp
1
- /home/andrey/git/x393/vivado_state/x393-place-20150609094851488.dcp
+ /home/andrey/git/x393/vivado_state/x393-place-20150720115714081.dcp
vivado_state/x393-route.dcp
1
- /home/andrey/git/x393/vivado_state/x393-route-20150609094851488.dcp
+ /home/andrey/git/x393/vivado_state/x393-route-20150720120920435.dcp
vivado_state/x393-synth.dcp
1
- /home/andrey/git/x393/vivado_state/x393-synth-20150719200102645.dcp
+ /home/andrey/git/x393/vivado_state/x393-synth-20150720113641113.dcp
diff --git a/includes/x393_parameters.vh b/includes/x393_parameters.vh
index 7eb0fc0edbf2debee78c9e9f8f3a6e3961ea50a0..400918d47681047937986a599295ac6933e151ec 100644
--- a/includes/x393_parameters.vh
+++ b/includes/x393_parameters.vh
@@ -415,9 +415,13 @@
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
- parameter PXD_IOSTANDARD = "LVCMOS33",
+ parameter PXD_IOSTANDARD = "LVCMOS25",
parameter PXD_SLEW = "SLOW",
- parameter real SENS_REFCLK_FREQUENCY = 300.0,
+`ifdef use200Mhz
+ parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY
+`else
+ parameter real SENS_REFCLK_FREQUENCY = 200.0,
+`endif
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
@@ -428,7 +432,9 @@
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
-
+
+ parameter BUF_IPCLK = "BUFG", // "BUFR",
+ parameter BUF_IPCLK2X = "BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
diff --git a/sensor/pxd_clock.v b/sensor/pxd_clock.v
index 46e8ddc4df0b00ca6bd641682c2888cc49842bfd..c7a6e40548d27ff92694394407182ce3b0b7d354 100644
--- a/sensor/pxd_clock.v
+++ b/sensor/pxd_clock.v
@@ -54,7 +54,8 @@ module pxd_clock #(
.I (pxclk_out), // input
.T (!pxclk_en) // input
);
-
+/*
+//finedelay not supported by HR banks?
idelay_fine_pipe # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
@@ -69,6 +70,21 @@ module pxd_clock #(
.data_in (pxclk_iobuf),
.data_out (pxclk_in)
);
+*/
+ idelay_nofine # (
+ .IODELAY_GRP (IODELAY_GRP),
+ .DELAY_VALUE (IDELAY_VALUE),
+ .REFCLK_FREQUENCY (REFCLK_FREQUENCY),
+ .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
+ ) pxclk_dly_i(
+ .clk (mclk),
+ .rst (rst),
+ .set (set_idelay),
+ .ld (ld_idelay),
+ .delay (dly_data[7:3]),
+ .data_in (pxclk_iobuf),
+ .data_out (pxclk_in)
+ );
endmodule
diff --git a/sensor/pxd_single.v b/sensor/pxd_single.v
index f3e6901220a2e6d6030e8c36dd67b797539e29a6..fbceefb3cbd8e1205165ad9a8c5173cbc66d2fef 100644
--- a/sensor/pxd_single.v
+++ b/sensor/pxd_single.v
@@ -69,6 +69,8 @@ module pxd_single#(
.T (!pxd_en) // input
);
+/*
+//finedelay not supported by HR banks?
idelay_fine_pipe # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
@@ -84,6 +86,22 @@ module pxd_single#(
.data_out (pxd_delayed)
);
+ */
+ idelay_nofine # (
+ .IODELAY_GRP (IODELAY_GRP),
+ .DELAY_VALUE (IDELAY_VALUE),
+ .REFCLK_FREQUENCY (REFCLK_FREQUENCY),
+ .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
+ ) pxd_dly_i(
+ .clk (mclk),
+ .rst (rst),
+ .set (set_idelay),
+ .ld (ld_idelay),
+ .delay (dly_data[7:3]),
+ .data_in (pxd_iobuf),
+ .data_out (pxd_delayed)
+ );
+
iserdes_mem #(
.DYN_CLKDIV_INV_EN("FALSE")
) iserdes_pxd_i (
diff --git a/sensor/sens_parallel12.v b/sensor/sens_parallel12.v
index 4a7d8969d50b922a75fcacc57c4306276f658597..4f9135dcee4605d3acfe77e3fedf8074aa1c052b 100644
--- a/sensor/sens_parallel12.v
+++ b/sensor/sens_parallel12.v
@@ -63,6 +63,8 @@ module sens_parallel12 #(
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
+ parameter BUF_IPCLK = "BUFR",
+ parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
@@ -622,9 +624,26 @@ module sens_parallel12 #(
.clkfb_stopped (clkfb_pxd_stopped_mmcm) // output
// output
);
+ generate
+ if (BUF_IPCLK == "BUFG") BUFG clk1x_i (.O(ipclk), .I(ipclk_pre));
+ else if (BUF_IPCLK == "BUFH") BUFH clk1x_i (.O(ipclk), .I(ipclk_pre));
+ else if (BUF_IPCLK == "BUFR") BUFR clk1x_i (.O(ipclk), .I(ipclk_pre), .CE(1'b1), .CLR(rst));
+ else if (BUF_IPCLK == "BUFMR") BUFMR clk1x_i (.O(ipclk), .I(ipclk_pre));
+ else if (BUF_IPCLK == "BUFIO") BUFIO clk1x_i (.O(ipclk), .I(ipclk_pre));
+ else assign ipclk = ipclk_pre;
+ endgenerate
+
+ generate
+ if (BUF_IPCLK2X == "BUFG") BUFG clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
+ else if (BUF_IPCLK2X == "BUFH") BUFH clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
+ else if (BUF_IPCLK2X == "BUFR") BUFR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre), .CE(1'b1), .CLR(rst));
+ else if (BUF_IPCLK2X == "BUFMR") BUFMR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
+ else if (BUF_IPCLK2X == "BUFIO") BUFIO clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
+ else assign ipclk2x = ipclk2x_pre;
+ endgenerate
-BUFR ipclk_bufr_i (.O(ipclk), .CE(), .CLR(), .I(ipclk_pre));
-BUFR ipclk2x_bufr_i (.O(ipclk2x), .CE(), .CLR(), .I(ipclk2x_pre));
+// BUFR ipclk_bufr_i (.O(ipclk), .CE(), .CLR(), .I(ipclk_pre));
+// BUFR ipclk2x_bufr_i (.O(ipclk2x), .CE(), .CLR(), .I(ipclk2x_pre));
endmodule
diff --git a/sensor/sensor_channel.v b/sensor/sensor_channel.v
index 171ff2e2e6b49e934b93e04a405239313e7dd535..92dc74192c06e1e23eecdfd217d490930620d279 100644
--- a/sensor/sensor_channel.v
+++ b/sensor/sensor_channel.v
@@ -147,7 +147,8 @@ module sensor_channel#(
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
-
+ parameter BUF_IPCLK = "BUFR",
+ parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
@@ -417,6 +418,8 @@ module sensor_channel#(
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
+ .BUF_IPCLK (BUF_IPCLK),
+ .BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
diff --git a/sensor/sensors393.v b/sensor/sensors393.v
index 5eda57014d3b9e23e8cf6e4cb0e0f1f63b539d9d..eae1f1a1ce747c35df7678005c55d96ae6e54585 100644
--- a/sensor/sensors393.v
+++ b/sensor/sensors393.v
@@ -163,6 +163,8 @@ module sensors393 #(
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
+ parameter BUF_IPCLK = "BUFR",
+ parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
@@ -271,8 +273,6 @@ module sensors393 #(
cmd_ad <= cmd_ad_in;
cmd_stb <= cmd_stb_in;
end
-// wire [3:0] sns_pg;
-// my_alias #(.WIDTH(4)) my_alias_sns_pg_i ({sns4_pg,sns3_pg,sns2_pg,sns1_pg},sns_pg);
generate
genvar i;
@@ -372,6 +372,8 @@ module sensors393 #(
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
+ .BUF_IPCLK (BUF_IPCLK),
+ .BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
@@ -547,18 +549,3 @@ module sensors393 #(
endmodule
-
-/*
-module my_alias #(
- parameter WIDTH = 1)
-(
- inout [WIDTH-1:0] a,
- inout [WIDTH-1:0] a
-);
-module my_alias #(
- parameter WIDTH = 1)
-(.A(W), .B(W));
- inout [WIDTH-1:0] W;
-
-endmodule
-*/
diff --git a/util_modules/dual_clock_source.v b/util_modules/dual_clock_source.v
index ba01e60ee9fc7e8863bd6e2e9dd90e8a8b8e05dc..a8f9875515c58bd11d847be3861c1e8ad59e7148 100644
--- a/util_modules/dual_clock_source.v
+++ b/util_modules/dual_clock_source.v
@@ -41,18 +41,23 @@ module dual_clock_source #(
);
wire clkfb, clk1x_pre, clk2x_pre;
generate
- if (BUF_CLK1X == "BUFG") BUFG clk1x_i (.O(clk1x), .I(clk1x_pre));
- else if (BUF_CLK1X == "BUFH") BUFH clk1x_i (.O(clk1x), .I(clk1x_pre));
- else if (BUF_CLK1X == "BUFR") BUFR clk1x_i (.O(clk1x), .I(clk1x_pre), .CE(1'b1), .CLR(rst));
+ if (BUF_CLK1X == "BUFG") BUFG clk1x_i (.O(clk1x), .I(clk1x_pre));
+ else if (BUF_CLK1X == "BUFH") BUFH clk1x_i (.O(clk1x), .I(clk1x_pre));
+ else if (BUF_CLK1X == "BUFR") BUFR clk1x_i (.O(clk1x), .I(clk1x_pre), .CE(1'b1), .CLR(rst));
+ else if (BUF_CLK1X == "BUFMR") BUFMR clk1x_i (.O(clk1x), .I(clk1x_pre));
+ else if (BUF_CLK1X == "BUFIO") BUFIO clk1x_i (.O(clk1x), .I(clk1x_pre));
else assign clk1x = clk1x_pre;
endgenerate
generate
- if (BUF_CLK2X == "BUFG") BUFG clk2x_i (.O(clk2x), .I(clk2x_pre));
- else if (BUF_CLK2X == "BUFH") BUFH clk2x_i (.O(clk2x), .I(clk2x_pre));
- else if (BUF_CLK2X == "BUFR") BUFR clk2x_i (.O(clk2x), .I(clk2x_pre), .CE(1'b1), .CLR(rst));
+ if (BUF_CLK2X == "BUFG") BUFG clk2x_i (.O(clk2x), .I(clk2x_pre));
+ else if (BUF_CLK2X == "BUFH") BUFH clk2x_i (.O(clk2x), .I(clk2x_pre));
+ else if (BUF_CLK2X == "BUFR") BUFR clk2x_i (.O(clk2x), .I(clk2x_pre), .CE(1'b1), .CLR(rst));
+ else if (BUF_CLK2X == "BUFMR") BUFMR clk2x_i (.O(clk2x), .I(clk2x_pre));
+ else if (BUF_CLK2X == "BUFIO") BUFIO clk2x_i (.O(clk2x), .I(clk2x_pre));
else assign clk2x = clk2x_pre;
endgenerate
+
pll_base #(
.CLKIN_PERIOD (CLKIN_PERIOD), // 20
.BANDWIDTH ("OPTIMIZED"),
diff --git a/util_modules/level_cross_clocks.v b/util_modules/level_cross_clocks.v
new file mode 100644
index 0000000000000000000000000000000000000000..bb379e0379b3ee92fb41bc1c25f33f9356d8ebeb
--- /dev/null
+++ b/util_modules/level_cross_clocks.v
@@ -0,0 +1,38 @@
+/*******************************************************************************
+ * Module: level_cross_clocks
+ * Date:2015-07-19
+ * Author: andrey
+ * Description: re-sample signal to a different clock to reduce metastability
+ *
+ * Copyright (c) 2015 Elphel, Inc .
+ * level_cross_clocks.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * level_cross_clocks.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module level_cross_clocks#(
+ parameter WIDTH = 1,
+ parameter REGISTER = 2 // number of registers (>=12)
+)(
+ input clk,
+ input [WIDTH-1:0] d_in,
+ output [WIDTH-1:0] d_out
+);
+
+ reg [WIDTH * REGISTER -1 : 0] regs;
+ assign d_out = regs [WIDTH-1:0];
+ always @ (posedge clk) begin
+ regs <= {d_in, regs[WIDTH * REGISTER -1 : WIDTH]};
+ end
+endmodule
+
diff --git a/wrap/mmcm_phase_cntr.v b/wrap/mmcm_phase_cntr.v
index 003fc7f62d6ebfa8e9e68200c71c7a06b2c4a0f4..76e7083a60d144614c9b2bb6438039bb5b664009 100644
--- a/wrap/mmcm_phase_cntr.v
+++ b/wrap/mmcm_phase_cntr.v
@@ -143,7 +143,7 @@ module mmcm_phase_cntr#(
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKFBOUT_USE_FINE_PS(CLKFBOUT_USE_FINE_PS),
.CLKIN1_PERIOD (CLKIN_PERIOD),
- .CLKIN2_PERIOD (0),
+ .CLKIN2_PERIOD (CLKIN_PERIOD),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE (CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
diff --git a/x393.v b/x393.v
index 49622dfbbe1cac188482f7d0578538e518e767f1..d6031c1e6cf212a23491d765d4ab4ae01dbbad55 100644
--- a/x393.v
+++ b/x393.v
@@ -1449,6 +1449,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
+ .BUF_IPCLK (BUF_IPCLK),
+ .BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
diff --git a/x393.xdc b/x393.xdc
index 8373fb728077862b30a7d1da4503c3c6e021072e..972c4c6c60df91e880170a7e3f852af8bb94e933 100644
--- a/x393.xdc
+++ b/x393.xdc
@@ -19,6 +19,10 @@
# along with this program. If not, see .
#################################################################################
+#http://forums.xilinx.com/t5/7-Series-FPGAs/MMCM-reference-clock-muxing/td-p/550622
+set_property is_enabled false [get_drc_checks REQP-119]
+
+
# output SDRST, // output SDRST, active low
set_property IOSTANDARD SSTL15 [get_ports {SDRST}]
set_property PACKAGE_PIN J4 [get_ports {SDRST}]
@@ -204,7 +208,7 @@ set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
# output DUMMY_TO_KEEP, // to keep PS7 signals from "optimization"
-#set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
+set_property IOSTANDARD LVCMOS25 [get_ports {DUMMY_TO_KEEP}]
set_property PACKAGE_PIN T11 [get_ports {DUMMY_TO_KEEP}]
#not yet used, just for debugging
@@ -244,3 +248,175 @@ set_property DCI_CASCADE 34 [get_iobanks 35]
set_property INTERNAL_VREF 0.750 [get_iobanks 35]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
+
+# ================= Sensor port 0 =================
+# inout [7:0] sns1_dp,
+# inout [7:0] sns1_dn,
+set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
+set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
+
+set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
+set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
+
+set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
+set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
+
+set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
+set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
+
+set_property PACKAGE_PIN AB9 [get_ports {sns1_dp[4]}]
+set_property PACKAGE_PIN AB8 [get_ports {sns1_dn[4]}]
+
+set_property PACKAGE_PIN AB13 [get_ports {sns1_dp[5]}]
+set_property PACKAGE_PIN AB12 [get_ports {sns1_dn[5]}]
+
+set_property PACKAGE_PIN AA12 [get_ports {sns1_dp[6]}]
+set_property PACKAGE_PIN AA11 [get_ports {sns1_dn[6]}]
+
+set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}]
+set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}]
+# inout sns1_clkp,
+# inout sns1_clkn,
+set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}]
+set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}]
+# inout sns1_scl,
+# inout sns1_sda,
+set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}]
+set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}]
+# inout sns1_ctl,
+# inout sns1_pg,
+set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}]
+set_property PACKAGE_PIN U8 [get_ports {sns1_pg}]
+
+
+# ================= Sensor port 1 =================
+# inout [7:0] sns2_dp,
+# inout [7:0] sns2_dn,
+set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
+set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
+
+set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
+set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
+
+set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
+set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
+
+set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
+set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
+
+set_property PACKAGE_PIN AA17 [get_ports {sns2_dp[4]}]
+set_property PACKAGE_PIN AB17 [get_ports {sns2_dn[4]}]
+
+set_property PACKAGE_PIN AA15 [get_ports {sns2_dp[5]}]
+set_property PACKAGE_PIN AB15 [get_ports {sns2_dn[5]}]
+
+set_property PACKAGE_PIN AA14 [get_ports {sns2_dp[6]}]
+set_property PACKAGE_PIN AB14 [get_ports {sns2_dn[6]}]
+
+set_property PACKAGE_PIN Y14 [get_ports {sns2_dp[7]}]
+set_property PACKAGE_PIN Y13 [get_ports {sns2_dn[7]}]
+# inout sns2_clkp,
+# inout sns2_clkn,
+set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}]
+set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}]
+# inout sns2_scl,
+# inout sns2_sda,
+set_property PACKAGE_PIN T12 [get_ports {sns2_scl}]
+set_property PACKAGE_PIN U12 [get_ports {sns2_sda}]
+# inout sns2_ctl,
+# inout sns2_pg,
+set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}]
+set_property PACKAGE_PIN W16 [get_ports {sns2_pg}]
+
+# ================= Sensor port 2 =================
+# inout [7:0] sns3_dp,
+# inout [7:0] sns3_dn,
+set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
+set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
+
+set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
+set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
+
+set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
+set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
+
+set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
+set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
+
+set_property PACKAGE_PIN N21 [get_ports {sns3_dp[4]}]
+set_property PACKAGE_PIN N22 [get_ports {sns3_dn[4]}]
+
+set_property PACKAGE_PIN R22 [get_ports {sns3_dp[5]}]
+set_property PACKAGE_PIN T22 [get_ports {sns3_dn[5]}]
+
+set_property PACKAGE_PIN P21 [get_ports {sns3_dp[6]}]
+set_property PACKAGE_PIN R21 [get_ports {sns3_dn[6]}]
+
+set_property PACKAGE_PIN T20 [get_ports {sns3_dp[7]}]
+set_property PACKAGE_PIN U20 [get_ports {sns3_dn[7]}]
+# inout sns3_clkp,
+# inout sns3_clkn,
+set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}]
+set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}]
+# inout sns3_scl,
+# inout sns3_sda,
+set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}]
+set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}]
+# inout sns3_ctl,
+# inout sns3_pg,
+set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}]
+set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}]
+
+# ================= Sensor port 3 =================
+# inout [7:0] sns4_dp,
+# inout [7:0] sns4_dn,
+set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
+set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
+
+set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
+set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
+
+set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
+set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
+
+set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
+set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
+
+set_property PACKAGE_PIN P18 [get_ports {sns4_dp[4]}]
+set_property PACKAGE_PIN P19 [get_ports {sns4_dn[4]}]
+
+set_property PACKAGE_PIN N17 [get_ports {sns4_dp[5]}]
+set_property PACKAGE_PIN N18 [get_ports {sns4_dn[5]}]
+
+set_property PACKAGE_PIN N20 [get_ports {sns4_dp[6]}]
+set_property PACKAGE_PIN P20 [get_ports {sns4_dn[6]}]
+
+set_property PACKAGE_PIN R17 [get_ports {sns4_dp[7]}]
+set_property PACKAGE_PIN R18 [get_ports {sns4_dn[7]}]
+# inout sns4_clkp,
+# inout sns4_clkn,
+set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}]
+set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}]
+# inout sns4_scl,
+# inout sns4_sda,
+set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}]
+set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}]
+# inout sns4_ctl,
+# inout sns4_pg,
+set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}]
+set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}]
+#ERROR: [Place 30-149] Unroutable Placement! A MMCM / (BUFIO/BUFR) component pair is not placed in a routable site pair.
+# The MMCM component can use the dedicated path between the MMCM and the (BUFIO/BUFR) if both are placed in the same clock
+# region or if they are placed in horizontally adjacent clock regions. If this sub optimal condition is acceptable
+# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
+# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
\ No newline at end of file
diff --git a/x393_timing.xdc b/x393_timing.xdc
index d2d48f4201f861ac2a6f16f569a3a35d15004bff..ed970bfc9a195048b77e4899937550c753346027 100644
--- a/x393_timing.xdc
+++ b/x393_timing.xdc
@@ -74,10 +74,12 @@ create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
-
+create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
-set_clock_groups -name ps_async_clock_axihp -asynchronous -group {clk_axihp_pre}
+#set_clock_groups -name ps_async_clock_axihp -asynchronous -group {clk_axihp_pre}
+set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
+