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Commit 0466926c authored by Andrey Filippov's avatar Andrey Filippov
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working with Xilinx ISE/Vivado to synthesize and P&R the design

parent 05378ee7
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.project
View file @ 0466926c
......@@ -52,87 +52,87 @@
<link>
<name>ise_logs/ISExst.log</name>
<type>1</type>
<location>/home/andrey/git/x393/ise_logs/ISExst-20150226190731427.log</location>
<location>/home/andrey/git/x393/ise_logs/ISExst-20150228145735970.log</location>
</link>
<link>
<name>ise_state/x393-synth.tgz</name>
<type>1</type>
<location>/home/andrey/git/x393/ise_state/x393-synth-20150226190731427.tgz</location>
<location>/home/andrey/git/x393/ise_state/x393-synth-20150228145735970.tgz</location>
</link>
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<locationURI>vivado_logs/VivadoBitstream-20140611174132808.log</locationURI>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150228213748063.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<locationURI>vivado_logs/VivadoOpt-20140611174132808.log</locationURI>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150228213748063.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<locationURI>vivado_logs/VivadoOptPhys-20140611174132808.log</locationURI>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150228213748063.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<locationURI>vivado_logs/VivadoOptPower-20140611174132808.log</locationURI>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150228213748063.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<locationURI>vivado_logs/VivadoPlace-20140611174132808.log</locationURI>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150228213748063.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<locationURI>vivado_logs/VivadoRoute-20140611174132808.log</locationURI>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150228213748063.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150227195107460.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150228213503140.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<locationURI>vivado_logs/VivadoTimimgSummaryReportImplemented-20140611174132808.log</locationURI>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150228213748063.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150227195107460.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150228213503140.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<locationURI>vivado_logs/VivadoTimingReportImplemented-20140611174132808.log</locationURI>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150228213748063.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150227195107460.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150228213503140.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type>
<locationURI>vivado_state/x393-opt-phys-20140611174132808.dcp</locationURI>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150228213748063.dcp</location>
</link>
<link>
<name>vivado_state/x393-place.dcp</name>
<type>1</type>
<locationURI>vivado_state/x393-place-20140611174132808.dcp</locationURI>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150228213748063.dcp</location>
</link>
<link>
<name>vivado_state/x393-route.dcp</name>
<type>1</type>
<locationURI>vivado_state/x393-route-20140611174132808.dcp</locationURI>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150228213748063.dcp</location>
</link>
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150227195107460.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150228213503140.dcp</location>
</link>
</linkedResources>
</projectDescription>
memctrl/phy/phy_top.v
View file @ 0466926c
......@@ -120,6 +120,7 @@ module phy_top #(
if (rst_in) rst <= 1'b1;
else rst <= 1'b0;
end
wire ld_data_l = (dly_addr[6:5] == 2'h0) && ld_delay ;
wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ;
wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ;
......@@ -271,7 +272,7 @@ wire sdclk; // BUFIO
) oddr_ds_i (
.clk(sdclk), // input
.ce(1'b1), // input
.rst(rst), // input
.rst(1'b0), //rst_n_clk), // input no need to reset?
.set(1'b0), // input
.din(2'b01), // input[1:0]
.tin(rst), // tristate at reset
......
x393.v
View file @ 0466926c
This diff is collapsed.
x393_testbench01.sav
View file @ 0466926c
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Fri Feb 27 02:13:30 2015
[*] Sun Mar 1 04:57:51 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150226183110913.lxt"
[dumpfile_mtime] "Fri Feb 27 01:46:16 2015"
[dumpfile_size] 861913910
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150228214141868.lxt"
[dumpfile_mtime] "Sun Mar 1 04:56:21 2015"
[dumpfile_size] 860951462
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 27500000
[size] 1823 1173
[pos] 2059 0
*-24.698502 91599500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 0
[size] 1823 1180
[pos] 2062 0
*-24.698502 12942500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.genblk4.
......@@ -26,6 +29,7 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
......@@ -37,7 +41,7 @@
[sst_width] 373
[signals_width] 465
[sst_expanded] 1
[sst_vpaned_height] 627
[sst_vpaned_height] 631
@800200
-top_simulation
@28
......@@ -1139,8 +1143,20 @@ x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
@1401200
-test01
@c00201
-vivado_debug
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div_pre[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk_pre[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk[0]
@200
-
@1401201
-vivado_debug
@200
-
@c00200
-byte_lane_0
......@@ -2548,10 +2564,6 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.suspend[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_cols[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_height_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_rows[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_vstep[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_vstep_zero[0]
......@@ -2640,11 +2652,12 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.rst[0]
@1401200
-mmcm_phase_cntr
@800200
@c00200
-memcntrl16_0
@200
-
@800200
-
@c00200
-debug_ch2_ch4
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.set_tile_whs_w[0]
......@@ -2694,10 +2707,13 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.gen
(4)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.i_cmd_deser_multi.sr[4:0]
@1401200
-group_end
@1000200
-debug_ch2_ch4
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_16bit_we[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_16bit_data[15:0]
@c00200
-cmd_deser_16bit_i
@22
......@@ -2797,6 +2813,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrefresh[0]
@1000200
-cmd0_buf
@1401200
-memcntrl16_0
@c00200
-scheduler
......
x393_testbench01.tf
View file @ 0466926c
......@@ -44,7 +44,7 @@
`define TEST_TILED_READ32 1
module x393_testbench01 #(
`include "includes/x393_parameters.vh"
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
`include "includes/x393_simulation_parameters.vh"
)(
);
......@@ -57,7 +57,7 @@ module x393_testbench01 #(
`endif
`define DEBUG_WR_SINGLE 1
`define DEBUG_RD_DATA 1
`include "includes/x393_localparams.vh"
`include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used
// DDR3 signals
wire SDRST;
wire SDCLK; // output
......@@ -76,7 +76,7 @@ module x393_testbench01 #(
wire SDDMU; // inout
wire DQSU; // inout
wire NDQSU; // inout
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization"
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
// wire MEMCLK;
// Simulation signals
......@@ -212,7 +212,7 @@ module x393_testbench01 #(
// localparam SCANLINE_STARTXY= 'h0; // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
localparam SCANLINE_STARTX= 'h0; // 13-bit start X (relative to window), high word (normally 0)
localparam SCANLINE_STARTY= 'h0; // 16-bit start y (normally 0)
localparam [1:0] SCANLINE_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write
localparam [1:0] SCANLINE_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write // SuppressThisWarning VEditor - not used
localparam TILED_STARTX= 'h0; // 13-bit start X (relative to window), high word (normally 0)
localparam TILED_STARTY= 'h0; // 16-bit start y (normally 0)
......@@ -227,7 +227,7 @@ module x393_testbench01 #(
localparam TEST01_START_FRAME= 1;
localparam TEST01_NEXT_PAGE= 2;
localparam TEST01_SUSPEND= 4;
localparam TEST01_SUSPEND= 4; // SuppressThisWarning VEditor - not used
......@@ -1718,7 +1718,7 @@ endtask
`include "includes/x393_tasks_mcntrl_en_dis_priority.vh"
`include "includes/x393_tasks_mcntrl_buffers.vh"
`include "includes/x393_tasks_pio_sequences.vh"
`include "includes/x393_tasks_mcntrl_timing.vh"
`include "includes/x393_tasks_mcntrl_timing.vh" // SuppressThisWarning VEditor - not used
`include "includes/x393_tasks_ps_pio.vh"
`include "includes/x393_tasks_status.vh"
`include "includes/x393_tasks01.vh"
......
x393_timing.xdc
View file @ 0466926c
......@@ -62,17 +62,18 @@ create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
### Version used with eddr3
###create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
###create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
###create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
###create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
###create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical *sdclk_pre ]
#create_generated_clock -name ddr3_clk [get_nets -hierarchical *clk_pre ]
#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical *clk_div_pre ]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical *mclk_pre ]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical *clk_ref_pre ]
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre ]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
......
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