Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393
Repository
ae549ed413b3d55ebac0d2b29fd9aaf04ce6c8a7
Switch branch/tag
x393
py393
.project
Find file
Blame
History
Permalink
creating Python program to pass Verilog parameters to Python FPGA tests
· 4c3995d6
Andrey Filippov
authored
Mar 03, 2015
4c3995d6
.project
359 Bytes
Edit
Web IDE
Replace .project
×
Attach a file by drag & drop or
click to upload
Commit message
Replace .project
Replace file
Cancel
A new branch will be created in your fork and a new merge request will be started.
