x393_vospi.timing_summary_impl 251 KB
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
4
| Date         : Mon May 20 11:20:49 2019
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
| Host         : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_timing_summary -file vivado_build/x393.timing_summary_impl
| Design       : x393
| Device       : 7z030-fbg484
| Speed File   : -1  PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 16 register/latch pins with no clock driven by root clock pin: DQSL (HIGH)

 There are 16 register/latch pins with no clock driven by root clock pin: DQSU (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: ffclk1p (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: memclk (HIGH)


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 20 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 90 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
90
 There are 99 ports with no output delay specified. (HIGH)
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
135
      0.080        0.000                      0               149809        0.036        0.000                      0               149809        0.264        0.000                       0                 60885  
136 137


138
All user specified timing constraints are met.
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock           Waveform(ns)         Period(ns)      Frequency(MHz)
-----           ------------         ----------      --------------
axi_aclk        {0.000 10.000}       20.000          50.000          
  axihp_clk     {0.000 3.333}        6.667           150.000         
  clk_fb        {0.000 10.000}       20.000          50.000          
  ddr3_clk      {0.000 1.250}        2.500           400.000         
  ddr3_clk_div  {0.000 2.500}        5.000           200.000         
  ddr3_clk_ref  {0.000 2.500}        5.000           200.000         
  ddr3_mclk     {1.250 3.750}        5.000           200.000         
  ddr3_sdclk    {0.000 1.250}        2.500           400.000         
  multi_clkfb   {0.000 10.000}       20.000          50.000          
  sclk          {0.000 5.000}        10.000          100.000         
  xclk          {0.000 2.083}        4.167           240.000         
ffclk0          {0.000 20.833}       41.667          24.000          
  clkfb         {0.000 20.833}       41.667          24.000          
  pclk          {0.000 50.000}       100.001         10.000          
gtrefclk        {0.000 3.333}        6.666           150.015         
rx_clk          {0.000 3.333}        6.666           150.015         
txoutclk        {0.000 3.333}        6.666           150.015         
usrclk2         {0.000 6.666}        13.333          75.002          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
175 176
axi_aclk             13.812        0.000                      0                 2685        0.057        0.000                      0                 2685        7.000        0.000                       0                   737  
  axihp_clk           0.742        0.000                      0                10218        0.044        0.000                      0                10218        0.267        0.000                       0                  3863  
177 178
  clk_fb                                                                                                                                                         18.751        0.000                       0                     2  
  ddr3_clk                                                                                                                                                        0.279        0.000                       0                    45  
179
  ddr3_clk_div        0.181        0.000                      0                 2158        0.134        0.000                      0                 2158        1.389        0.000                       0                   755  
180
  ddr3_clk_ref                                                                                                                                                    0.264        0.000                       0                     3  
181
  ddr3_mclk           0.151        0.000                      0                81401        0.043        0.000                      0                81401        1.590        0.000                       0                 32799  
182 183
  ddr3_sdclk                                                                                                                                                      1.092        0.000                       0                     3  
  multi_clkfb                                                                                                                                                    18.751        0.000                       0                     2  
184 185 186
  sclk                4.271        0.000                      0                 2742        0.044        0.000                      0                 2742        4.090        0.000                       0                  1349  
  xclk                0.202        0.000                      0                33101        0.038        0.000                      0                33101        0.875        0.000                       0                 13490  
ffclk0               40.972        0.000                      0                    1        0.211        0.000                      0                    1       10.833        0.000                       0                     3  
187
  clkfb                                                                                                                                                          10.966        0.000                       0                     2  
188 189 190 191 192
  pclk               45.389        0.000                      0                10880        0.036        0.000                      0                10880       49.090        0.000                       0                  5316  
gtrefclk              3.795        0.000                      0                   45        0.269        0.000                      0                   45        2.553        0.000                       0                    25  
rx_clk                0.588        0.000                      0                  916        0.040        0.000                      0                  916        2.423        0.000                       0                   329  
txoutclk              2.159        0.000                      0                  232        0.159        0.000                      0                  232        2.666        0.000                       0                   138  
usrclk2               3.117        0.000                      0                 4579        0.053        0.000                      0                 4579        5.756        0.000                       0                  2024  
193 194 195 196 197 198 199 200 201


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
202 203 204
ddr3_clk_div  ddr3_clk            0.319        0.000                      0                   23        0.215        0.000                      0                   23  
ddr3_mclk     ddr3_clk_div        0.080        0.000                      0                  146        1.433        0.000                      0                  146  
ddr3_clk_div  ddr3_mclk           3.006        0.000                      0                   76        0.162        0.000                      0                   76  
205 206 207 208 209 210 211 212 213


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group         From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------         ----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
214 215 216 217 218 219
**async_default**  axihp_clk          axihp_clk                1.159        0.000                      0                   23        0.727        0.000                      0                   23  
**async_default**  ddr3_mclk          ddr3_mclk                0.741        0.000                      0                  469        0.274        0.000                      0                  469  
**async_default**  pclk               pclk                    89.858        0.000                      0                   20        0.318        0.000                      0                   20  
**async_default**  sclk               sclk                     6.877        0.000                      0                   16        0.201        0.000                      0                   16  
**async_default**  usrclk2            usrclk2                  3.039        0.000                      0                    7        0.785        0.000                      0                    7  
**async_default**  xclk               xclk                     0.821        0.000                      0                   72        0.388        0.000                      0                   72  
220 221 222 223 224 225 226 227 228 229 230 231


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  axi_aclk
  To Clock:  axi_aclk

232 233
Setup :            0  Failing Endpoints,  Worst Slack       13.812ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.057ns,  Total Violation        0.000ns
234 235 236 237 238 239
PW    :            0  Failing Endpoints,  Worst Slack        7.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
240
Slack (MET) :             13.812ns  (required time - arrival time)
241 242
  Source:                 mcntrl393_i/select_buf2rd_reg/C
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
243
  Destination:            ps7_i/MAXIGP0RDATA[23]
244
                            (rising edge-triggered cell PS7 clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
245 246 247
  Path Group:             axi_aclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (axi_aclk rise@20.000ns - axi_aclk rise@0.000ns)
248
  Data Path Delay:        5.640ns  (logic 0.467ns (8.280%)  route 5.173ns (91.720%))
249
  Logic Levels:           3  (LUT4=1 LUT5=1 LUT6=1)
250
  Clock Path Skew:        0.037ns (DCD - SCD + CPR)
251
    Destination Clock Delay (DCD):    1.336ns = ( 21.336 - 20.000 ) 
252 253
    Source Clock Delay      (SCD):    1.388ns
    Clock Pessimism Removal (CPR):    0.089ns
254 255 256 257 258 259 260 261 262 263 264
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
265 266
                         net (fo=738, routed)         1.388     1.388    mcntrl393_i/axi_clk
    SLICE_X48Y143        FDRE                                         r  mcntrl393_i/select_buf2rd_reg/C
267
  -------------------------------------------------------------------    -------------------
268 269 270 271 272 273 274 275 276
    SLICE_X48Y143        FDRE (Prop_fdre_C_Q)         0.308     1.696 r  mcntrl393_i/select_buf2rd_reg/Q
                         net (fo=34, routed)          2.246     3.942    cmd_readback_i/lopt_1
    SLICE_X55Y116        LUT4 (Prop_lut4_I1_O)        0.053     3.995 r  cmd_readback_i/xlnx_opt_LUT_ps7_i_i_38/O
                         net (fo=1, routed)           0.457     4.452    cmd_readback_i/xlnx_opt_MAXIGP0RDATA[23]_1
    SLICE_X55Y116        LUT5 (Prop_lut5_I4_O)        0.053     4.505 r  cmd_readback_i/xlnx_opt_LUT_ps7_i_i_38_1/O
                         net (fo=1, routed)           1.368     5.873    cmd_readback_i/xlnx_opt_MAXIGP0RDATA[23]
    SLICE_X55Y147        LUT6 (Prop_lut6_I5_O)        0.053     5.926 r  cmd_readback_i/xlnx_opt_LUT_ps7_i_i_38_2/O
                         net (fo=1, routed)           1.102     7.028    axird_rdata[23]
    PS7_X0Y0             PS7                                          r  ps7_i/MAXIGP0RDATA[23]
277 278 279 280 281
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                     20.000    20.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000    20.000 r  clocks393_i/bufg_axi_aclk_i/O
282 283
                         net (fo=738, routed)         1.336    21.336    axi_aclk
    PS7_X0Y0             PS7                                          r  ps7_i/MAXIGP0ACLK
284 285 286 287
                         clock pessimism              0.089    21.425    
                         clock uncertainty           -0.035    21.390    
    PS7_X0Y0             PS7 (Setup_ps7_MAXIGP0ACLK_MAXIGP0RDATA[23])
                                                     -0.550    20.840    ps7_i
288
  -------------------------------------------------------------------
289 290
                         required time                         20.840    
                         arrival time                          -7.028    
291
  -------------------------------------------------------------------
292
                         slack                                 13.812    
293 294 295 296 297 298 299





Min Delay Paths
--------------------------------------------------------------------------------------
300 301
Slack (MET) :             0.057ns  (arrival time - required time)
  Source:                 axibram_write_i/waddr_i/inreg_reg[16]/C
302
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
303
  Destination:            axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMC/I
304 305 306 307
                            (rising edge-triggered cell RAMD32 clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             axi_aclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axi_aclk rise@0.000ns - axi_aclk rise@0.000ns)
308
  Data Path Delay:        0.200ns  (logic 0.100ns (50.053%)  route 0.100ns (49.947%))
309
  Logic Levels:           0  
310 311 312 313
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.838ns
    Source Clock Delay      (SCD):    0.613ns
    Clock Pessimism Removal (CPR):    0.211ns
314 315 316 317 318 319

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
320 321
                         net (fo=738, routed)         0.613     0.613    axibram_write_i/waddr_i/axi_clk
    SLICE_X37Y151        FDRE                                         r  axibram_write_i/waddr_i/inreg_reg[16]/C
322
  -------------------------------------------------------------------    -------------------
323 324 325
    SLICE_X37Y151        FDRE (Prop_fdre_C_Q)         0.100     0.713 r  axibram_write_i/waddr_i/inreg_reg[16]/Q
                         net (fo=1, routed)           0.100     0.813    axibram_write_i/waddr_i/ram_reg_0_15_12_17/DIC0
    SLICE_X38Y151        RAMD32                                       r  axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMC/I
326 327 328 329 330
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
331 332 333 334 335
                         net (fo=738, routed)         0.838     0.838    axibram_write_i/waddr_i/ram_reg_0_15_12_17/WCLK
    SLICE_X38Y151        RAMD32                                       r  axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMC/CLK
                         clock pessimism             -0.211     0.627    
    SLICE_X38Y151        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.129     0.756    axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMC
336
  -------------------------------------------------------------------
337 338
                         required time                         -0.756    
                         arrival time                           0.813    
339
  -------------------------------------------------------------------
340
                         slack                                  0.057    
341 342 343 344 345 346 347 348 349 350 351 352 353





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axi_aclk
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/bufg_axi_aclk_i/O }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
354
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.183         20.000      17.817     RAMB36_X3Y31    cmd_readback_i/ram_reg_0/CLKBWRCLK
355 356 357 358 359 360 361 362 363 364
Max Period        n/a     PLLE2_ADV/CLKIN1    n/a            52.633        20.000      32.633     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  axihp_clk
  To Clock:  axihp_clk

365 366
Setup :            0  Failing Endpoints,  Worst Slack        0.742ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.044ns,  Total Violation        0.000ns
367 368 369 370 371 372
PW    :            0  Failing Endpoints,  Worst Slack        0.267ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
373 374
Slack (MET) :             0.742ns  (required time - arrival time)
  Source:                 sata_top/ahci_top_i/axi_ahci_regs_i/drp_read_data_reg[7]/C
375
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
376
  Destination:            sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[7]/D
377 378 379 380
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             axihp_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
381 382 383 384 385 386
  Data Path Delay:        5.549ns  (logic 0.361ns (6.505%)  route 5.188ns (93.495%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.377ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.053ns = ( 11.720 - 6.667 ) 
    Source Clock Delay      (SCD):    5.675ns
    Clock Pessimism Removal (CPR):    0.245ns
387 388 389 390 391 392 393 394 395 396 397 398 399 400 401
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     3.904    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/hclk_i/clk1x_i/O
402 403 404 405 406 407 408 409
                         net (fo=3868, routed)        1.651     5.675    sata_top/ahci_top_i/axi_ahci_regs_i/hclk
    SLICE_X108Y38        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/drp_read_data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y38        FDRE (Prop_fdre_C_Q)         0.308     5.983 r  sata_top/ahci_top_i/axi_ahci_regs_i/drp_read_data_reg[7]/Q
                         net (fo=1, routed)           5.188    11.171    sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_i/drp_read_data_reg[15][7]
    SLICE_X34Y148        LUT5 (Prop_lut5_I0_O)        0.053    11.224 r  sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_i/bram_rdata_r[7]_i_1/O
                         net (fo=1, routed)           0.000    11.224    sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_i_n_73
    SLICE_X34Y148        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[7]/D
410 411 412 413 414 415 416 417 418 419
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      6.667     6.667 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.667 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     8.339    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     8.422 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    10.333    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.113    10.446 r  clocks393_i/hclk_i/clk1x_i/O
420 421 422 423 424
                         net (fo=3868, routed)        1.274    11.720    sata_top/ahci_top_i/axi_ahci_regs_i/hclk
    SLICE_X34Y148        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[7]/C
                         clock pessimism              0.245    11.965    
                         clock uncertainty           -0.071    11.893    
    SLICE_X34Y148        FDRE (Setup_fdre_C_D)        0.073    11.966    sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[7]
425
  -------------------------------------------------------------------
426 427
                         required time                         11.966    
                         arrival time                         -11.224    
428
  -------------------------------------------------------------------
429
                         slack                                  0.742    
430 431 432 433 434 435 436





Min Delay Paths
--------------------------------------------------------------------------------------
437 438
Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/inreg_reg[4]/C
439
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
440
  Destination:            sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/RAMC/I
441
                            (rising edge-triggered cell RAMD32 clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
442 443 444
  Path Group:             axihp_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
445
  Data Path Delay:        0.146ns  (logic 0.091ns (62.374%)  route 0.055ns (37.626%))
446
  Logic Levels:           0  
447 448 449 450
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.651ns
    Source Clock Delay      (SCD):    2.118ns
    Clock Pessimism Removal (CPR):    0.522ns
451 452 453 454 455 456 457 458 459 460 461

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.478    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/hclk_i/clk1x_i/O
462 463
                         net (fo=3868, routed)        0.614     2.118    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/hclk
    SLICE_X37Y155        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/inreg_reg[4]/C
464
  -------------------------------------------------------------------    -------------------
465 466 467
    SLICE_X37Y155        FDRE (Prop_fdre_C_Q)         0.091     2.209 r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/inreg_reg[4]/Q
                         net (fo=1, routed)           0.055     2.264    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/DIC0
    SLICE_X36Y155        RAMD32                                       r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/RAMC/I
468 469 470 471 472 473 474 475 476 477
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.782    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/hclk_i/clk1x_i/O
478 479 480 481 482
                         net (fo=3868, routed)        0.839     2.651    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/WCLK
    SLICE_X36Y155        RAMD32                                       r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/RAMC/CLK
                         clock pessimism             -0.522     2.129    
    SLICE_X36Y155        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     2.220    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/RAMC
483
  -------------------------------------------------------------------
484 485
                         required time                         -2.220    
                         arrival time                           2.264    
486
  -------------------------------------------------------------------
487
                         slack                                  0.044    
488 489 490 491 492 493 494 495 496 497 498 499 500 501 502





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axihp_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin               Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/DRPCLK  n/a            6.400         6.667       0.267      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/DRPCLK
Max Period        n/a     PLLE2_ADV/CLKOUT0     n/a            160.000       6.667       153.333    PLLE2_ADV_X0Y0      clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
503 504
Low Pulse Width   Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X14Y83        compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_ptr_i/ptr_ram_reg_0_7_15_15/DP/CLK
High Pulse Width  Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X32Y123       sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_54_59/RAMA/CLK
505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557



---------------------------------------------------------------------------------------------------
From Clock:  clk_fb
  To Clock:  clk_fb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       20.000      80.000     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk
  To Clock:  ddr3_clk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.279ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFR/I              n/a            2.221         2.500       0.279      BUFR_X1Y8        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_clk_div

558 559
Setup :            0  Failing Endpoints,  Worst Slack        0.181ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.134ns,  Total Violation        0.000ns
560 561 562 563 564 565
PW    :            0  Failing Endpoints,  Worst Slack        1.389ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
566
Slack (MET) :             0.181ns  (required time - arrival time)
567
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
568
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
569
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i/RST
570
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
571 572 573
  Path Group:             ddr3_clk_div
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_clk_div rise@5.000ns - ddr3_clk_div rise@0.000ns)
574
  Data Path Delay:        4.074ns  (logic 0.269ns (6.604%)  route 3.805ns (93.396%))
575
  Logic Levels:           0  
576 577 578
  Clock Path Skew:        0.085ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.639ns = ( 8.639 - 5.000 ) 
    Source Clock Delay      (SCD):    3.810ns
579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
595 596
                         net (fo=753, routed)         0.664     3.810    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/CLK
    SLICE_X116Y102       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
597
  -------------------------------------------------------------------    -------------------
598 599 600
    SLICE_X116Y102       FDRE (Prop_fdre_C_Q)         0.269     4.079 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/Q
                         net (fo=786, routed)         3.805     7.884    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/tin
    OLOGIC_X1Y138        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i/RST
601 602 603 604 605 606 607 608 609 610
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      5.000     5.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     6.437    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     6.520 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     7.536    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     7.906 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
611 612 613 614 615 616
                         net (fo=753, routed)         0.733     8.639    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/psincdec_reg
    OLOGIC_X1Y138        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i/CLKDIV
                         clock pessimism              0.256     8.895    
                         clock uncertainty           -0.085     8.810    
    OLOGIC_X1Y138        OSERDESE2 (Setup_oserdese2_CLKDIV_RST)
                                                     -0.745     8.065    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_we_i/oserdes_i/oserdes_i
617
  -------------------------------------------------------------------
618 619
                         required time                          8.065    
                         arrival time                          -7.884    
620
  -------------------------------------------------------------------
621
                         slack                                  0.181    
622 623 624 625 626 627 628





Min Delay Paths
--------------------------------------------------------------------------------------
629 630
Slack (MET) :             0.134ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dly_data_r_reg[0]/C
631
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
632
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[0]/D
633 634 635 636
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_clk_div rise@0.000ns - ddr3_clk_div rise@0.000ns)
637 638
  Data Path Delay:        0.205ns  (logic 0.128ns (62.372%)  route 0.077ns (37.628%))
  Logic Levels:           1  (LUT3=1)
639
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
640 641 642
    Destination Clock Delay (DCD):    1.740ns
    Source Clock Delay      (SCD):    1.424ns
    Clock Pessimism Removal (CPR):    0.305ns
643 644 645 646 647 648 649 650 651 652 653

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     0.580    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.050     0.630 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.433     1.063    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.090     1.153 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
654 655
                         net (fo=753, routed)         0.271     1.424    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/psincdec_reg_0
    SLICE_X116Y113       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dly_data_r_reg[0]/C
656
  -------------------------------------------------------------------    -------------------
657 658 659 660 661
    SLICE_X116Y113       FDRE (Prop_fdre_C_Q)         0.100     1.524 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dly_data_r_reg[0]/Q
                         net (fo=19, routed)          0.077     1.601    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/dly_data_r_reg[7][0]
    SLICE_X117Y113       LUT3 (Prop_lut3_I0_O)        0.028     1.629 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre[0]_i_1__3/O
                         net (fo=1, routed)           0.000     1.629    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre[0]_i_1__3_n_0
    SLICE_X117Y113       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[0]/D
662 663 664 665 666 667 668 669 670 671
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
672 673 674 675
                         net (fo=753, routed)         0.308     1.740    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/psincdec_reg
    SLICE_X117Y113       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[0]/C
                         clock pessimism             -0.305     1.435    
    SLICE_X117Y113       FDRE (Hold_fdre_C_D)         0.060     1.495    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[0]
676
  -------------------------------------------------------------------
677 678
                         required time                         -1.495    
                         arrival time                           1.629    
679
  -------------------------------------------------------------------
680
                         slack                                  0.134    
681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_div
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFR/I              n/a            2.221         5.000       2.779      BUFR_X1Y9        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/I
Max Period        n/a     MMCME2_ADV/CLKOUT2  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width   Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width  Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_ref
  To Clock:  ddr3_clk_ref

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.264ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_ref
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT5 }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     IDELAYCTRL/REFCLK  n/a            3.225         5.000       1.775      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
Max Period  n/a     IDELAYCTRL/REFCLK  n/a            5.264         5.000       0.264      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_mclk
  To Clock:  ddr3_mclk

728 729
Setup :            0  Failing Endpoints,  Worst Slack        0.151ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.043ns,  Total Violation        0.000ns
730 731 732 733 734 735
PW    :            0  Failing Endpoints,  Worst Slack        1.590ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
736 737
Slack (MET) :             0.151ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_early_master_reg_rep/C
738
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
739
  Destination:            event_logger_i/status_generate_i/status_generate_only_i/data_reg[1]/D
740
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
741 742
  Path Group:             ddr3_mclk
  Path Type:              Setup (Max at Slow Process Corner)
743
  Requirement:            5.000ns  (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
744 745 746 747 748 749
  Data Path Delay:        4.651ns  (logic 0.435ns (9.352%)  route 4.216ns (90.648%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.147ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.424ns = ( 10.674 - 6.250 ) 
    Source Clock Delay      (SCD):    4.805ns = ( 6.055 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.234ns
750 751 752 753 754 755 756 757 758 759 760 761 762 763 764
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
765 766 767 768 769 770 771 772
                         net (fo=32797, routed)       1.394     6.055    sync_resets_i/mclk
    SLICE_X54Y96         FDRE                                         r  sync_resets_i/rst_early_master_reg_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y96         FDRE (Prop_fdre_C_Q)         0.282     6.337 f  sync_resets_i/rst_early_master_reg_rep/Q
                         net (fo=1272, routed)        4.216    10.553    event_logger_i/status_generate_i/status_generate_only_i/rst_early_master_reg_rep
    SLICE_X57Y125        LUT5 (Prop_lut5_I2_O)        0.153    10.706 r  event_logger_i/status_generate_i/status_generate_only_i/data[1]_i_1__37/O
                         net (fo=1, routed)           0.000    10.706    event_logger_i/status_generate_i/status_generate_only_i/data_0[1]
    SLICE_X57Y125        FDRE                                         r  event_logger_i/status_generate_i/status_generate_only_i/data_reg[1]/D
773 774
  -------------------------------------------------------------------    -------------------

775 776 777 778
                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
779
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
780 781 782
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
783 784 785 786 787
                         net (fo=32797, routed)       1.247    10.674    event_logger_i/status_generate_i/status_generate_only_i/mclk
    SLICE_X57Y125        FDRE                                         r  event_logger_i/status_generate_i/status_generate_only_i/data_reg[1]/C
                         clock pessimism              0.234    10.908    
                         clock uncertainty           -0.085    10.823    
    SLICE_X57Y125        FDRE (Setup_fdre_C_D)        0.035    10.858    event_logger_i/status_generate_i/status_generate_only_i/data_reg[1]
788
  -------------------------------------------------------------------
789 790
                         required time                         10.858    
                         arrival time                         -10.706    
791
  -------------------------------------------------------------------
792
                         slack                                  0.151    
793 794 795 796 797 798 799





Min Delay Paths
--------------------------------------------------------------------------------------
800 801
Slack (MET) :             0.043ns  (arrival time - required time)
  Source:                 mcntrl393_test01_i/status_generate_chn2_i/status_generate_only_i/data_reg[6]/C
802
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
803
  Destination:            mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA/I
804
                            (rising edge-triggered cell RAMD32 clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
805 806 807
  Path Group:             ddr3_mclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
808
  Data Path Delay:        0.208ns  (logic 0.100ns (48.170%)  route 0.108ns (51.830%))
809
  Logic Levels:           0  
810 811 812
  Clock Path Skew:        0.034ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.246ns = ( 3.496 - 1.250 ) 
    Source Clock Delay      (SCD):    1.757ns = ( 3.007 - 1.250 ) 
813
    Clock Pessimism Removal (CPR):    0.455ns
814 815 816 817 818 819 820 821 822 823 824

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
825 826
                         net (fo=32797, routed)       0.542     3.007    mcntrl393_test01_i/status_generate_chn2_i/status_generate_only_i/mclk
    SLICE_X61Y88         FDRE                                         r  mcntrl393_test01_i/status_generate_chn2_i/status_generate_only_i/data_reg[6]/C
827
  -------------------------------------------------------------------    -------------------
828 829 830
    SLICE_X61Y88         FDRE (Prop_fdre_C_Q)         0.100     3.107 r  mcntrl393_test01_i/status_generate_chn2_i/status_generate_only_i/data_reg[6]/Q
                         net (fo=1, routed)           0.108     3.215    mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/DIA0
    SLICE_X62Y89         RAMD32                                       r  mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA/I
831 832 833 834 835 836 837 838 839 840
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     2.046    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.053     2.099 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.623     2.722    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     2.752 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
841 842 843 844 845
                         net (fo=32797, routed)       0.744     3.496    mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/WCLK
    SLICE_X62Y89         RAMD32                                       r  mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA/CLK
                         clock pessimism             -0.455     3.041    
    SLICE_X62Y89         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.131     3.172    mcntrl393_test01_i/status_router4_i/status_router2_01_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA
846
  -------------------------------------------------------------------
847 848
                         required time                         -3.172    
                         arrival time                           3.215    
849
  -------------------------------------------------------------------
850
                         slack                                  0.043    
851 852 853 854 855 856 857 858 859 860 861 862 863





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_mclk
Waveform(ns):       { 1.250 3.750 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
864
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.495         5.000       2.505      RAMB36_X5Y33     sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/CLKBWRCLK
865
Max Period        n/a     MMCME2_ADV/CLKOUT3  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
866 867
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.910         2.500       1.590      SLICE_X46Y51     compressor393_i/status_router8_i/status_router4_0123_i/status_router2_23_i/fifo_in0_i/ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.910         2.500       1.590      SLICE_X18Y68     sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_i2c_io_i/sensor_i2c_i/fifo_same_clock_i2c_rdata_i/ram_reg_0_15_6_7/RAMA/CLK
868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_sdclk
  To Clock:  ddr3_sdclk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.092ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_sdclk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFIO/I             n/a            1.408         2.500       1.092      BUFIO_X1Y9       mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/iclk_bufio_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0



---------------------------------------------------------------------------------------------------
From Clock:  multi_clkfb
  To Clock:  multi_clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         multi_clkfb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        20.000      32.633     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  sclk
  To Clock:  sclk

921
Setup :            0  Failing Endpoints,  Worst Slack        4.271ns,  Total Violation        0.000ns
922
Hold  :            0  Failing Endpoints,  Worst Slack        0.044ns,  Total Violation        0.000ns
923 924 925 926 927 928
PW    :            0  Failing Endpoints,  Worst Slack        4.090ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
929 930
Slack (MET) :             4.271ns  (required time - arrival time)
  Source:                 event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
931
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
932 933
  Destination:            event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
                            (falling edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
934 935
  Path Group:             sclk
  Path Type:              Setup (Max at Slow Process Corner)
936 937 938 939 940 941 942
  Requirement:            5.000ns  (sclk fall@5.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.499ns  (logic 0.246ns (49.268%)  route 0.253ns (50.732%))
  Logic Levels:           0  
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.052ns = ( 10.052 - 5.000 ) 
    Source Clock Delay      (SCD):    5.415ns
    Clock Pessimism Removal (CPR):    0.343ns
943 944 945 946 947 948 949 950 951 952 953 954 955 956
  Clock Uncertainty:      0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.133ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           2.009     3.904    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/sync_clk_i/clk1x_i/O
957 958
                         net (fo=1347, routed)        1.391     5.415    event_logger_i/i_imu_spi/CLK
    SLICE_X68Y140        FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
959
  -------------------------------------------------------------------    -------------------
960 961 962
    SLICE_X68Y140        FDRE (Prop_fdre_C_Q)         0.246     5.661 r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/Q
                         net (fo=2, routed)           0.253     5.914    event_logger_i/i_imu_spi/sngl_wire_stb_reg_n_0_[0]
    SLICE_X69Y141        FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
963 964
  -------------------------------------------------------------------    -------------------

965 966 967
                         (clock sclk fall edge)       5.000     5.000 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     6.672    clocks393_i/pll_base_i/axi_clk
968
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
969 970 971 972 973 974 975 976
                                                      0.083     6.755 f  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.911     8.666    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.113     8.779 f  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        1.273    10.052    event_logger_i/i_imu_spi/CLK
    SLICE_X69Y141        FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/C  (IS_INVERTED)
                         clock pessimism              0.343    10.395    
                         clock uncertainty           -0.075    10.320    
    SLICE_X69Y141        FDRE (Setup_fdre_C_D)       -0.134    10.186    event_logger_i/i_imu_spi/sngl_wire_r_reg[1]
977
  -------------------------------------------------------------------
978 979
                         required time                         10.186    
                         arrival time                          -5.914    
980
  -------------------------------------------------------------------
981
                         slack                                  4.271    
982 983 984 985 986 987 988





Min Delay Paths
--------------------------------------------------------------------------------------
989
Slack (MET) :             0.044ns  (arrival time - required time)
990
  Source:                 event_logger_i/i_imu_spi/miso_reg_reg[4]/C
991
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
992
  Destination:            i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC/I
993 994 995 996
                            (rising edge-triggered cell RAMD32 clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sclk rise@0.000ns - sclk rise@0.000ns)
997
  Data Path Delay:        0.146ns  (logic 0.091ns (62.374%)  route 0.055ns (37.626%))
998
  Logic Levels:           0  
999
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
1000 1001 1002
    Destination Clock Delay (DCD):    2.541ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    0.502ns
1003 1004 1005 1006 1007 1008 1009 1010 1011 1012

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.771     1.478    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/sync_clk_i/clk1x_i/O
1013 1014
                         net (fo=1347, routed)        0.524     2.028    event_logger_i/i_imu_spi/CLK
    SLICE_X59Y137        FDRE                                         r  event_logger_i/i_imu_spi/miso_reg_reg[4]/C
1015
  -------------------------------------------------------------------    -------------------
1016 1017 1018
    SLICE_X59Y137        FDRE (Prop_fdre_C_Q)         0.091     2.119 r  event_logger_i/i_imu_spi/miso_reg_reg[4]/Q
                         net (fo=2, routed)           0.055     2.174    i_imu_spi/odbuf0_ram_reg_0_31_0_5/DIC0
    SLICE_X58Y137        RAMD32                                       r  i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC/I
1019 1020 1021 1022 1023 1024 1025 1026 1027
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.840     1.782    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/sync_clk_i/clk1x_i/O
1028 1029 1030 1031 1032
                         net (fo=1347, routed)        0.729     2.541    i_imu_spi/odbuf0_ram_reg_0_31_0_5/WCLK
    SLICE_X58Y137        RAMD32                                       r  i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC/CLK
                         clock pessimism             -0.502     2.039    
    SLICE_X58Y137        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     2.130    i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC
1033
  -------------------------------------------------------------------
1034 1035
                         required time                         -2.130    
                         arrival time                           2.174    
1036
  -------------------------------------------------------------------
1037
                         slack                                  0.044    
1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sclk
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I             n/a            1.600         10.000      8.400      BUFGCTRL_X0Y7   clocks393_i/sync_clk_i/clk1x_i/I
Max Period        n/a     PLLE2_ADV/CLKOUT3  n/a            160.000       10.000      150.000    PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
1053 1054
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X54Y135   event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_6_11/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X52Y142   event_logger_i/i_buf_xclk_mclk16/fifo_4x16_ram_reg_0_3_0_5/RAMA/CLK
1055 1056 1057 1058 1059 1060 1061



---------------------------------------------------------------------------------------------------
From Clock:  xclk
  To Clock:  xclk

1062 1063
Setup :            0  Failing Endpoints,  Worst Slack        0.202ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.038ns,  Total Violation        0.000ns
1064 1065 1066 1067 1068 1069
PW    :            0  Failing Endpoints,  Worst Slack        0.875ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1070 1071
Slack (MET) :             0.202ns  (required time - arrival time)
  Source:                 compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/k1_reg[1]/C
1072
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
1073
  Destination:            compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]/D
1074 1075 1076 1077
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             xclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (xclk rise@4.167ns - xclk rise@0.000ns)
1078 1079 1080 1081 1082 1083
  Data Path Delay:        3.920ns  (logic 1.410ns (35.971%)  route 2.510ns (64.029%))
  Logic Levels:           7  (CARRY4=4 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.249ns = ( 9.416 - 4.167 ) 
    Source Clock Delay      (SCD):    5.613ns
    Clock Pessimism Removal (CPR):    0.338ns
1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           2.009     3.904    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/xclk_i/clk1x_i/O
1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121
                         net (fo=13488, routed)       1.589     5.613    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/xclk
    SLICE_X47Y10         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/k1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y10         FDRE (Prop_fdre_C_Q)         0.269     5.882 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/k1_reg[1]/Q
                         net (fo=67, routed)          0.692     6.574    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[3]_0
    SLICE_X47Y13         LUT5 (Prop_lut5_I3_O)        0.053     6.627 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___114_i_7/O
                         net (fo=1, routed)           0.457     7.084    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___114_i_7_n_0
    SLICE_X45Y14         CARRY4 (Prop_carry4_DI[2]_CO[3])
                                                      0.239     7.323 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___114_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.323    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___114_i_2_n_0
    SLICE_X45Y15         CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.132     7.455 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___121_i_4/CO[2]
                         net (fo=2, routed)           0.453     7.908    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___121_i_4_n_1
    SLICE_X46Y16         LUT4 (Prop_lut4_I3_O)        0.161     8.069 f  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___121_i_2/O
                         net (fo=2, routed)           0.467     8.537    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_3
    SLICE_X46Y16         LUT6 (Prop_lut6_I2_O)        0.053     8.590 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/i___124_i_1/O
                         net (fo=2, routed)           0.440     9.030    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_2[0]
    SLICE_X47Y16         CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.324     9.354 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_i_1/CO[3]
                         net (fo=1, routed)           0.000     9.354    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[14]_i_1_n_0
    SLICE_X47Y17         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.179     9.533 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]_i_1/CO[0]
                         net (fo=1, routed)           0.000     9.533    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/mm2[15]
    SLICE_X47Y17         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]/D
1122 1123 1124 1125 1126 1127 1128 1129 1130
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       4.167     4.167 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     4.167 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     5.839    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.083     5.922 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.911     7.833    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.113     7.946 r  clocks393_i/xclk_i/clk1x_i/O
1131 1132 1133 1134 1135
                         net (fo=13488, routed)       1.470     9.416    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/xclk
    SLICE_X47Y17         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]/C
                         clock pessimism              0.338     9.754    
                         clock uncertainty           -0.067     9.686    
    SLICE_X47Y17         FDRE (Setup_fdre_C_D)        0.048     9.734    compressor393_i/cmprs_channel_block[0].jp_channel_i/csconvert_i/i_csconvert18/y2_reg[15]
1136
  -------------------------------------------------------------------
1137 1138
                         required time                          9.734    
                         arrival time                          -9.533    
1139
  -------------------------------------------------------------------
1140
                         slack                                  0.202    
1141 1142 1143 1144 1145 1146 1147





Min Delay Paths
--------------------------------------------------------------------------------------
1148 1149
Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/inreg_reg[8]/C
1150
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
1151
  Destination:            compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/RAMB/I
1152
                            (rising edge-triggered cell RAMD32 clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
1153 1154 1155
  Path Group:             xclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (xclk rise@0.000ns - xclk rise@0.000ns)
1156 1157 1158 1159 1160 1161
  Data Path Delay:        0.145ns  (logic 0.091ns (62.668%)  route 0.054ns (37.332%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.664ns
    Source Clock Delay      (SCD):    2.136ns
    Clock Pessimism Removal (CPR):    0.517ns
1162 1163 1164 1165 1166 1167 1168 1169 1170 1171

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.771     1.478    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/xclk_i/clk1x_i/O
1172 1173
                         net (fo=13488, routed)       0.632     2.136    compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/xclk
    SLICE_X13Y35         FDRE                                         r  compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/inreg_reg[8]/C
1174
  -------------------------------------------------------------------    -------------------
1175 1176 1177
    SLICE_X13Y35         FDRE (Prop_fdre_C_Q)         0.091     2.227 r  compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/inreg_reg[8]/Q
                         net (fo=1, routed)           0.054     2.281    compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/DIB0
    SLICE_X12Y35         RAMD32                                       r  compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/RAMB/I
1178 1179 1180 1181 1182 1183 1184 1185 1186
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.840     1.782    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/xclk_i/clk1x_i/O
1187 1188 1189 1190 1191
                         net (fo=13488, routed)       0.852     2.664    compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/WCLK
    SLICE_X12Y35         RAMD32                                       r  compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/RAMB/CLK
                         clock pessimism             -0.517     2.147    
    SLICE_X12Y35         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.096     2.243    compressor393_i/cmprs_channel_block[1].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/fifo_same_clock_i/ram_reg_0_15_6_11/RAMB
1192
  -------------------------------------------------------------------
1193 1194
                         required time                         -2.243    
                         arrival time                           2.281    
1195
  -------------------------------------------------------------------
1196
                         slack                                  0.038    
1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         xclk
Waveform(ns):       { 0.000 2.083 }
Period(ns):         4.167
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
1210
Min Period        n/a     DSP48E1/CLK        n/a            3.292         4.167       0.875      DSP48_X2Y1      compressor393_i/cmprs_channel_block[0].jp_channel_i/focus_sharp393_i/mult_p_r_reg/CLK
1211
Max Period        n/a     PLLE2_ADV/CLKOUT1  n/a            160.000       4.167       155.833    PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
1212 1213
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X88Y4     compressor393_i/cmprs_channel_block[2].jp_channel_i/dct2d8x8_chen_i/dct1d_chen_reorder_in_i/bufh_ram_reg_0_3_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X58Y13    compressor393_i/cmprs_channel_block[3].jp_channel_i/focus_sharp393_i/ram4_reg_0_3_0_4/RAMA/CLK
1214 1215 1216 1217 1218 1219 1220



---------------------------------------------------------------------------------------------------
From Clock:  ffclk0
  To Clock:  ffclk0

1221 1222
Setup :            0  Failing Endpoints,  Worst Slack       40.972ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.211ns,  Total Violation        0.000ns
1223 1224 1225 1226 1227 1228
PW    :            0  Failing Endpoints,  Worst Slack       10.833ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1229
Slack (MET) :             40.972ns  (required time - arrival time)
1230 1231 1232 1233 1234 1235 1236
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            41.667ns  (ffclk0 rise@41.667ns - ffclk0 rise@0.000ns)
1237
  Data Path Delay:        0.731ns  (logic 0.361ns (49.417%)  route 0.370ns (50.583%))
1238 1239
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
1240 1241 1242
    Destination Clock Delay (DCD):    4.390ns = ( 46.057 - 41.667 ) 
    Source Clock Delay      (SCD):    4.689ns
    Clock Pessimism Removal (CPR):    0.299ns
1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
1257 1258
                         net (fo=2, routed)           1.457     4.689    clocks393_i/clk_in
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/C
1259
  -------------------------------------------------------------------    -------------------
1260 1261 1262 1263 1264
    SLICE_X20Y91         FDCE (Prop_fdce_C_Q)         0.308     4.997 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           0.370     5.366    clocks393_i/test_clk_reg
    SLICE_X20Y91         LUT1 (Prop_lut1_I0_O)        0.053     5.419 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     5.419    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/D
1265 1266 1267 1268 1269 1270 1271 1272
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)    41.667    41.667 r  
    Y12                                               0.000    41.667 r  ffclk0p (IN)
                         net (fo=0)                   0.000    41.667    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    42.494 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102    44.596    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113    44.709 r  PLLE2_ADV_i_i_1__0/O
1273 1274 1275 1276 1277
                         net (fo=2, routed)           1.348    46.057    clocks393_i/clk_in
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism              0.299    46.356    
                         clock uncertainty           -0.035    46.320    
    SLICE_X20Y91         FDCE (Setup_fdce_C_D)        0.071    46.391    clocks393_i/test_clk_reg[1]
1278
  -------------------------------------------------------------------
1279 1280
                         required time                         46.391    
                         arrival time                          -5.419    
1281
  -------------------------------------------------------------------
1282
                         slack                                 40.972    
1283 1284 1285 1286 1287 1288 1289





Min Delay Paths
--------------------------------------------------------------------------------------
1290
Slack (MET) :             0.211ns  (arrival time - required time)
1291 1292 1293 1294 1295 1296 1297
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ffclk0 rise@0.000ns - ffclk0 rise@0.000ns)
1298
  Data Path Delay:        0.298ns  (logic 0.146ns (49.073%)  route 0.152ns (50.927%))
1299 1300
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
1301 1302 1303
    Destination Clock Delay (DCD):    2.301ns
    Source Clock Delay      (SCD):    1.949ns
    Clock Pessimism Removal (CPR):    0.352ns
1304 1305 1306 1307 1308 1309 1310 1311 1312

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
1313 1314
                         net (fo=2, routed)           0.581     1.949    clocks393_i/clk_in
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/C
1315
  -------------------------------------------------------------------    -------------------
1316 1317 1318 1319 1320
    SLICE_X20Y91         FDCE (Prop_fdce_C_Q)         0.118     2.067 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           0.152     2.218    clocks393_i/test_clk_reg
    SLICE_X20Y91         LUT1 (Prop_lut1_I0_O)        0.028     2.246 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     2.246    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/D
1321 1322 1323 1324 1325 1326 1327 1328
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
1329 1330 1331 1332
                         net (fo=2, routed)           0.783     2.301    clocks393_i/clk_in
    SLICE_X20Y91         FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism             -0.352     1.949    
    SLICE_X20Y91         FDCE (Hold_fdce_C_D)         0.087     2.036    clocks393_i/test_clk_reg[1]
1333
  -------------------------------------------------------------------
1334 1335
                         required time                         -2.036    
                         arrival time                           2.246    
1336
  -------------------------------------------------------------------
1337
                         slack                                  0.211    
1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ffclk0
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { ffclk0p }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I            n/a            1.600         41.667      40.067     BUFGCTRL_X0Y8   PLLE2_ADV_i_i_1__0/I
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  clkfb
  To Clock:  clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       10.966ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfb
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         41.667      40.418     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  pclk
  To Clock:  pclk

1385 1386
Setup :            0  Failing Endpoints,  Worst Slack       45.389ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.036ns,  Total Violation        0.000ns
1387 1388 1389 1390 1391 1392
PW    :            0  Failing Endpoints,  Worst Slack       49.090ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1393 1394
Slack (MET) :             45.389ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/cs_r_reg[0]/C
1395 1396 1397 1398 1399 1400
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/CE
                            (falling edge-triggered cell ODDR clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             pclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (pclk fall@50.000ns - pclk rise@0.000ns)
1401
  Data Path Delay:        4.200ns  (logic 0.371ns (8.834%)  route 3.829ns (91.166%))
1402
  Logic Levels:           1  (LUT3=1)
1403
  Clock Path Skew:        0.294ns (DCD - SCD + CPR)
1404
    Destination Clock Delay (DCD):    7.936ns = ( 57.936 - 50.000 ) 
1405 1406
    Source Clock Delay      (SCD):    8.070ns
    Clock Pessimism Removal (CPR):    0.428ns
1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424
  Clock Uncertainty:      0.166ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.324ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.609     4.841    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     4.929 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.633     6.562    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     6.682 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
1425 1426
                         net (fo=5314, routed)        1.388     8.070    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/clk1x
    SLICE_X38Y83         FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/cs_r_reg[0]/C
1427
  -------------------------------------------------------------------    -------------------
1428 1429 1430 1431
    SLICE_X38Y83         FDRE (Prop_fdre_C_Q)         0.308     8.378 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/cs_r_reg[0]/Q
                         net (fo=38, routed)          0.959     9.336    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/spi_clken
    SLICE_X33Y82         LUT3 (Prop_lut3_I2_O)        0.063     9.399 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/ODDR_i_i_1__0/O
                         net (fo=1, routed)           2.870    12.269    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ce
1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445
    OLOGIC_X0Y11         ODDR                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/CE
  -------------------------------------------------------------------    -------------------

                         (clock pclk fall edge)      50.000    50.000 f  
    Y12                                               0.000    50.000 f  ffclk0p (IN)
                         net (fo=0)                   0.000    50.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    50.827 f  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102    52.929    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113    53.042 f  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.476    54.518    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    54.601 f  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.550    56.151    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    56.264 f  clocks393_i/dual_clock_pclk_i/clk1x_i/O
1446
                         net (fo=5314, routed)        1.672    57.936    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/clk1x
1447
    OLOGIC_X0Y11         ODDR                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/C
1448 1449 1450
                         clock pessimism              0.428    58.364    
                         clock uncertainty           -0.166    58.198    
    OLOGIC_X0Y11         ODDR (Setup_oddr_C_CE)      -0.540    57.658    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i
1451
  -------------------------------------------------------------------
1452 1453
                         required time                         57.658    
                         arrival time                         -12.269    
1454
  -------------------------------------------------------------------
1455
                         slack                                 45.389    
1456 1457 1458 1459 1460 1461 1462





Min Delay Paths
--------------------------------------------------------------------------------------
1463 1464
Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[20]/C
1465
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
1466
  Destination:            sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[21]/D
1467 1468 1469 1470
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             pclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclk rise@0.000ns - pclk rise@0.000ns)
1471 1472 1473
  Data Path Delay:        0.406ns  (logic 0.253ns (62.243%)  route 0.153ns (37.757%))
  Logic Levels:           3  (CARRY4=2 LUT3=1)
  Clock Path Skew:        0.299ns (DCD - SCD - CPR)
1474
    Destination Clock Delay (DCD):    3.945ns
1475
    Source Clock Delay      (SCD):    3.202ns
1476
    Clock Pessimism Removal (CPR):    0.444ns
1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.603     1.971    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.021 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.584     2.605    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     2.631 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504
                         net (fo=5314, routed)        0.571     3.202    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/clk1x
    SLICE_X109Y149       FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y149       FDRE (Prop_fdre_C_Q)         0.100     3.302 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[20]/Q
                         net (fo=5, routed)           0.153     3.454    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg_n_0_[20]
    SLICE_X109Y149       LUT3 (Prop_lut3_I2_O)        0.028     3.482 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__3_i_2/O
                         net (fo=1, routed)           0.000     3.482    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__3_i_2_n_0
    SLICE_X109Y149       CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.084     3.566 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__3/CO[3]
                         net (fo=1, routed)           0.001     3.567    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__3_n_0
    SLICE_X109Y150       CARRY4 (Prop_carry4_CI_O[0])
                                                      0.041     3.608 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X0_carry__4/O[0]
                         net (fo=1, routed)           0.000     3.608    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X[21]
    SLICE_X109Y150       FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[21]/D
1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.815     2.333    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.386 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.651     3.037    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     3.067 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
1518 1519
                         net (fo=5314, routed)        0.878     3.945    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/clk1x
    SLICE_X109Y150       FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[21]/C
1520
                         clock pessimism             -0.444     3.501    
1521
    SLICE_X109Y150       FDRE (Hold_fdre_C_D)         0.071     3.572    sensors393_i/sensor_channel_block[0].sensor_channel_i/lens_flat393_i/i_fy/A2X_reg[21]
1522
  -------------------------------------------------------------------
1523
                         required time                         -3.572    
1524
                         arrival time                           3.608    
1525
  -------------------------------------------------------------------
1526
                         slack                                  0.036    
1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pclk
Waveform(ns):       { 0.000 50.000 }
Period(ns):         100.001
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
1540
Min Period        n/a     DSP48E1/CLK        n/a            3.124         100.001     96.877     DSP48_X5Y64     sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_gamma_i/table_mult/CLK
1541
Max Period        n/a     PLLE2_ADV/CLKOUT0  n/a            160.000       100.001     59.999     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
1542 1543
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         50.000      49.090     SLICE_X70Y165   sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK         n/a            0.910         50.000      49.090     SLICE_X54Y163   sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
1544 1545 1546 1547 1548 1549 1550



---------------------------------------------------------------------------------------------------
From Clock:  gtrefclk
  To Clock:  gtrefclk

1551 1552
Setup :            0  Failing Endpoints,  Worst Slack        3.795ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.269ns,  Total Violation        0.000ns
1553 1554 1555 1556 1557 1558
PW    :            0  Failing Endpoints,  Worst Slack        2.553ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1559 1560 1561
Slack (MET) :             3.795ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
1562
  Destination:            sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/CE
1563 1564 1565 1566
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (gtrefclk rise@6.666ns - gtrefclk rise@0.000ns)
1567
  Data Path Delay:        2.574ns  (logic 0.414ns (16.087%)  route 2.160ns (83.913%))
1568
  Logic Levels:           2  (LUT3=1 LUT6=1)
1569 1570 1571 1572
  Clock Path Skew:        -0.018ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.442ns = ( 8.108 - 6.666 ) 
    Source Clock Delay      (SCD):    1.565ns
    Clock Pessimism Removal (CPR):    0.105ns
1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
1584 1585
                         net (fo=25, routed)          1.565     1.565    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X62Y42         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
1586
  -------------------------------------------------------------------    -------------------
1587 1588 1589 1590 1591 1592 1593
    SLICE_X62Y42         FDRE (Prop_fdre_C_Q)         0.308     1.873 r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/Q
                         net (fo=5, routed)           0.844     2.718    sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[2]
    SLICE_X62Y42         LUT6 (Prop_lut6_I1_O)        0.053     2.771 f  sata_top/ahci_sata_layers_i/phy/sata_areset_i_2/O
                         net (fo=4, routed)           0.709     3.479    sata_top/ahci_sata_layers_i/phy/sata_areset_i_2_n_0
    SLICE_X58Y44         LUT3 (Prop_lut3_I2_O)        0.053     3.532 r  sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2/O
                         net (fo=8, routed)           0.607     4.139    sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2_n_0
    SLICE_X63Y42         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/CE
1594 1595 1596 1597 1598
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      6.666     6.666 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
1599 1600 1601 1602 1603
                         net (fo=25, routed)          1.442     8.108    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X63Y42         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C
                         clock pessimism              0.105     8.213    
                         clock uncertainty           -0.035     8.178    
    SLICE_X63Y42         FDRE (Setup_fdre_C_CE)      -0.244     7.934    sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]
1604
  -------------------------------------------------------------------
1605 1606
                         required time                          7.934    
                         arrival time                          -4.139    
1607
  -------------------------------------------------------------------
1608
                         slack                                  3.795    
1609 1610 1611 1612 1613 1614 1615





Min Delay Paths
--------------------------------------------------------------------------------------
1616 1617
Slack (MET) :             0.269ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[4]/C
1618
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
1619
  Destination:            sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[6]/D
1620 1621 1622 1623
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gtrefclk rise@0.000ns - gtrefclk rise@0.000ns)
1624 1625
  Data Path Delay:        0.330ns  (logic 0.157ns (47.568%)  route 0.173ns (52.432%))
  Logic Levels:           1  (LUT5=1)
1626 1627
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.654ns
1628 1629
    Source Clock Delay      (SCD):    0.451ns
    Clock Pessimism Removal (CPR):    0.203ns
1630 1631 1632 1633 1634 1635

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
1636 1637
                         net (fo=25, routed)          0.451     0.451    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X65Y38         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[4]/C
1638
  -------------------------------------------------------------------    -------------------
1639 1640 1641 1642 1643
    SLICE_X65Y38         FDRE (Prop_fdre_C_Q)         0.091     0.542 r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[4]/Q
                         net (fo=4, routed)           0.173     0.715    sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg__0[4]
    SLICE_X65Y38         LUT5 (Prop_lut5_I1_O)        0.066     0.781 r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt[6]_i_2/O
                         net (fo=1, routed)           0.000     0.781    sata_top/ahci_sata_layers_i/phy/p_0_in__2[6]
    SLICE_X65Y38         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[6]/D
1644 1645 1646 1647 1648
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
1649
                         net (fo=25, routed)          0.654     0.654    sata_top/ahci_sata_layers_i/phy/gtrefclk
1650 1651 1652
    SLICE_X65Y38         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[6]/C
                         clock pessimism             -0.203     0.451    
    SLICE_X65Y38         FDRE (Hold_fdre_C_D)         0.061     0.512    sata_top/ahci_sata_layers_i/phy/rxeyereset_cnt_reg[6]
1653
  -------------------------------------------------------------------
1654 1655
                         required time                         -0.512    
                         arrival time                           0.781    
1656
  -------------------------------------------------------------------
1657
                         slack                                  0.269    
1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gtrefclk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O }

Check Type        Corner  Lib Pin                  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/GTREFCLK0  n/a            1.538         6.666       5.128      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/GTREFCLK0
1672 1673
Low Pulse Width   Fast    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X62Y41        sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X62Y41        sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK
1674 1675 1676 1677 1678 1679 1680



---------------------------------------------------------------------------------------------------
From Clock:  rx_clk
  To Clock:  rx_clk

1681 1682
Setup :            0  Failing Endpoints,  Worst Slack        0.588ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.040ns,  Total Violation        0.000ns
1683 1684 1685 1686 1687 1688
PW    :            0  Failing Endpoints,  Worst Slack        2.423ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1689 1690
Slack (MET) :             0.588ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKBWRCLK
1691
                            (rising edge-triggered cell RAMB36E1 clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
1692 1693
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
1694 1695 1696
  Path Group:             rx_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (rx_clk rise@6.666ns - rx_clk rise@0.000ns)
1697 1698 1699 1700
  Data Path Delay:        5.672ns  (logic 1.193ns (21.033%)  route 4.479ns (78.967%))
  Logic Levels:           6  (LUT3=4 LUT6=2)
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.676ns = ( 9.342 - 6.666 ) 
1701
    Source Clock Delay      (SCD):    2.884ns
1702
    Clock Pessimism Removal (CPR):    0.056ns
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
1715
                         net (fo=327, routed)         1.415     2.884    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/CLK
1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733
    RAMB36_X3Y16         RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X3Y16         RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[4])
                                                      0.748     3.632 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/DOBDO[4]
                         net (fo=5, routed)           1.549     5.180    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/rxdata_dec_out[12]
    SLICE_X35Y100        LUT6 (Prop_lut6_I5_O)        0.053     5.233 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_5/O
                         net (fo=7, routed)           0.482     5.715    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/data_in_r_reg[2]
    SLICE_X32Y100        LUT3 (Prop_lut3_I1_O)        0.065     5.780 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/is_prim_r[11]_i_3/O
                         net (fo=2, routed)           0.326     6.106    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/RAMB36E1_i_0
    SLICE_X32Y100        LUT6 (Prop_lut6_I5_O)        0.168     6.274 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[16]_i_2/O
                         net (fo=4, routed)           0.353     6.627    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r_reg[16]
    SLICE_X33Y103        LUT3 (Prop_lut3_I2_O)        0.053     6.680 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_aligned_r_i_2/O
                         net (fo=5, routed)           0.577     7.257    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/RAMB36E1_i_0
    SLICE_X36Y106        LUT3 (Prop_lut3_I1_O)        0.053     7.310 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1/O
                         net (fo=2, routed)           0.763     8.072    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1_n_0
    SLICE_X38Y120        LUT3 (Prop_lut3_I0_O)        0.053     8.125 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/xlnx_opt_LUT_wen_reg[0]_CE_cooolgate_en_gate_1470/O
                         net (fo=6, routed)           0.430     8.556    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]_CE_cooolgate_en_sig_254
    SLICE_X38Y120        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/CE
1734 1735 1736 1737 1738 1739
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
1740 1741 1742 1743 1744
                         net (fo=327, routed)         1.263     9.342    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/CLK
    SLICE_X38Y120        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/C
                         clock pessimism              0.056     9.398    
                         clock uncertainty           -0.035     9.363    
    SLICE_X38Y120        FDRE (Setup_fdre_C_CE)      -0.219     9.144    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]
1745
  -------------------------------------------------------------------
1746 1747
                         required time                          9.144    
                         arrival time                          -8.556    
1748
  -------------------------------------------------------------------
1749
                         slack                                  0.588    
1750 1751 1752 1753 1754 1755 1756





Min Delay Paths
--------------------------------------------------------------------------------------
1757 1758 1759 1760
Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[2]/D
1761 1762 1763 1764
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             rx_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rx_clk rise@0.000ns - rx_clk rise@0.000ns)
1765
  Data Path Delay:        0.306ns  (logic 0.118ns (38.588%)  route 0.188ns (61.412%))
1766
  Logic Levels:           0  
1767 1768 1769 1770
  Clock Path Skew:        0.228ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.374ns
    Source Clock Delay      (SCD):    1.105ns
    Clock Pessimism Removal (CPR):    0.041ns
1771 1772 1773 1774 1775 1776 1777

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.526     0.526    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     0.552 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
1778 1779
                         net (fo=327, routed)         0.553     1.105    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/CLK
    SLICE_X26Y100        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[1]/C
1780
  -------------------------------------------------------------------    -------------------
1781 1782 1783
    SLICE_X26Y100        FDRE (Prop_fdre_C_Q)         0.118     1.223 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[1]/Q
                         net (fo=5, routed)           0.188     1.411    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg_n_0_[1]
    SLICE_X27Y99         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[2]/D
1784 1785 1786 1787 1788 1789
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.563     0.563    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.030     0.593 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
1790 1791 1792 1793
                         net (fo=327, routed)         0.781     1.374    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/CLK
    SLICE_X27Y99         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[2]/C
                         clock pessimism             -0.041     1.333    
    SLICE_X27Y99         FDRE (Hold_fdre_C_D)         0.038     1.371    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fill_reg[2]
1794
  -------------------------------------------------------------------
1795 1796
                         required time                         -1.371    
                         arrival time                           1.411    
1797
  -------------------------------------------------------------------
1798
                         slack                                  0.040    
1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rx_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/RXUSRCLK  n/a            4.000         6.666       2.666      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXUSRCLK
1813 1814
Low Pulse Width   Fast    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X32Y101       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X32Y101       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
1815 1816 1817 1818 1819 1820 1821



---------------------------------------------------------------------------------------------------
From Clock:  txoutclk
  To Clock:  txoutclk

1822 1823
Setup :            0  Failing Endpoints,  Worst Slack        2.159ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.159ns,  Total Violation        0.000ns
1824 1825 1826 1827 1828 1829
PW    :            0  Failing Endpoints,  Worst Slack        2.666ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1830 1831
Slack (MET) :             2.159ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]/C
1832
                            (rising edge-triggered cell FDRE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
1833
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRARDADDR[6]
1834 1835 1836 1837
                            (rising edge-triggered cell RAMB36E1 clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             txoutclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (txoutclk rise@6.666ns - txoutclk rise@0.000ns)
1838
  Data Path Delay:        4.060ns  (logic 0.246ns (6.060%)  route 3.814ns (93.940%))
1839
  Logic Levels:           0  
1840 1841 1842 1843
  Clock Path Skew:        0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.970ns = ( 9.636 - 6.666 ) 
    Source Clock Delay      (SCD):    2.864ns
    Clock Pessimism Removal (CPR):    0.066ns
1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
1857 1858
                         net (fo=136, routed)         1.395     2.864    sata_top/ahci_sata_layers_i/phy/gtx_wrap/CLK
    SLICE_X44Y96         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]/C
1859
  -------------------------------------------------------------------    -------------------
1860 1861 1862
    SLICE_X44Y96         FDRE (Prop_fdre_C_Q)         0.246     3.110 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]/Q
                         net (fo=1, routed)           3.814     6.924    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/ADDRARDADDR[1]
    RAMB36_X5Y3          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRARDADDR[6]
1863 1864 1865 1866 1867 1868 1869
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk rise edge)
                                                      6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
1870 1871 1872 1873 1874 1875
                         net (fo=136, routed)         1.557     9.636    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/CLK
    RAMB36_X5Y3          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/CLKARDCLK
                         clock pessimism              0.066     9.702    
                         clock uncertainty           -0.035     9.666    
    RAMB36_X5Y3          RAMB36E1 (Setup_ramb36e1_CLKARDCLK_ADDRARDADDR[6])
                                                     -0.584     9.082    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i
1876
  -------------------------------------------------------------------
1877 1878
                         required time                          9.082    
                         arrival time                          -6.924    
1879
  -------------------------------------------------------------------
1880
                         slack                                  2.159    
1881 1882 1883 1884 1885 1886 1887