x393_testbench01.sav 181 KB
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[*]
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[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
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[*] Sun Mar  1 04:57:51 2015
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[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150228214141868.lxt"
[dumpfile_mtime] "Sun Mar  1 04:56:21 2015"
[dumpfile_size] 860951462
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[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
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[timestart] 0
[size] 1823 1180
[pos] 2062 0
*-24.698502 12942500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] x393_testbench01.
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[treeopen] x393_testbench01.x393_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.genblk4.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn2_i.cmd_deser_32bit_i.genblk4.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_deser_32bit_i.genblk4.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
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[sst_width] 373
[signals_width] 465
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[sst_expanded] 1
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[sst_vpaned_height] 631
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x393_testbench01.x393_i.status_read_i.axird_start_burst[0]
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x393_testbench01.x393_i.status_read_i.clk[0]
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x393_testbench01.x393_i.status_read_i.dstb[3:0]
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x393_testbench01.x393_i.status_read_i.rd[0]
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x393_testbench01.x393_i.status_read_i.rq[0]
x393_testbench01.x393_i.status_read_i.rq_r[0]
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389 390 391
x393_testbench01.x393_i.status_read_i.select_d[0]
x393_testbench01.x393_i.status_read_i.select_r[0]
x393_testbench01.x393_i.status_read_i.select_w[0]
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x393_testbench01.x393_i.status_read_i.start[0]
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x393_testbench01.x393_i.status_read_i.waddr[7:0]
x393_testbench01.x393_i.status_read_i.wdata[31:0]
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x393_testbench01.x393_i.status_read_i.we[0]
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400
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x393_testbench01.x393_i.status_router2_top_i.chn_sel_w[0]
404
x393_testbench01.x393_i.status_router2_top_i.current_chn_r[0]
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x393_testbench01.x393_i.status_router2_top_i.clk[0]
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x393_testbench01.x393_i.status_router2_top_i.rq_out[0]
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x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_out[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.early_chn[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_out[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_rest_r[0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo0_out[7:0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_half_full[1:0]
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(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_last_byte[1:0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_last_byte[1:0]
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-group_end
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_re[1:0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rcv_rest_r[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_pre_start[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_rcv[1:0]
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-memcntrl16_status_router2_top
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-mcontr_sequencer_status_generate
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.dly_ready[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_busy[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.locked[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.mode[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.mode_w[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.need_to_send[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.rq[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.rq_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.rst[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.snd_rest[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.wd[7:0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.we[0]
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627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817
-mcontr_sequencer_status_generate
@c00200
-mcontr_cmd_deser_16bit
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.addr[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.data[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.stb[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.we[0]
@1401200
-mcontr_cmd_deser_16bit
@c00200
-mcont_cmd_deser_16bit_multi
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.addr[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.data[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.deser_r[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.match_high[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.match_low[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.rst[0]
@800028
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0]
(2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.sr[2:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.stb[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.stb_d[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.i_cmd_deser_multi.we[0]
@1401200
-mcont_cmd_deser_16bit_multi
@c00200
-test01_status_router4
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in0[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in1[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in2[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_in3[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.db_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_in3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_int[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rq_out[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.rst[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_in3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_int[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.start_out[0]
@1401200
-test01_status_router4
@c00200
-test01_status_router2_top
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.clk[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_in[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rq_out[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.chn_sel_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_out[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.current_chn_r[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.db_in0[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.db_in1[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.db_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.early_chn[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo0_out[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo1_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_half_full[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_last_byte[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_nempty[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_nempty_pre[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.fifo_re[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.next_chn[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rcv_rest_r[1:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.rst[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.set_other_only_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.snd_last_byte[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.snd_pre_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.snd_rest_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_top_i.start_rcv[1:0]
@1401200
-test01_status_router2_top
@c00200
-test01_status_router2_01
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.chn_sel_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.clk[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.current_chn_r[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.db_in0[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.db_in1[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.db_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.early_chn[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo0_out[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo1_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_half_full[1:0]
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_last_byte[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_last_byte[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_last_byte[1:0]
@1001200
-group_end
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty[1:0]
@1001200
-group_end
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty_pre[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty_pre[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_nempty_pre[1:0]
@1001200
-group_end
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_re[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_re[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.fifo_re[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.next_chn[0]
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rcv_rest_r[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rcv_rest_r[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rcv_rest_r[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in1[0]
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_in[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rq_out[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.rst[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.set_other_only_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.snd_last_byte[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.snd_pre_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.snd_rest_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_in0[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_in1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_out[0]
@800028
x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_rcv[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_rcv[1:0]
(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.start_rcv[1:0]
@1001200
-group_end
@1401200
-test01_status_router2_01
818
@c00200
819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883
-axibram_read
@28
x393_testbench01.x393_i.axibram_read_i.aclk[0]
x393_testbench01.x393_i.axibram_read_i.ar_half_full[0]
x393_testbench01.x393_i.axibram_read_i.ar_nempty[0]
@22
x393_testbench01.x393_i.axibram_read_i.araddr[31:0]
@28
x393_testbench01.x393_i.axibram_read_i.arburst[1:0]
x393_testbench01.x393_i.axibram_read_i.arburst_out[1:0]
@22
x393_testbench01.x393_i.axibram_read_i.arid[11:0]
x393_testbench01.x393_i.axibram_read_i.arid_out[11:0]
x393_testbench01.x393_i.axibram_read_i.arlen[3:0]
x393_testbench01.x393_i.axibram_read_i.arlen_out[3:0]
@28
x393_testbench01.x393_i.axibram_read_i.arready[0]
x393_testbench01.x393_i.axibram_read_i.arsize[1:0]
x393_testbench01.x393_i.axibram_read_i.arsize_out[1:0]
x393_testbench01.x393_i.axibram_read_i.arvalid[0]
x393_testbench01.x393_i.axibram_read_i.bram_rclk[0]
@22
x393_testbench01.x393_i.axibram_read_i.bram_rdata[31:0]
@28
x393_testbench01.x393_i.axibram_read_i.bram_reg_re_0[0]
x393_testbench01.x393_i.axibram_read_i.bram_reg_re_w[0]
x393_testbench01.x393_i.axibram_read_i.bram_regen[0]
x393_testbench01.x393_i.axibram_read_i.bram_ren[0]
x393_testbench01.x393_i.axibram_read_i.dev_ready[0]
x393_testbench01.x393_i.axibram_read_i.last_in_burst_0[0]
x393_testbench01.x393_i.axibram_read_i.last_in_burst_1[0]
x393_testbench01.x393_i.axibram_read_i.last_in_burst_d_w[0]
x393_testbench01.x393_i.axibram_read_i.last_in_burst_w[0]
x393_testbench01.x393_i.axibram_read_i.pre_last_in_burst_r[0]
x393_testbench01.x393_i.axibram_read_i.pre_left_zero_w[0]
@22
x393_testbench01.x393_i.axibram_read_i.pre_rid0[11:0]
x393_testbench01.x393_i.axibram_read_i.pre_rid[11:0]
@28
x393_testbench01.x393_i.axibram_read_i.pre_rvalid_w[0]
x393_testbench01.x393_i.axibram_read_i.rburst[1:0]
@22
x393_testbench01.x393_i.axibram_read_i.rdata[31:0]
@28
x393_testbench01.x393_i.axibram_read_i.read_in_progress[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_d[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_d_w[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_or[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_w[0]
@22
x393_testbench01.x393_i.axibram_read_i.read_left[3:0]
x393_testbench01.x393_i.axibram_read_i.rid[11:0]
@28
x393_testbench01.x393_i.axibram_read_i.rlast[0]
@22
x393_testbench01.x393_i.axibram_read_i.rlen[3:0]
@28
x393_testbench01.x393_i.axibram_read_i.rready[0]
x393_testbench01.x393_i.axibram_read_i.rresp[1:0]
x393_testbench01.x393_i.axibram_read_i.rst[0]
x393_testbench01.x393_i.axibram_read_i.rvalid[0]
x393_testbench01.x393_i.axibram_read_i.start_burst[0]
x393_testbench01.x393_i.axibram_read_i.start_read_burst_0[0]
x393_testbench01.x393_i.axibram_read_i.start_read_burst_1[0]
x393_testbench01.x393_i.axibram_read_i.start_read_burst_w[0]
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@200
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@28
x393_testbench01.x393_i.axibram_read_i.dev_ready[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_d[0]
x393_testbench01.x393_i.axibram_read_i.read_in_progress_or[0]
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x393_testbench01.x393_i.axibram_read_i.pre_last_in_burst_r[0]
x393_testbench01.x393_i.axibram_read_i.bram_ren[0]
x393_testbench01.x393_i.axibram_read_i.bram_regen[0]
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x393_testbench01.x393_i.axibram_read_i.bram_ren[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sequencer_run_busy[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.cry[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.en[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.en_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.en_refresh[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.grant[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.need[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.over[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.pending_rq[4:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.period_cntr[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.pre_div[3:0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.refresh_due[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.refresh_period[7:0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.set[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.want[0]
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935
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x393_testbench01.x393_i.SDRST[0]
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x393_testbench01.x393_i.SDRAS[0]
x393_testbench01.x393_i.SDCAS[0]
x393_testbench01.x393_i.SDWE[0]
x393_testbench01.x393_i.DQSL[0]
x393_testbench01.x393_i.DQSU[0]
x393_testbench01.x393_i.NDQSL[0]
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x393_testbench01.x393_i.SDODT[0]
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-mcntrl393_test01
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x393_testbench01.x393_i.mcntrl393_test01_i.cmd_a[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_ad[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_data[7:0]
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x393_testbench01.x393_i.mcntrl393_test01_i.cmd_frame_start_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_next_page_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_suspend_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn4[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.page_chn2[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn3[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn4[3:0]
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x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.rst[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_ad[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2[21:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_ad[7:0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_start[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ext_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ext_buf_rrun[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.sequence_done[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.cmd_a[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_ad[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_data[7:0]
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x393_testbench01.x393_i.mcntrl393_test01_i.cmd_frame_start_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_next_page_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_suspend_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_finished_chn1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_finished_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_finished_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_finished_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn1_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn4_r[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn1[15:0]
x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn2[15:0]
x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn3[15:0]
x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn4[15:0]
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x393_testbench01.x393_i.mcntrl393_test01_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn1_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4_r[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.page_chn1[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn2[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn3[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn4[3:0]
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x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.rst[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chn1_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chn1_status[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chn2_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chn2_status[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chn3_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chn3_status[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chn4_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chn4_status[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_ad[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn1[21:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn1_ad[7:0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_chn1_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn1_start[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2[21:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_ad[7:0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_start[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_start[0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4[21:0]
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x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn1[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn1_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div_pre[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk_pre[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk[0]
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x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dq[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dq_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dqs[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dqs_r[0]
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.web[7:0]
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1371
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1373
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1374
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1375
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1376 1377
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ext_raddr[9:0]
1378
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.need_to_send[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.rq_r[0]
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_y[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.curr_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_y[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.calc_valid[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.want_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pending_xfers[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.page_cntr[2:0]
x393_testbench01.x393_i.mcntrl393_i.page_ready_chn1[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn1[3:0]
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1878
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1879 1880 1881 1882 1883
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.busy_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.calc_valid[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.chn_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.chn_rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.chn_rst_d[0]
1884
@22
1885 1886 1887
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_a[3:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_ad[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_data[31:0]
1888
@28
1889 1890 1891 1892 1893
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_extra_pages[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_wrmem[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.continued_xfer[0]
1894
@22
1895 1896
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.curr_y[15:0]
1897
@28
1898 1899 1900 1901
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_done_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_finished[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_finished_r[0]
1902
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1903 1904
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_full_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_full_width_r[13:0]
1905
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1906
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_start[0]
1907
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1908 1909 1910 1911
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_y8_r[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.i[31:0]
1912
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_block[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_in_row[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_row_w[0]
1917
@22
1918 1919 1920 1921 1922
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.leftover[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.lim_by_xfer[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.line_start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.line_start_page_left[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.line_unfinished[15:0]
1923
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1924 1925
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.lsw13_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mclk[0]
1926
@22
1927 1928
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mem_page_left[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mode_reg[4:0]
1929
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.msw_zero[0]
1931
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mul_rslt[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mul_rslt_w[26:0]
1934
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1935 1936
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.need_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_page[0]
1937
@22
1938
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_y[16:0]
1939
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1940
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.page_cntr[2:0]
1941
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.par_mod_r[8:0]
1943
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1944 1945 1946
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pending_xfers[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pgm_param_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pre_want[0]
1947
@22
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.remainder_in_xfer[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.row_col_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.row_left[13:0]
1952
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1953 1954 1955 1956 1957 1958 1959 1960
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_frame_width_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_mode_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_start_addr_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_status_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_window_start_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_window_wh_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.set_window_x0y0_w[0]
1961
@22
1962 1963
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_addr_r[21:0]
1964
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1965
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_not_partial[0]
1966
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1967 1968 1969
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.start_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_ad[7:0]
1970
@28
1971 1972 1973 1974 1975
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_data[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.suspend[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.want_r[0]
1976
@22
1977 1978 1979 1980
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.window_height[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.window_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.window_x0[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.window_y0[15:0]
1981
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1982
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_bank[2:0]
1983
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_col[6:0]
1985
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1986 1987 1988 1989 1990 1991
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_done_d[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_grant[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_limited_by_mem_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_limited_by_mem_page_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_need[0]
1992
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1993 1994
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_num128[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_num128_r[6:0]
1995
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1996 1997 1998 1999 2000 2001
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_neg[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_pos[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_partial[0]
2002
@22
2003
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_row[14:0]
2004
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2005 2006 2007 2008 2009 2010
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0]
Andrey Filippov's avatar
Andrey Filippov committed
2011
@1401200
2012
-LINEAR_CH1
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@c00200
-TILED_CH2
-ch2wr
@22
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.data_out[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_we[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.raddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rpage_set[0]
@1401200
-ch2wr
@c00200
-ch2rd
@22
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.data_in[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.waddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.we[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_set[0]
@1401200
-ch2rd
@c00200
-encod_tiled_wr
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.gen_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rom_r[11:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.loop_continue[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_done[0]
2077 2078
@200
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