x393_testbench01.sav 55.5 KB
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[*]
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[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
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[*] Sat Aug  1 01:57:02 2015
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[*]
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[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150731124427127.lxt"
[dumpfile_mtime] "Fri Jul 31 19:02:35 2015"
[dumpfile_size] 1073757835
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[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
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[timestart] 38799000
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[size] 1823 1180
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[pos] 1919 0
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*-18.877661 39967388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] x393_testbench01.
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[treeopen] x393_testbench01.ddr3_i.
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[treeopen] x393_testbench01.x393_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.
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[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
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[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.
[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].
[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.
[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.
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[sst_width] 363
[signals_width] 446
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[sst_expanded] 1
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x393_testbench01.x393_i.membridge_i.read_started[0]
@22
x393_testbench01.x393_i.membridge_i.rel_addr64[28:0]
@28
x393_testbench01.x393_i.membridge_i.reset_page_rd[0]
x393_testbench01.x393_i.membridge_i.reset_page_wr[0]
x393_testbench01.x393_i.membridge_i.rollover[0]
x393_testbench01.x393_i.membridge_i.rw_in_progress[0]
x393_testbench01.x393_i.membridge_i.set_ctrl_w[0]
x393_testbench01.x393_i.membridge_i.set_len64_w[0]
x393_testbench01.x393_i.membridge_i.set_lo_addr64_w[0]
x393_testbench01.x393_i.membridge_i.set_size64_w[0]
x393_testbench01.x393_i.membridge_i.set_start64_w[0]
x393_testbench01.x393_i.membridge_i.set_status_w[0]
x393_testbench01.x393_i.membridge_i.set_width64_w[0]
@22
x393_testbench01.x393_i.membridge_i.size64[28:0]
x393_testbench01.x393_i.membridge_i.size64_mclk[28:0]
x393_testbench01.x393_i.membridge_i.src_wcntr[3:0]
x393_testbench01.x393_i.membridge_i.start64[28:0]
x393_testbench01.x393_i.membridge_i.start64_mclk[28:0]
@28
x393_testbench01.x393_i.membridge_i.start_hclk[0]
x393_testbench01.x393_i.membridge_i.start_mclk[0]
@22
x393_testbench01.x393_i.membridge_i.status_ad[7:0]
@28
x393_testbench01.x393_i.membridge_i.status_rq[0]
x393_testbench01.x393_i.membridge_i.status_start[0]
x393_testbench01.x393_i.membridge_i.suspend_chn1[0]
@22
x393_testbench01.x393_i.membridge_i.wr_id[4:0]
@28
x393_testbench01.x393_i.membridge_i.wr_mode[0]
x393_testbench01.x393_i.membridge_i.wr_start[0]
665 666
@c00200
-x393_testbench01.x393_i.membridge_i.wresp_pending
667 668
@1401200
-group_end
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669 670 671 672 673 674 675
@28
x393_testbench01.x393_i.membridge_i.write_busy[0]
x393_testbench01.x393_i.membridge_i.write_page[1:0]
x393_testbench01.x393_i.membridge_i.write_page_r[1:0]
x393_testbench01.x393_i.membridge_i.write_pages_ready[2:0]
x393_testbench01.x393_i.membridge_i.xfer_reset_page_rd[0]
x393_testbench01.x393_i.membridge_i.xfer_reset_page_wr[0]
676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695
@200
-
@28
x393_testbench01.x393_i.membridge_i.cmd_we[0]
x393_testbench01.x393_i.membridge_i.set_status_w[0]
@c00200
-membridge_status
@22
x393_testbench01.x393_i.membridge_i.status_generate_i.ad[7:0]
@28
x393_testbench01.x393_i.membridge_i.status_generate_i.clk[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.rq[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.rst[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.start[0]
@22
x393_testbench01.x393_i.membridge_i.status_generate_i.wd[7:0]
@28
x393_testbench01.x393_i.membridge_i.status_generate_i.we[0]
@1401200
-membridge_status
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Andrey Filippov committed
696
-membridge
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@c00200
-debug_01
@28
x393_testbench01.enable_memcntrl.en[0]
@22
x393_testbench01.axi_set_wbuf_delay.delay[3:0]
x393_testbench01.read_status.address[7:0]
x393_testbench01.read_and_wait_w.address[29:0]
x393_testbench01.read_and_wait.address[31:0]
@800200
-axi_read_addr
@22
x393_testbench01.axi_read_addr.addr[31:0]
@28
x393_testbench01.axi_read_addr.burst[1:0]
@22
x393_testbench01.axi_read_addr.id[11:0]
x393_testbench01.axi_read_addr.len[3:0]
@28
x393_testbench01.AR_SET_CMD[0]
@1000200
-axi_read_addr
@28
x393_testbench01.rvalid[0]
x393_testbench01.rready[0]
x393_testbench01.enable_cmda.en[0]
@1401200
-debug_01
@800200
-debug_o2
@28
x393_testbench01.x393_i.mclk[0]
@c00200
-cmd0_buf
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.ren[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.web[3:0]
@1401200
-cmd0_buf
748 749
@200
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@800200
-mcntrl16_sel
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mrst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_0bit_we[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_0bit_addr[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_en[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_reset[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_fill[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_full[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_need[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_set[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
@1000200
-mcntrl16_sel
@c00200
-sheduler16
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.chn_en[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.en_schedul[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn_r[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_sent[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index_valid[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.mrst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_conf[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_r2[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_set[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_some[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf_d[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf_w[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_need_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_want_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_data[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_en[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pri_reg[255:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_need_set_r[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
@1401200
-sheduler16
@c00200
-mcontr_common_chnbuf_reg0
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.buf_chn_sel[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.buf_done[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.buf_run[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_page_nxt[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_rchn[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_rrefresh[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_run[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.page_nxt[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.seq_done[0]
@1401200
-mcontr_common_chnbuf_reg0
@22
x393_testbench01.set_mrs.cmd_addr[29:0]
x393_testbench01.set_mrs.data[31:0]
x393_testbench01.set_mrs.mr0[17:0]
x393_testbench01.set_mrs.mr1[17:0]
x393_testbench01.set_mrs.mr2[17:0]
x393_testbench01.set_mrs.mr3[17:0]
@28
x393_testbench01.set_mrs.reset_dll[0]
@200
-
@1000200
-debug_o2
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mrst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dly_rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst[0]
x393_testbench01.x393_i.idelay_ctrl_reset[0]
x393_testbench01.x393_i.idelay_ctrl_rdy[0]
@200
-
@28
x393_testbench01.x393_i.mrst[0]
@800200
-sync_resets
@28
x393_testbench01.x393_i.sync_resets_i.arst[0]
@c00022
x393_testbench01.x393_i.sync_resets_i.clk[6:0]
@28
(0)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(1)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(2)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(3)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(4)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(5)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(6)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
@1401200
-group_end
@800022
x393_testbench01.x393_i.sync_resets_i.locked[6:0]
@28
(0)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(1)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(2)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(3)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(4)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(5)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(6)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.sync_resets_i.mrst[0]
@800022
x393_testbench01.x393_i.sync_resets_i.rst[6:0]
@28
(0)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(1)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(2)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(3)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(4)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(5)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(6)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.sync_resets_i.rst_early_master[0]
@22
x393_testbench01.x393_i.sync_resets_i.rst_w[6:0]
@200
-
@28
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.clk[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.d_in[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.d_out[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.d_sync[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.regs[1:0]
@200
-
@c00200
-level_cross_clocks_sync_bit
@28
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.clk[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.d_in[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.d_out[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.sync_zer[1:0]
@1401200
-level_cross_clocks_sync_bit
@1000200
-sync_resets
@c00200
-clocks393
@28
x393_testbench01.x393_i.clocks393_i.aclk[0]
x393_testbench01.x393_i.clocks393_i.async_rst[0]
x393_testbench01.x393_i.clocks393_i.cmd_a[0]
@22
x393_testbench01.x393_i.clocks393_i.cmd_ad[7:0]
x393_testbench01.x393_i.clocks393_i.cmd_data[10:0]
@28
x393_testbench01.x393_i.clocks393_i.cmd_stb[0]
x393_testbench01.x393_i.clocks393_i.cmd_we[0]
x393_testbench01.x393_i.clocks393_i.extra_status[1:0]
@22
x393_testbench01.x393_i.clocks393_i.fclk[3:0]
@28
x393_testbench01.x393_i.clocks393_i.ffclk0[0]
x393_testbench01.x393_i.clocks393_i.ffclk0_rst[0]
x393_testbench01.x393_i.clocks393_i.ffclk0n_pad[0]
x393_testbench01.x393_i.clocks393_i.ffclk0p_pad[0]
x393_testbench01.x393_i.clocks393_i.ffclk1[0]
x393_testbench01.x393_i.clocks393_i.ffclk1_rst[0]
x393_testbench01.x393_i.clocks393_i.ffclk1n_pad[0]
x393_testbench01.x393_i.clocks393_i.ffclk1p_pad[0]
x393_testbench01.x393_i.clocks393_i.hclk[0]
@22
x393_testbench01.x393_i.clocks393_i.locked[3:0]
@28
x393_testbench01.x393_i.clocks393_i.locked_hclk[0]
x393_testbench01.x393_i.clocks393_i.locked_pclk[0]
x393_testbench01.x393_i.clocks393_i.locked_sync_clk[0]
x393_testbench01.x393_i.clocks393_i.locked_xclk[0]
x393_testbench01.x393_i.clocks393_i.mclk[0]
x393_testbench01.x393_i.clocks393_i.memclk[0]
x393_testbench01.x393_i.clocks393_i.memclk_pad[0]
x393_testbench01.x393_i.clocks393_i.memclk_rst[0]
x393_testbench01.x393_i.clocks393_i.mrst[0]
x393_testbench01.x393_i.clocks393_i.pclk2x[0]
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_page_rst_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_partial[0]
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1233
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_row[14:0]
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1235 1236 1237 1238 1239 1240
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0]
1241
@1000200
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-linear_rw_chn1
1243
@c00200
1244 1245
-axibram_write
@28
1246 1247 1248 1249 1250
x393_testbench01.x393_i.axibram_write_i.bvalid[0]
x393_testbench01.x393_i.axibram_write_i.bready[0]
x393_testbench01.x393_i.axibram_write_i.bresp_re[0]
x393_testbench01.x393_i.axibram_write_i.wresp_i.we[0]
x393_testbench01.x393_i.axibram_write_i.wresp_i.re[0]
1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354
x393_testbench01.x393_i.axibram_write_i.bram_wclk[0]
x393_testbench01.x393_i.axibram_write_i.bram_wen[0]
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x393_testbench01.x393_i.axibram_write_i.bram_wdata[31:0]
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x393_testbench01.x393_i.axibram_write_i.bvalid[0]
x393_testbench01.x393_i.axibram_write_i.bram_we_w[0]
x393_testbench01.x393_i.axibram_write_i.bresp_re[0]
x393_testbench01.x393_i.axibram_write_i.wlast[0]
x393_testbench01.x393_i.axibram_write_i.wlast_out[0]
@22
x393_testbench01.x393_i.axibram_write_i.awlen_out[3:0]
x393_testbench01.x393_i.axibram_write_i.wlen[3:0]
x393_testbench01.x393_i.axibram_write_i.write_left[3:0]
@28
x393_testbench01.x393_i.axibram_write_i.start_write_burst_w[0]
x393_testbench01.x393_i.axibram_write_i.write_in_progress_w[0]
x393_testbench01.x393_i.axibram_write_i.write_in_progress[0]
@22
x393_testbench01.x393_i.axibram_write_i.write_address[13:0]
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x393_testbench01.x393_i.axibram_write_i.awvalid[0]
x393_testbench01.x393_i.axibram_write_i.awready[0]
x393_testbench01.x393_i.axibram_write_i.wvalid[0]
x393_testbench01.x393_i.axibram_write_i.wready[0]
@200
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x393_testbench01.x393_i.axibram_write_i.aclk[0]
x393_testbench01.x393_i.axibram_write_i.aw_half_full[0]
x393_testbench01.x393_i.axibram_write_i.aw_nempty[0]
x393_testbench01.x393_i.axibram_write_i.aw_nempty_ready[0]
@22
x393_testbench01.x393_i.axibram_write_i.awaddr[31:0]
x393_testbench01.x393_i.axibram_write_i.awaddr_out[13:0]
@28
x393_testbench01.x393_i.axibram_write_i.awburst[1:0]
x393_testbench01.x393_i.axibram_write_i.awburst_out[1:0]
@22
x393_testbench01.x393_i.axibram_write_i.awid[11:0]
x393_testbench01.x393_i.axibram_write_i.awid_out[11:0]
x393_testbench01.x393_i.axibram_write_i.awlen[3:0]
x393_testbench01.x393_i.axibram_write_i.awlen_out[3:0]
@28
x393_testbench01.x393_i.axibram_write_i.awready[0]
x393_testbench01.x393_i.axibram_write_i.awsize[1:0]
x393_testbench01.x393_i.axibram_write_i.awsize_out[1:0]
x393_testbench01.x393_i.axibram_write_i.awvalid[0]
@22
x393_testbench01.x393_i.axibram_write_i.bid[11:0]
x393_testbench01.x393_i.axibram_write_i.bram_waddr[13:0]
@28
x393_testbench01.x393_i.axibram_write_i.bram_wclk[0]
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x393_testbench01.x393_i.axibram_write_i.bram_wdata[31:0]
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x393_testbench01.x393_i.axibram_write_i.bram_we_w[0]
x393_testbench01.x393_i.axibram_write_i.bram_wen[0]
@22
x393_testbench01.x393_i.axibram_write_i.bram_wstb[3:0]
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x393_testbench01.x393_i.axibram_write_i.bready[0]
x393_testbench01.x393_i.axibram_write_i.bresp[1:0]
x393_testbench01.x393_i.axibram_write_i.bresp_in[1:0]
x393_testbench01.x393_i.axibram_write_i.bresp_re[0]
x393_testbench01.x393_i.axibram_write_i.bvalid[0]
x393_testbench01.x393_i.axibram_write_i.dev_ready[0]
x393_testbench01.x393_i.axibram_write_i.dev_ready_r[0]
@22
x393_testbench01.x393_i.axibram_write_i.next_wr_address_w[13:0]
x393_testbench01.x393_i.axibram_write_i.pre_awaddr[13:0]
@28
x393_testbench01.x393_i.axibram_write_i.start_burst[0]
x393_testbench01.x393_i.axibram_write_i.start_write_burst_w[0]
x393_testbench01.x393_i.axibram_write_i.w_half_full[0]
x393_testbench01.x393_i.axibram_write_i.w_nempty[0]
x393_testbench01.x393_i.axibram_write_i.w_nempty_ready[0]
x393_testbench01.x393_i.axibram_write_i.was_bresp_re[0]
x393_testbench01.x393_i.axibram_write_i.wburst[1:0]
@22
x393_testbench01.x393_i.axibram_write_i.wdata[31:0]
x393_testbench01.x393_i.axibram_write_i.wdata_out[31:0]
x393_testbench01.x393_i.axibram_write_i.wid[11:0]
x393_testbench01.x393_i.axibram_write_i.wid_out[11:0]
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x393_testbench01.x393_i.axibram_write_i.wlast[0]
x393_testbench01.x393_i.axibram_write_i.wlast_out[0]
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x393_testbench01.x393_i.axibram_write_i.wlen[3:0]
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x393_testbench01.x393_i.axibram_write_i.wready[0]
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x393_testbench01.x393_i.axibram_write_i.write_address[13:0]
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x393_testbench01.x393_i.axibram_write_i.write_in_progress[0]
x393_testbench01.x393_i.axibram_write_i.write_in_progress_w[0]
@22
x393_testbench01.x393_i.axibram_write_i.write_left[3:0]
x393_testbench01.x393_i.axibram_write_i.wstb[3:0]
x393_testbench01.x393_i.axibram_write_i.wstb_out[3:0]
@28
x393_testbench01.x393_i.axibram_write_i.wvalid[0]
1355
@1401200
1356
-axibram_write
1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
@c00200
-amd_mux
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x393_testbench01.x393_i.cmd_mux_i.par_waddr[13:0]
x393_testbench01.x393_i.cmd_mux_i.par_data[31:0]
x393_testbench01.x393_i.cmd_mux_i.byte_ad[7:0]
@28
x393_testbench01.x393_i.cmd_mux_i.ad_stb[0]
@200
-
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x393_testbench01.x393_i.cmd_mux_i.ad_stb[0]
x393_testbench01.x393_i.cmd_mux_i.ad_stb_r[0]
x393_testbench01.x393_i.cmd_mux_i.axi_clk[0]
x393_testbench01.x393_i.cmd_mux_i.busy[0]
x393_testbench01.x393_i.cmd_mux_i.busy_r[0]
@22
x393_testbench01.x393_i.cmd_mux_i.byte_ad[7:0]
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x393_testbench01.x393_i.cmd_mux_i.can_start_w[0]
x393_testbench01.x393_i.cmd_mux_i.cmdseq_full_r[0]
x393_testbench01.x393_i.cmd_mux_i.cseq_ackn[0]
@22
x393_testbench01.x393_i.cmd_mux_i.cseq_waddr[13:0]
x393_testbench01.x393_i.cmd_mux_i.cseq_waddr_r[13:0]
x393_testbench01.x393_i.cmd_mux_i.cseq_wdata[31:0]
x393_testbench01.x393_i.cmd_mux_i.cseq_wdata_r[31:0]
@28
x393_testbench01.x393_i.cmd_mux_i.cseq_wr_en[0]
x393_testbench01.x393_i.cmd_mux_i.fifo_half_empty[0]
x393_testbench01.x393_i.cmd_mux_i.fifo_nempty[0]
x393_testbench01.x393_i.cmd_mux_i.mclk[0]
@22
x393_testbench01.x393_i.cmd_mux_i.par_ad[47:0]
x393_testbench01.x393_i.cmd_mux_i.par_data[31:0]
x393_testbench01.x393_i.cmd_mux_i.par_waddr[13:0]
x393_testbench01.x393_i.cmd_mux_i.pre_waddr[13:0]
@28
x393_testbench01.x393_i.cmd_mux_i.selected[0]
x393_testbench01.x393_i.cmd_mux_i.selected_w[0]
@22
x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0]
x393_testbench01.x393_i.cmd_mux_i.seq_length[3:0]
@28
x393_testbench01.x393_i.cmd_mux_i.ss[0]
x393_testbench01.x393_i.cmd_mux_i.start_axi_w[0]
x393_testbench01.x393_i.cmd_mux_i.start_w[0]
x393_testbench01.x393_i.cmd_mux_i.start_wburst[0]
@22
x393_testbench01.x393_i.cmd_mux_i.waddr[13:0]
x393_testbench01.x393_i.cmd_mux_i.waddr_fifo_out[13:0]
x393_testbench01.x393_i.cmd_mux_i.wdata[31:0]
x393_testbench01.x393_i.cmd_mux_i.wdata_fifo_out[31:0]
@28
x393_testbench01.x393_i.cmd_mux_i.wr_en[0]
@1401200
-amd_mux
@c00200
-status_read
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x393_testbench01.x393_i.status_read_i.ad[7:0]
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x393_testbench01.x393_i.status_read_i.axi_clk[0]
@22
x393_testbench01.x393_i.status_read_i.axi_status_rdata[31:0]
x393_testbench01.x393_i.status_read_i.axi_status_rdata_r[31:0]
x393_testbench01.x393_i.status_read_i.axird_pre_araddr[13:0]
x393_testbench01.x393_i.status_read_i.axird_raddr[7:0]
x393_testbench01.x393_i.status_read_i.axird_rdata[31:0]
@28
x393_testbench01.x393_i.status_read_i.axird_regen[0]
x393_testbench01.x393_i.status_read_i.axird_ren[0]
x393_testbench01.x393_i.status_read_i.axird_selected[0]
x393_testbench01.x393_i.status_read_i.axird_start_burst[0]
x393_testbench01.x393_i.status_read_i.clk[0]
@22
x393_testbench01.x393_i.status_read_i.dstb[3:0]
@28
x393_testbench01.x393_i.status_read_i.rd[0]
x393_testbench01.x393_i.status_read_i.regen[0]
x393_testbench01.x393_i.status_read_i.rq[0]
x393_testbench01.x393_i.status_read_i.rq_r[0]
x393_testbench01.x393_i.status_read_i.select_d[0]
x393_testbench01.x393_i.status_read_i.select_r[0]
x393_testbench01.x393_i.status_read_i.select_w[0]
x393_testbench01.x393_i.status_read_i.start[0]
@22
x393_testbench01.x393_i.status_read_i.waddr[7:0]
x393_testbench01.x393_i.status_read_i.wdata[31:0]
@28
x393_testbench01.x393_i.status_read_i.we[0]
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-status_read
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@c00200
-readback
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x393_testbench01.x393_i.cmd_readback_i.ad_stb[0]
x393_testbench01.x393_i.cmd_readback_i.axi_clk[0]
@22
x393_testbench01.x393_i.cmd_readback_i.axi_rback_rdata[31:0]
x393_testbench01.x393_i.cmd_readback_i.axi_rback_rdata_r[31:0]
x393_testbench01.x393_i.cmd_readback_i.axird_pre_araddr[13:0]
x393_testbench01.x393_i.cmd_readback_i.axird_rdata[31:0]
@28
x393_testbench01.x393_i.cmd_readback_i.axird_regen[0]
x393_testbench01.x393_i.cmd_readback_i.axird_ren[0]
x393_testbench01.x393_i.cmd_readback_i.axird_selected[0]
x393_testbench01.x393_i.cmd_readback_i.axird_start_burst[0]
x393_testbench01.x393_i.cmd_readback_i.mclk[0]
@22
x393_testbench01.x393_i.cmd_readback_i.par_data[31:0]
x393_testbench01.x393_i.cmd_readback_i.par_waddr[13:0]
@28
x393_testbench01.x393_i.cmd_readback_i.rd[0]
x393_testbench01.x393_i.cmd_readback_i.regen[0]
x393_testbench01.x393_i.cmd_readback_i.select_d[0]
x393_testbench01.x393_i.cmd_readback_i.select_r[0]
x393_testbench01.x393_i.cmd_readback_i.select_w[0]
@22
x393_testbench01.x393_i.cmd_readback_i.wdata[31:0]
@28
x393_testbench01.x393_i.cmd_readback_i.we[0]
x393_testbench01.x393_i.cmd_readback_i.we_w[0]
@1401200
-readback
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