x393_vospi.timing_summary_impl 253 KB
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date         : Thu Apr 25 18:21:02 2019
| Host         : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_timing_summary -file vivado_build/x393.timing_summary_impl
| Design       : x393
| Device       : 7z030-fbg484
| Speed File   : -1  PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 16 register/latch pins with no clock driven by root clock pin: DQSL (HIGH)

 There are 16 register/latch pins with no clock driven by root clock pin: DQSU (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: ffclk1p (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: memclk (HIGH)


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 20 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 90 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 103 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.065        0.000                      0               149245        0.008        0.000                      0               149245        0.264        0.000                       0                 60676  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock           Waveform(ns)         Period(ns)      Frequency(MHz)
-----           ------------         ----------      --------------
axi_aclk        {0.000 10.000}       20.000          50.000          
  axihp_clk     {0.000 3.333}        6.667           150.000         
  clk_fb        {0.000 10.000}       20.000          50.000          
  ddr3_clk      {0.000 1.250}        2.500           400.000         
  ddr3_clk_div  {0.000 2.500}        5.000           200.000         
  ddr3_clk_ref  {0.000 2.500}        5.000           200.000         
  ddr3_mclk     {1.250 3.750}        5.000           200.000         
  ddr3_sdclk    {0.000 1.250}        2.500           400.000         
  multi_clkfb   {0.000 10.000}       20.000          50.000          
  sclk          {0.000 5.000}        10.000          100.000         
  xclk          {0.000 2.083}        4.167           240.000         
ffclk0          {0.000 20.833}       41.667          24.000          
  clkfb         {0.000 20.833}       41.667          24.000          
  pclk          {0.000 50.000}       100.001         10.000          
gtrefclk        {0.000 3.333}        6.666           150.015         
rx_clk          {0.000 3.333}        6.666           150.015         
txoutclk        {0.000 3.333}        6.666           150.015         
usrclk2         {0.000 6.666}        13.333          75.002          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
axi_aclk             13.952        0.000                      0                 2685        0.047        0.000                      0                 2685        7.000        0.000                       0                   737  
  axihp_clk           0.316        0.000                      0                10211        0.053        0.000                      0                10211        0.267        0.000                       0                  3863  
  clk_fb                                                                                                                                                         18.751        0.000                       0                     2  
  ddr3_clk                                                                                                                                                        0.279        0.000                       0                    45  
  ddr3_clk_div        0.367        0.000                      0                 2158        0.133        0.000                      0                 2158        1.389        0.000                       0                   755  
  ddr3_clk_ref                                                                                                                                                    0.264        0.000                       0                     3  
  ddr3_mclk           0.316        0.000                      0                81303        0.008        0.000                      0                81303        1.590        0.000                       0                 32769  
  ddr3_sdclk                                                                                                                                                      1.092        0.000                       0                     3  
  multi_clkfb                                                                                                                                                    18.751        0.000                       0                     2  
  sclk                4.269        0.000                      0                 2736        0.055        0.000                      0                 2736        4.090        0.000                       0                  1349  
  xclk                0.065        0.000                      0                33071        0.042        0.000                      0                33071        0.875        0.000                       0                 13491  
ffclk0               40.985        0.000                      0                    1        0.220        0.000                      0                    1       10.833        0.000                       0                     3  
  clkfb                                                                                                                                                          10.966        0.000                       0                     2  
  pclk               43.745        0.000                      0                10471        0.029        0.000                      0                10471       49.090        0.000                       0                  5136  
gtrefclk              4.218        0.000                      0                   45        0.259        0.000                      0                   45        2.553        0.000                       0                    25  
rx_clk                0.765        0.000                      0                  916        0.055        0.000                      0                  916        2.423        0.000                       0                   329  
txoutclk              1.247        0.000                      0                  232        0.122        0.000                      0                  232        2.666        0.000                       0                   138  
usrclk2               4.996        0.000                      0                 4573        0.029        0.000                      0                 4573        5.756        0.000                       0                  2024  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
ddr3_clk_div  ddr3_clk            0.305        0.000                      0                   23        0.221        0.000                      0                   23  
ddr3_mclk     ddr3_clk_div        0.175        0.000                      0                  146        1.410        0.000                      0                  146  
ddr3_clk_div  ddr3_mclk           2.967        0.000                      0                   76        0.233        0.000                      0                   76  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group         From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------         ----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**  axihp_clk          axihp_clk                1.765        0.000                      0                   23        0.547        0.000                      0                   23  
**async_default**  ddr3_mclk          ddr3_mclk                0.576        0.000                      0                  461        0.280        0.000                      0                  461  
**async_default**  pclk               pclk                    90.827        0.000                      0                   20        0.520        0.000                      0                   20  
**async_default**  sclk               sclk                     7.213        0.000                      0                   16        0.343        0.000                      0                   16  
**async_default**  usrclk2            usrclk2                  6.138        0.000                      0                    7        0.930        0.000                      0                    7  
**async_default**  xclk               xclk                     0.835        0.000                      0                   72        0.420        0.000                      0                   72  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  axi_aclk
  To Clock:  axi_aclk

Setup :            0  Failing Endpoints,  Worst Slack       13.952ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.047ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        7.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             13.952ns  (required time - arrival time)
  Source:                 mcntrl393_i/select_buf3rd_reg/C
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            ps7_i/MAXIGP0RDATA[20]
                            (rising edge-triggered cell PS7 clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             axi_aclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (axi_aclk rise@20.000ns - axi_aclk rise@0.000ns)
  Data Path Delay:        5.500ns  (logic 0.541ns (9.837%)  route 4.959ns (90.163%))
  Logic Levels:           3  (LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.336ns = ( 21.336 - 20.000 ) 
    Source Clock Delay      (SCD):    1.388ns
    Clock Pessimism Removal (CPR):    0.089ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.388     1.388    mcntrl393_i/axi_clk
    SLICE_X48Y145        FDRE                                         r  mcntrl393_i/select_buf3rd_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y145        FDRE (Prop_fdre_C_Q)         0.282     1.670 r  mcntrl393_i/select_buf3rd_reg/Q
                         net (fo=34, routed)          2.045     3.715    cmd_readback_i/lopt_3
    SLICE_X58Y130        LUT4 (Prop_lut4_I3_O)        0.153     3.868 r  cmd_readback_i/xlnx_opt_LUT_ps7_i_i_41/O
                         net (fo=1, routed)           0.779     4.647    cmd_readback_i/xlnx_opt_MAXIGP0RDATA[20]_1
    SLICE_X58Y138        LUT5 (Prop_lut5_I4_O)        0.053     4.700 r  cmd_readback_i/xlnx_opt_LUT_ps7_i_i_41_1/O
                         net (fo=1, routed)           0.994     5.694    cmd_readback_i/xlnx_opt_MAXIGP0RDATA[20]
    SLICE_X58Y153        LUT6 (Prop_lut6_I5_O)        0.053     5.747 r  cmd_readback_i/xlnx_opt_LUT_ps7_i_i_41_2/O
                         net (fo=1, routed)           1.141     6.888    axird_rdata[20]
    PS7_X0Y0             PS7                                          r  ps7_i/MAXIGP0RDATA[20]
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                     20.000    20.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000    20.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.336    21.336    axi_aclk
    PS7_X0Y0             PS7                                          r  ps7_i/MAXIGP0ACLK
                         clock pessimism              0.089    21.425    
                         clock uncertainty           -0.035    21.390    
    PS7_X0Y0             PS7 (Setup_ps7_MAXIGP0ACLK_MAXIGP0RDATA[20])
                                                     -0.550    20.840    ps7_i
  -------------------------------------------------------------------
                         required time                         20.840    
                         arrival time                          -6.888    
  -------------------------------------------------------------------
                         slack                                 13.952    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.047ns  (arrival time - required time)
  Source:                 axibram_write_i/wdata_i/inreg_reg[47]/C
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            axibram_write_i/wdata_i/ram_reg_0_15_42_47/RAMC_D1/I
                            (rising edge-triggered cell RAMD32 clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             axi_aclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axi_aclk rise@0.000ns - axi_aclk rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.091ns (38.771%)  route 0.144ns (61.229%))
  Logic Levels:           0  
  Clock Path Skew:        0.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.757ns
    Source Clock Delay      (SCD):    0.631ns
    Clock Pessimism Removal (CPR):    0.008ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.631     0.631    axibram_write_i/wdata_i/axi_clk
    SLICE_X27Y150        FDRE                                         r  axibram_write_i/wdata_i/inreg_reg[47]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y150        FDRE (Prop_fdre_C_Q)         0.091     0.722 r  axibram_write_i/wdata_i/inreg_reg[47]/Q
                         net (fo=1, routed)           0.144     0.866    axibram_write_i/wdata_i/ram_reg_0_15_42_47/DIC1
    SLICE_X26Y149        RAMD32                                       r  axibram_write_i/wdata_i/ram_reg_0_15_42_47/RAMC_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.757     0.757    axibram_write_i/wdata_i/ram_reg_0_15_42_47/WCLK
    SLICE_X26Y149        RAMD32                                       r  axibram_write_i/wdata_i/ram_reg_0_15_42_47/RAMC_D1/CLK
                         clock pessimism             -0.008     0.749    
    SLICE_X26Y149        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.070     0.819    axibram_write_i/wdata_i/ram_reg_0_15_42_47/RAMC_D1
  -------------------------------------------------------------------
                         required time                         -0.819    
                         arrival time                           0.866    
  -------------------------------------------------------------------
                         slack                                  0.047    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axi_aclk
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/bufg_axi_aclk_i/O }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.183         20.000      17.817     RAMB36_X3Y30    cmd_readback_i/ram_reg_0/CLKBWRCLK
Max Period        n/a     PLLE2_ADV/CLKIN1    n/a            52.633        20.000      32.633     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  axihp_clk
  To Clock:  axihp_clk

Setup :            0  Failing Endpoints,  Worst Slack        0.316ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.053ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.267ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.316ns  (required time - arrival time)
  Source:                 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/outreg_reg[36]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            sata_top/ahci_top_i/axi_ahci_regs_i/hba_reset_cntr_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             axihp_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
  Data Path Delay:        5.618ns  (logic 0.938ns (16.697%)  route 4.680ns (83.303%))
  Logic Levels:           8  (LUT3=1 LUT4=2 LUT5=4 LUT6=1)
  Clock Path Skew:        -0.327ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.047ns = ( 11.714 - 6.667 ) 
    Source Clock Delay      (SCD):    5.629ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     3.904    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.605     5.629    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/hclk
    SLICE_X26Y159        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/outreg_reg[36]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y159        FDRE (Prop_fdre_C_Q)         0.282     5.911 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/outreg_reg[36]/Q
                         net (fo=2, routed)           0.710     6.621    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/wlast_out
    SLICE_X33Y159        LUT5 (Prop_lut5_I0_O)        0.153     6.774 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/write_in_progress_i_2/O
                         net (fo=3, routed)           0.473     7.247    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/write_in_progress_i_2_n_0
    SLICE_X32Y159        LUT5 (Prop_lut5_I0_O)        0.053     7.300 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/wburst[1]_i_1/O
                         net (fo=31, routed)          0.411     7.711    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/write_in_progress_reg[0]
    SLICE_X32Y156        LUT4 (Prop_lut4_I3_O)        0.053     7.764 r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/RAMB36E1_i_i_1__45/O
                         net (fo=55, routed)          0.810     8.574    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/bram_ren_0
    SLICE_X34Y143        LUT5 (Prop_lut5_I1_O)        0.053     8.627 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/RAMB36E1_i_i_4__4/O
                         net (fo=3, routed)           0.590     9.217    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/data_in[9]
    SLICE_X35Y140        LUT4 (Prop_lut4_I3_O)        0.053     9.270 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/pgm_ad[17]_i_3/O
                         net (fo=2, routed)           0.302     9.572    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/pgm_ad[17]_i_3_n_0
    SLICE_X35Y140        LUT3 (Prop_lut3_I0_O)        0.065     9.637 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/hba_reset_cntr[8]_i_5/O
                         net (fo=2, routed)           0.365    10.002    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/hba_reset_cntr[8]_i_5_n_0
    SLICE_X36Y140        LUT6 (Prop_lut6_I0_O)        0.170    10.172 r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/hba_reset_cntr[8]_i_4/O
                         net (fo=12, routed)          0.579    10.751    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/set_hba_rst
    SLICE_X36Y134        LUT5 (Prop_lut5_I4_O)        0.056    10.807 r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/hba_reset_cntr[8]_i_1/O
                         net (fo=9, routed)           0.439    11.247    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i_n_92
    SLICE_X36Y134        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/hba_reset_cntr_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      6.667     6.667 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.667 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     8.339    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     8.422 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    10.333    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.113    10.446 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.268    11.714    sata_top/ahci_top_i/axi_ahci_regs_i/hclk
    SLICE_X36Y134        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/hba_reset_cntr_reg[0]/C
                         clock pessimism              0.255    11.969    
                         clock uncertainty           -0.071    11.897    
    SLICE_X36Y134        FDRE (Setup_fdre_C_CE)      -0.334    11.563    sata_top/ahci_top_i/axi_ahci_regs_i/hba_reset_cntr_reg[0]
  -------------------------------------------------------------------
                         required time                         11.563    
                         arrival time                         -11.247    
  -------------------------------------------------------------------
                         slack                                  0.316    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.053ns  (arrival time - required time)
  Source:                 membridge_i/read_pages_ready_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            membridge_i/read_pages_ready_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             axihp_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
  Data Path Delay:        0.337ns  (logic 0.128ns (38.016%)  route 0.209ns (61.984%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.224ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.591ns
    Source Clock Delay      (SCD):    2.059ns
    Clock Pessimism Removal (CPR):    0.308ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.478    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.555     2.059    membridge_i/hclk
    SLICE_X28Y100        FDRE                                         r  membridge_i/read_pages_ready_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y100        FDRE (Prop_fdre_C_Q)         0.100     2.159 r  membridge_i/read_pages_ready_reg[1]/Q
                         net (fo=4, routed)           0.209     2.368    membridge_i/read_pages_ready_reg_n_0_[1]
    SLICE_X28Y99         LUT6 (Prop_lut6_I3_O)        0.028     2.396 r  membridge_i/read_pages_ready[2]_i_1/O
                         net (fo=1, routed)           0.000     2.396    membridge_i/read_pages_ready[2]_i_1_n_0
    SLICE_X28Y99         FDRE                                         r  membridge_i/read_pages_ready_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.782    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.779     2.591    membridge_i/hclk
    SLICE_X28Y99         FDRE                                         r  membridge_i/read_pages_ready_reg[2]/C
                         clock pessimism             -0.308     2.283    
    SLICE_X28Y99         FDRE (Hold_fdre_C_D)         0.060     2.343    membridge_i/read_pages_ready_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.343    
                         arrival time                           2.396    
  -------------------------------------------------------------------
                         slack                                  0.053    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axihp_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin               Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/DRPCLK  n/a            6.400         6.667       0.267      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/DRPCLK
Max Period        n/a     PLLE2_ADV/CLKOUT0     n/a            160.000       6.667       153.333    PLLE2_ADV_X0Y0      clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X34Y159       sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/waddr_i/ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X36Y122       sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_18_23/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_fb
  To Clock:  clk_fb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       20.000      80.000     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk
  To Clock:  ddr3_clk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.279ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFR/I              n/a            2.221         2.500       0.279      BUFR_X1Y8        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_clk_div

Setup :            0  Failing Endpoints,  Worst Slack        0.367ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.133ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.389ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.367ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/oserdes_i/oserdes_i/RST
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_clk_div rise@5.000ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        3.849ns  (logic 0.269ns (6.990%)  route 3.580ns (93.010%))
  Logic Levels:           0  
  Clock Path Skew:        0.046ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.639ns = ( 8.639 - 5.000 ) 
    Source Clock Delay      (SCD):    3.849ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.703     3.849    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/CLK
    SLICE_X93Y126        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y126        FDRE (Prop_fdre_C_Q)         0.269     4.118 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/Q
                         net (fo=786, routed)         3.580     7.698    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/oserdes_i/tin
    OLOGIC_X1Y136        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/oserdes_i/oserdes_i/RST
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      5.000     5.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     6.437    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     6.520 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     7.536    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     7.906 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.733     8.639    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/oserdes_i/psincdec_reg_0
    OLOGIC_X1Y136        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/oserdes_i/oserdes_i/CLKDIV
                         clock pessimism              0.256     8.895    
                         clock uncertainty           -0.085     8.810    
    OLOGIC_X1Y136        OSERDESE2 (Setup_oserdese2_CLKDIV_RST)
                                                     -0.745     8.065    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/oserdes_i/oserdes_i
  -------------------------------------------------------------------
                         required time                          8.065    
                         arrival time                          -7.698    
  -------------------------------------------------------------------
                         slack                                  0.367    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.133ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/ld_odly_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[6].dq_i/dq_out_dly_i/fdly_pre_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_clk_div rise@0.000ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        0.204ns  (logic 0.128ns (62.781%)  route 0.076ns (37.219%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.740ns
    Source Clock Delay      (SCD):    1.424ns
    Clock Pessimism Removal (CPR):    0.305ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     0.580    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.050     0.630 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.433     1.063    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.090     1.153 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.271     1.424    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/psincdec_reg_0
    SLICE_X116Y113       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/ld_odly_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y113       FDRE (Prop_fdre_C_Q)         0.100     1.524 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/ld_odly_reg[6]/Q
                         net (fo=5, routed)           0.076     1.600    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[6].dq_i/dq_out_dly_i/ld_odly_reg[6][0]
    SLICE_X117Y113       LUT3 (Prop_lut3_I1_O)        0.028     1.628 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[6].dq_i/dq_out_dly_i/fdly_pre[0]_i_1__5/O
                         net (fo=1, routed)           0.000     1.628    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[6].dq_i/dq_out_dly_i/fdly_pre[0]_i_1__5_n_0
    SLICE_X117Y113       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[6].dq_i/dq_out_dly_i/fdly_pre_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.308     1.740    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[6].dq_i/dq_out_dly_i/psincdec_reg
    SLICE_X117Y113       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[6].dq_i/dq_out_dly_i/fdly_pre_reg[0]/C
                         clock pessimism             -0.305     1.435    
    SLICE_X117Y113       FDRE (Hold_fdre_C_D)         0.060     1.495    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[6].dq_i/dq_out_dly_i/fdly_pre_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.495    
                         arrival time                           1.628    
  -------------------------------------------------------------------
                         slack                                  0.133    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_div
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFR/I              n/a            2.221         5.000       2.779      BUFR_X1Y9        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/I
Max Period        n/a     MMCME2_ADV/CLKOUT2  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width   Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width  Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_ref
  To Clock:  ddr3_clk_ref

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.264ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_ref
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT5 }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     IDELAYCTRL/REFCLK  n/a            3.225         5.000       1.775      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
Max Period  n/a     IDELAYCTRL/REFCLK  n/a            5.264         5.000       0.264      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_mclk
  To Clock:  ddr3_mclk

Setup :            0  Failing Endpoints,  Worst Slack        0.316ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.008ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.590ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.316ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_r0r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r_reg/D
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        4.221ns  (logic 0.757ns (17.936%)  route 3.464ns (82.064%))
  Logic Levels:           3  (CARRY4=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.469ns = ( 10.719 - 6.250 ) 
    Source Clock Delay      (SCD):    5.125ns = ( 6.375 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.244ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       1.714     6.375    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/mclk
    SLICE_X0Y12          FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_r0r_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X0Y12          FDRE (Prop_fdre_C_Q)         0.308     6.683 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_r0r_reg[14]/Q
                         net (fo=2, routed)           3.054     9.737    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_r0[14]
    SLICE_X73Y96         LUT6 (Prop_lut6_I4_O)        0.053     9.790 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r1_carry__0_i_1__16/O
                         net (fo=1, routed)           0.000     9.790    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r1_carry__0_i_1__16_n_0
    SLICE_X73Y96         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.239    10.029 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r1_carry__0/CO[0]
                         net (fo=1, routed)           0.410    10.439    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r1
    SLICE_X74Y96         LUT4 (Prop_lut4_I3_O)        0.157    10.596 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r_i_1__17/O
                         net (fo=1, routed)           0.000    10.596    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r
    SLICE_X74Y96         FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       1.292    10.719    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/mclk
    SLICE_X74Y96         FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r_reg/C
                         clock pessimism              0.244    10.963    
                         clock uncertainty           -0.085    10.878    
    SLICE_X74Y96         FDRE (Setup_fdre_C_D)        0.034    10.912    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/status_generate_sens_io_i/status_generate_only_i/status_changed_r_reg
  -------------------------------------------------------------------
                         required time                         10.912    
                         arrival time                         -10.596    
  -------------------------------------------------------------------
                         slack                                  0.316    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.008ns  (arrival time - required time)
  Source:                 mcntrl393_test01_i/page_chn4_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_test01_i/status_generate_chn4_i/status_generate_only_i/status_r0r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        0.273ns  (logic 0.118ns (43.212%)  route 0.155ns (56.788%))
  Logic Levels:           0  
  Clock Path Skew:        0.218ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.251ns = ( 3.501 - 1.250 ) 
    Source Clock Delay      (SCD):    1.746ns = ( 2.996 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.287ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       0.531     2.996    mcntrl393_test01_i/mclk
    SLICE_X50Y100        FDRE                                         r  mcntrl393_test01_i/page_chn4_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y100        FDRE (Prop_fdre_C_Q)         0.118     3.114 r  mcntrl393_test01_i/page_chn4_reg[2]/Q
                         net (fo=3, routed)           0.155     3.269    mcntrl393_test01_i/status_generate_chn4_i/status_generate_only_i/page_chn4_reg[3][2]
    SLICE_X51Y99         FDRE                                         r  mcntrl393_test01_i/status_generate_chn4_i/status_generate_only_i/status_r0r_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     2.046    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.053     2.099 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.623     2.722    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     2.752 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       0.749     3.501    mcntrl393_test01_i/status_generate_chn4_i/status_generate_only_i/mclk
    SLICE_X51Y99         FDRE                                         r  mcntrl393_test01_i/status_generate_chn4_i/status_generate_only_i/status_r0r_reg[20]/C
                         clock pessimism             -0.287     3.214    
    SLICE_X51Y99         FDRE (Hold_fdre_C_D)         0.047     3.261    mcntrl393_test01_i/status_generate_chn4_i/status_generate_only_i/status_r0r_reg[20]
  -------------------------------------------------------------------
                         required time                         -3.261    
                         arrival time                           3.269    
  -------------------------------------------------------------------
                         slack                                  0.008    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_mclk
Waveform(ns):       { 1.250 3.750 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.495         5.000       2.505      RAMB36_X5Y33     sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/CLKBWRCLK
Max Period        n/a     MMCME2_ADV/CLKOUT3  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.910         2.500       1.590      SLICE_X108Y127   sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/AX_ram_reg_0_3_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.910         2.500       1.590      SLICE_X118Y95    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_i2c_io_i/sensor_i2c_i/fifo_same_clock_i2c_rdata_i/ram_reg_0_15_0_5/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_sdclk
  To Clock:  ddr3_sdclk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.092ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_sdclk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFIO/I             n/a            1.408         2.500       1.092      BUFIO_X1Y9       mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/iclk_bufio_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0



---------------------------------------------------------------------------------------------------
From Clock:  multi_clkfb
  To Clock:  multi_clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         multi_clkfb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        20.000      32.633     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  sclk
  To Clock:  sclk

Setup :            0  Failing Endpoints,  Worst Slack        4.269ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.090ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.269ns  (required time - arrival time)
  Source:                 event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
                            (falling edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (sclk fall@5.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.606ns  (logic 0.308ns (50.837%)  route 0.298ns (49.163%))
  Logic Levels:           0  
  Clock Path Skew:        -0.018ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.130ns = ( 10.130 - 5.000 ) 
    Source Clock Delay      (SCD):    5.486ns
    Clock Pessimism Removal (CPR):    0.338ns
  Clock Uncertainty:      0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.133ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           2.009     3.904    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        1.462     5.486    event_logger_i/i_imu_spi/camsync_clk
    SLICE_X10Y98         FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y98         FDRE (Prop_fdre_C_Q)         0.308     5.794 r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/Q
                         net (fo=2, routed)           0.298     6.092    event_logger_i/i_imu_spi/sngl_wire_stb_reg_n_0_[0]
    SLICE_X11Y98         FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sclk fall edge)       5.000     5.000 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     6.672    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.083     6.755 f  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.911     8.666    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.113     8.779 f  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        1.351    10.130    event_logger_i/i_imu_spi/camsync_clk
    SLICE_X11Y98         FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/C  (IS_INVERTED)
                         clock pessimism              0.338    10.468    
                         clock uncertainty           -0.075    10.393    
    SLICE_X11Y98         FDRE (Setup_fdre_C_D)       -0.032    10.361    event_logger_i/i_imu_spi/sngl_wire_r_reg[1]
  -------------------------------------------------------------------
                         required time                         10.361    
                         arrival time                          -6.092    
  -------------------------------------------------------------------
                         slack                                  4.269    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 event_logger_i/i_imu_timestamps/ts_data_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sclk rise@0.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.200ns  (logic 0.100ns (50.053%)  route 0.100ns (49.947%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.595ns
    Source Clock Delay      (SCD):    2.085ns
    Clock Pessimism Removal (CPR):    0.496ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.771     1.478    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        0.581     2.085    event_logger_i/i_imu_timestamps/camsync_clk
    SLICE_X23Y94         FDRE                                         r  event_logger_i/i_imu_timestamps/ts_data_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X23Y94         FDRE (Prop_fdre_C_Q)         0.100     2.185 r  event_logger_i/i_imu_timestamps/ts_data_r_reg[0]/Q
                         net (fo=1, routed)           0.100     2.285    event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/DIA0
    SLICE_X22Y93         RAMD32                                       r  event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.840     1.782    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        0.783     2.595    event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/WCLK
    SLICE_X22Y93         RAMD32                                       r  event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMA/CLK
                         clock pessimism             -0.496     2.099    
    SLICE_X22Y93         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.131     2.230    event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMA
  -------------------------------------------------------------------
                         required time                         -2.230    
                         arrival time                           2.285    
  -------------------------------------------------------------------
                         slack                                  0.055    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sclk
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I             n/a            1.600         10.000      8.400      BUFGCTRL_X0Y7   clocks393_i/sync_clk_i/clk1x_i/I
Max Period        n/a     PLLE2_ADV/CLKOUT3  n/a            160.000       10.000      150.000    PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
Low Pulse Width   Fast    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X26Y95    event_logger_i/i_buf_xclk_mclk16/fifo_4x16_ram_reg_0_3_0_5/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X18Y93    event_logger_i/i_nmea_decoder/odbuf0_ram_reg_0_31_0_3/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  xclk
  To Clock:  xclk

Setup :            0  Failing Endpoints,  Worst Slack        0.065ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.042ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.875ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.065ns  (required time - arrival time)
  Source:                 compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/outreg_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[31]/R
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             xclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (xclk rise@4.167ns - xclk rise@0.000ns)
  Data Path Delay:        3.564ns  (logic 0.651ns (18.266%)  route 2.913ns (81.734%))
  Logic Levels:           5  (LUT2=1 LUT6=4)
  Clock Path Skew:        -0.103ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.237ns = ( 9.404 - 4.167 ) 
    Source Clock Delay      (SCD):    5.597ns
    Clock Pessimism Removal (CPR):    0.257ns
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           2.009     3.904    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13489, routed)       1.573     5.597    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/xclk
    SLICE_X58Y23         FDRE                                         r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/outreg_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y23         FDRE (Prop_fdre_C_Q)         0.282     5.879 r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/outreg_reg[8]/Q
                         net (fo=4, routed)           0.714     6.593    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[0].fifo_same_clock_i/outreg_reg[8]_2[8]
    SLICE_X56Y22         LUT6 (Prop_lut6_I1_O)        0.157     6.750 r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[0].fifo_same_clock_i/d_out[14]_i_2__0/O
                         net (fo=19, routed)          0.570     7.321    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg_reg[8]_0
    SLICE_X55Y22         LUT6 (Prop_lut6_I2_O)        0.053     7.374 r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg[8]_i_4__5/O
                         net (fo=2, routed)           0.455     7.829    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/cry_ff_reg_3
    SLICE_X55Y22         LUT6 (Prop_lut6_I1_O)        0.053     7.882 r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/outreg[8]_i_2__16/O
                         net (fo=9, routed)           0.274     8.155    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/bytes_out0
    SLICE_X55Y23         LUT6 (Prop_lut6_I0_O)        0.053     8.208 r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/d_out[23]_i_1__1/O
                         net (fo=35, routed)          0.305     8.513    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/dv0
    SLICE_X54Y24         LUT2 (Prop_lut2_I1_O)        0.053     8.566 r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out[31]_i_1__1/O
                         net (fo=8, routed)           0.595     9.161    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out[31]_i_1__1_n_0
    SLICE_X55Y25         FDRE                                         r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[31]/R
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       4.167     4.167 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     4.167 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     5.839    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.083     5.922 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.911     7.833    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.113     7.946 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13489, routed)       1.458     9.404    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/xclk
    SLICE_X55Y25         FDRE                                         r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[31]/C
                         clock pessimism              0.257     9.661    
                         clock uncertainty           -0.067     9.593    
    SLICE_X55Y25         FDRE (Setup_fdre_C_R)       -0.367     9.226    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[31]
  -------------------------------------------------------------------
                         required time                          9.226    
                         arrival time                          -9.161    
  -------------------------------------------------------------------
                         slack                                  0.065    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.042ns  (arrival time - required time)
  Source:                 compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/sr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/sr_reg[2]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             xclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (xclk rise@0.000ns - xclk rise@0.000ns)
  Data Path Delay:        0.155ns  (logic 0.100ns (64.432%)  route 0.055ns (35.568%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.622ns
    Source Clock Delay      (SCD):    2.095ns
    Clock Pessimism Removal (CPR):    0.516ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.771     1.478    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13489, routed)       0.591     2.095    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/xclk
    SLICE_X47Y18         FDRE                                         r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/sr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y18         FDRE (Prop_fdre_C_Q)         0.100     2.195 r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/sr_reg[0]/Q
                         net (fo=1, routed)           0.055     2.250    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/sr_reg_n_0_[0]
    SLICE_X46Y18         SRL16E                                       r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/sr_reg[2]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.840     1.782    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13489, routed)       0.810     2.622    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/xclk
    SLICE_X46Y18         SRL16E                                       r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/sr_reg[2]_srl2/CLK
                         clock pessimism             -0.516     2.106    
    SLICE_X46Y18         SRL16E (Hold_srl16e_CLK_D)
                                                      0.102     2.208    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/huffman_snglclk_i/dly_16_val_literal_i/bit_block[2].dly01_16_i/sr_reg[2]_srl2
  -------------------------------------------------------------------
                         required time                         -2.208    
                         arrival time                           2.250    
  -------------------------------------------------------------------
                         slack                                  0.042    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         xclk
Waveform(ns):       { 0.000 2.083 }
Period(ns):         4.167
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     DSP48E1/CLK        n/a            3.292         4.167       0.875      DSP48_X0Y8      compressor393_i/cmprs_channel_block[0].jp_channel_i/focus_sharp393_i/mult_p_r_reg/CLK
Max Period        n/a     PLLE2_ADV/CLKOUT1  n/a            160.000       4.167       155.833    PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X88Y6     compressor393_i/cmprs_channel_block[2].jp_channel_i/dct2d8x8_chen_i/dct1d_chen_reorder_in_i/bufh_ram_reg_0_3_6_9/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X54Y29    compressor393_i/cmprs_channel_block[3].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/ram_reg_0_15_6_8/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  ffclk0
  To Clock:  ffclk0

Setup :            0  Failing Endpoints,  Worst Slack       40.985ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.220ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       10.833ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             40.985ns  (required time - arrival time)
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            41.667ns  (ffclk0 rise@41.667ns - ffclk0 rise@0.000ns)
  Data Path Delay:        0.682ns  (logic 0.322ns (47.229%)  route 0.360ns (52.771%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.314ns = ( 45.981 - 41.667 ) 
    Source Clock Delay      (SCD):    4.624ns
    Clock Pessimism Removal (CPR):    0.310ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.392     4.624    clocks393_i/clk_in
    SLICE_X45Y102        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y102        FDCE (Prop_fdce_C_Q)         0.269     4.893 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           0.360     5.253    clocks393_i/test_clk_reg
    SLICE_X45Y102        LUT1 (Prop_lut1_I0_O)        0.053     5.306 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     5.306    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X45Y102        FDCE                                         r  clocks393_i/test_clk_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)    41.667    41.667 r  
    Y12                                               0.000    41.667 r  ffclk0p (IN)
                         net (fo=0)                   0.000    41.667    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    42.494 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102    44.596    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113    44.709 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.272    45.981    clocks393_i/clk_in
    SLICE_X45Y102        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism              0.310    46.291    
                         clock uncertainty           -0.035    46.255    
    SLICE_X45Y102        FDCE (Setup_fdce_C_D)        0.035    46.290    clocks393_i/test_clk_reg[1]
  -------------------------------------------------------------------
                         required time                         46.290    
                         arrival time                          -5.306    
  -------------------------------------------------------------------
                         slack                                 40.985    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.220ns  (arrival time - required time)
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ffclk0 rise@0.000ns - ffclk0 rise@0.000ns)
  Data Path Delay:        0.280ns  (logic 0.128ns (45.750%)  route 0.152ns (54.250%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.257ns
    Source Clock Delay      (SCD):    1.901ns
    Clock Pessimism Removal (CPR):    0.356ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.533     1.901    clocks393_i/clk_in
    SLICE_X45Y102        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y102        FDCE (Prop_fdce_C_Q)         0.100     2.001 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           0.152     2.152    clocks393_i/test_clk_reg
    SLICE_X45Y102        LUT1 (Prop_lut1_I0_O)        0.028     2.180 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     2.180    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X45Y102        FDCE                                         r  clocks393_i/test_clk_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.739     2.257    clocks393_i/clk_in
    SLICE_X45Y102        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism             -0.356     1.901    
    SLICE_X45Y102        FDCE (Hold_fdce_C_D)         0.060     1.961    clocks393_i/test_clk_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.961    
                         arrival time                           2.180    
  -------------------------------------------------------------------
                         slack                                  0.220    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ffclk0
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { ffclk0p }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I            n/a            1.600         41.667      40.067     BUFGCTRL_X0Y8   PLLE2_ADV_i_i_1__0/I
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  clkfb
  To Clock:  clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       10.966ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfb
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         41.667      40.418     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  pclk
  To Clock:  pclk

Setup :            0  Failing Endpoints,  Worst Slack       43.745ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.029ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       49.090ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             43.745ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/cs_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/CE
                            (falling edge-triggered cell ODDR clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             pclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (pclk fall@50.000ns - pclk rise@0.000ns)
  Data Path Delay:        5.769ns  (logic 0.334ns (5.790%)  route 5.435ns (94.210%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.219ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.936ns = ( 57.936 - 50.000 ) 
    Source Clock Delay      (SCD):    8.135ns
    Clock Pessimism Removal (CPR):    0.418ns
  Clock Uncertainty:      0.166ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.324ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.609     4.841    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     4.929 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.633     6.562    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     6.682 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5134, routed)        1.453     8.135    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/clk1x
    SLICE_X92Y100        FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/cs_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y100        FDRE (Prop_fdre_C_Q)         0.269     8.404 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/cs_r_reg[0]/Q
                         net (fo=38, routed)          1.332     9.736    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/spi_clken
    SLICE_X76Y98         LUT3 (Prop_lut3_I2_O)        0.065     9.801 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/ODDR_i_i_1__0/O
                         net (fo=1, routed)           4.103    13.904    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ce
    OLOGIC_X0Y11         ODDR                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/CE
  -------------------------------------------------------------------    -------------------

                         (clock pclk fall edge)      50.000    50.000 f  
    Y12                                               0.000    50.000 f  ffclk0p (IN)
                         net (fo=0)                   0.000    50.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    50.827 f  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102    52.929    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113    53.042 f  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.476    54.518    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    54.601 f  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.550    56.151    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    56.264 f  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5134, routed)        1.672    57.936    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/clk1x
    OLOGIC_X0Y11         ODDR                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/C
                         clock pessimism              0.418    58.354    
                         clock uncertainty           -0.166    58.188    
    OLOGIC_X0Y11         ODDR (Setup_oddr_C_CE)      -0.540    57.648    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i
  -------------------------------------------------------------------
                         required time                         57.648    
                         arrival time                         -13.904    
  -------------------------------------------------------------------
                         slack                                 43.745    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             pclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclk rise@0.000ns - pclk rise@0.000ns)
  Data Path Delay:        0.283ns  (logic 0.128ns (45.152%)  route 0.155ns (54.848%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.193ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.842ns
    Source Clock Delay      (SCD):    3.213ns
    Clock Pessimism Removal (CPR):    0.436ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.603     1.971    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.021 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.584     2.605    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     2.631 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5134, routed)        0.582     3.213    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/clk1x
    SLICE_X98Y99         FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y99         FDRE (Prop_fdre_C_Q)         0.100     3.313 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr_reg[1]/Q
                         net (fo=5, routed)           0.155     3.468    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr[1]
    SLICE_X98Y100        LUT6 (Prop_lut6_I3_O)        0.028     3.496 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr[4]_i_1__0/O
                         net (fo=1, routed)           0.000     3.496    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr[4]_i_1__0_n_0
    SLICE_X98Y100        FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.815     2.333    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.386 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.651     3.037    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     3.067 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5134, routed)        0.775     3.842    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/clk1x
    SLICE_X98Y100        FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr_reg[4]/C
                         clock pessimism             -0.436     3.406    
    SLICE_X98Y100        FDRE (Hold_fdre_C_D)         0.061     3.467    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/duration_cntr_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.467    
                         arrival time                           3.496    
  -------------------------------------------------------------------
                         slack                                  0.029    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pclk
Waveform(ns):       { 0.000 50.000 }
Period(ns):         100.001
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     DSP48E1/CLK        n/a            3.124         100.001     96.877     DSP48_X5Y59     sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_gamma_i/table_mult/CLK
Max Period        n/a     PLLE2_ADV/CLKOUT0  n/a            160.000       100.001     59.999     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         50.000      49.090     SLICE_X96Y160   sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK         n/a            0.910         50.000      49.090     SLICE_X104Y163  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  gtrefclk
  To Clock:  gtrefclk

Setup :            0  Failing Endpoints,  Worst Slack        4.218ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.259ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.553ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.218ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (gtrefclk rise@6.666ns - gtrefclk rise@0.000ns)
  Data Path Delay:        2.169ns  (logic 0.375ns (17.290%)  route 1.794ns (82.710%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.441ns = ( 8.107 - 6.666 ) 
    Source Clock Delay      (SCD):    1.565ns
    Clock Pessimism Removal (CPR):    0.124ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          1.565     1.565    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X59Y47         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y47         FDRE (Prop_fdre_C_Q)         0.269     1.834 r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/Q
                         net (fo=7, routed)           1.037     2.872    sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[0]
    SLICE_X59Y48         LUT6 (Prop_lut6_I2_O)        0.053     2.925 f  sata_top/ahci_sata_layers_i/phy/sata_areset_i_2/O
                         net (fo=4, routed)           0.460     3.384    sata_top/ahci_sata_layers_i/phy/sata_areset_i_2_n_0
    SLICE_X59Y47         LUT3 (Prop_lut3_I2_O)        0.053     3.437 r  sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2/O
                         net (fo=8, routed)           0.297     3.734    sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2_n_0
    SLICE_X59Y47         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      6.666     6.666 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          1.441     8.107    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X59Y47         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C
                         clock pessimism              0.124     8.231    
                         clock uncertainty           -0.035     8.196    
    SLICE_X59Y47         FDRE (Setup_fdre_C_CE)      -0.244     7.952    sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]
  -------------------------------------------------------------------
                         required time                          7.952    
                         arrival time                          -3.734    
  -------------------------------------------------------------------
                         slack                                  4.218    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.259ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[3]/C
                            (rising edge-triggered cell FDSE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gtrefclk rise@0.000ns - gtrefclk rise@0.000ns)
  Data Path Delay:        0.334ns  (logic 0.131ns (39.267%)  route 0.203ns (60.733%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.655ns
    Source Clock Delay      (SCD):    0.453ns
    Clock Pessimism Removal (CPR):    0.202ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          0.453     0.453    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X59Y48         FDSE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y48         FDSE (Prop_fdse_C_Q)         0.100     0.553 r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[3]/Q
                         net (fo=4, routed)           0.203     0.756    sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[3]
    SLICE_X59Y48         LUT5 (Prop_lut5_I4_O)        0.031     0.787 r  sata_top/ahci_sata_layers_i/phy/rst_timer[4]_i_1/O
                         net (fo=1, routed)           0.000     0.787    sata_top/ahci_sata_layers_i/phy/rst_timer[4]_i_1_n_0
    SLICE_X59Y48         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          0.655     0.655    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X59Y48         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/C
                         clock pessimism             -0.202     0.453    
    SLICE_X59Y48         FDRE (Hold_fdre_C_D)         0.075     0.528    sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]
  -------------------------------------------------------------------
                         required time                         -0.528    
                         arrival time                           0.787    
  -------------------------------------------------------------------
                         slack                                  0.259    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gtrefclk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O }

Check Type        Corner  Lib Pin                  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/GTREFCLK0  n/a            1.538         6.666       5.128      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/GTREFCLK0
Low Pulse Width   Fast    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X58Y46        sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X58Y46        sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK



---------------------------------------------------------------------------------------------------
From Clock:  rx_clk
  To Clock:  rx_clk

Setup :            0  Failing Endpoints,  Worst Slack        0.765ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.423ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.765ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/state_aligned_reg/C
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_aligned_r_reg/CE
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             rx_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (rx_clk rise@6.666ns - rx_clk rise@0.000ns)
  Data Path Delay:        5.251ns  (logic 0.322ns (6.132%)  route 4.929ns (93.868%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.371ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.685ns = ( 9.351 - 6.666 ) 
    Source Clock Delay      (SCD):    3.112ns
    Clock Pessimism Removal (CPR):    0.056ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         1.643     3.112    sata_top/ahci_sata_layers_i/phy/gtx_wrap/busy_r_reg
    SLICE_X105Y18        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/state_aligned_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y18        FDRE (Prop_fdre_C_Q)         0.269     3.381 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/state_aligned_reg/Q
                         net (fo=6, routed)           4.527     7.908    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/state_aligned
    SLICE_X63Y147        LUT2 (Prop_lut2_I0_O)        0.053     7.961 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_aligned_r_reg_CE_cooolgate_en_gate_5564/O
                         net (fo=1, routed)           0.402     8.363    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_aligned_r_reg_CE_cooolgate_en_sig_1673
    SLICE_X63Y147        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_aligned_r_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         1.272     9.351    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/CLK
    SLICE_X63Y147        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_aligned_r_reg/C
                         clock pessimism              0.056     9.407    
                         clock uncertainty           -0.035     9.372    
    SLICE_X63Y147        FDRE (Setup_fdre_C_CE)      -0.244     9.128    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/is_aligned_r_reg
  -------------------------------------------------------------------
                         required time                          9.128    
                         arrival time                          -8.363    
  -------------------------------------------------------------------
                         slack                                  0.765    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/data_in_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             rx_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rx_clk rise@0.000ns - rx_clk rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.091ns (57.946%)  route 0.066ns (42.054%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.326ns
    Source Clock Delay      (SCD):    1.079ns
    Clock Pessimism Removal (CPR):    0.236ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.526     0.526    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     0.552 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         0.527     1.079    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/CLK
    SLICE_X59Y144        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/data_in_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y144        FDRE (Prop_fdre_C_Q)         0.091     1.170 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/data_in_r_reg[4]/Q
                         net (fo=3, routed)           0.066     1.236    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/DIC0
    SLICE_X58Y144        RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.563     0.563    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.030     0.593 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         0.733     1.326    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/WCLK
    SLICE_X58Y144        RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMC/CLK
                         clock pessimism             -0.236     1.090    
    SLICE_X58Y144        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     1.181    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMC
  -------------------------------------------------------------------
                         required time                         -1.181    
                         arrival time                           1.236    
  -------------------------------------------------------------------
                         slack                                  0.055    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rx_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/RXUSRCLK  n/a            4.000         6.666       2.666      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXUSRCLK
Low Pulse Width   Fast    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X58Y144       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X54Y142       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_24_29/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  txoutclk
  To Clock:  txoutclk

Setup :            0  Failing Endpoints,  Worst Slack        1.247ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.122ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.666ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.247ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRBWRADDR[9]
                            (rising edge-triggered cell RAMB36E1 clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             txoutclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (txoutclk rise@6.666ns - txoutclk rise@0.000ns)
  Data Path Delay:        5.095ns  (logic 0.308ns (6.045%)  route 4.787ns (93.954%))
  Logic Levels:           0  
  Clock Path Skew:        0.190ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.978ns = ( 9.644 - 6.666 ) 
    Source Clock Delay      (SCD):    2.844ns
    Clock Pessimism Removal (CPR):    0.056ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         1.375     2.844    sata_top/ahci_sata_layers_i/phy/gtx_wrap/CLK
    SLICE_X54Y129        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y129        FDRE (Prop_fdre_C_Q)         0.308     3.152 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[12]/Q
                         net (fo=1, routed)           4.787     7.939    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/ADDRBWRADDR[4]
    RAMB36_X5Y2          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRBWRADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk rise edge)
                                                      6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         1.565     9.644    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/CLK
    RAMB36_X5Y2          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/CLKBWRCLK
                         clock pessimism              0.056     9.700    
                         clock uncertainty           -0.035     9.664    
    RAMB36_X5Y2          RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9])
                                                     -0.479     9.185    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i
  -------------------------------------------------------------------
                         required time                          9.185    
                         arrival time                          -7.939    
  -------------------------------------------------------------------
                         slack                                  1.247    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table0_r_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             txoutclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (txoutclk rise@0.000ns - txoutclk rise@0.000ns)
  Data Path Delay:        0.220ns  (logic 0.128ns (58.297%)  route 0.092ns (41.703%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.448ns
    Source Clock Delay      (SCD):    1.185ns
    Clock Pessimism Removal (CPR):    0.252ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           0.526     0.526    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026     0.552 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         0.633     1.185    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/CLK
    SLICE_X103Y7         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table0_r_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y7         FDRE (Prop_fdre_C_Q)         0.100     1.285 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table0_r_reg[13]/Q
                         net (fo=2, routed)           0.092     1.377    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table0_r[13]
    SLICE_X102Y7         LUT3 (Prop_lut3_I2_O)        0.028     1.405 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l[3]_i_1/O
                         net (fo=1, routed)           0.000     1.405    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/enc0[3]
    SLICE_X102Y7         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           0.563     0.563    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.030     0.593 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         0.855     1.448    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/CLK
    SLICE_X102Y7         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[3]/C
                         clock pessimism             -0.252     1.196    
    SLICE_X102Y7         FDRE (Hold_fdre_C_D)         0.087     1.283    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.283    
                         arrival time                           1.405    
  -------------------------------------------------------------------
                         slack                                  0.122    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         txoutclk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/TXUSRCLK  n/a            4.000         6.666       2.666      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXUSRCLK
Low Pulse Width   Fast    FDRE/C                  n/a            0.400         3.333       2.933      SLICE_X93Y7         sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/table0_r_reg[8]/C
High Pulse Width  Slow    FDCE/C                  n/a            0.350         3.333       2.983      SLICE_X53Y130       sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[33]/C



---------------------------------------------------------------------------------------------------
From Clock:  usrclk2
  To Clock:  usrclk2

Setup :            0  Failing Endpoints,  Worst Slack        4.996ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.029ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.756ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.996ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_top_i/ahci_fis_transmit_i/todev_type_reg[1]/CE
                            (rising edge-triggered cell FDSE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             usrclk2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            13.333ns  (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
  Data Path Delay:        7.754ns  (logic 0.428ns (5.520%)  route 7.326ns (94.480%))
  Logic Levels:           3  (LUT2=2 LUT3=1)
  Clock Path Skew:        -0.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.523ns = ( 15.856 - 13.333 ) 
    Source Clock Delay      (SCD):    3.060ns
    Clock Pessimism Removal (CPR):    0.208ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X59Y50         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.351     1.351    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.120     1.471 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.589     3.060    sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
    SLICE_X55Y49         FDCE                                         r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y49         FDCE (Prop_fdce_C_Q)         0.269     3.329 f  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/Q
                         net (fo=8, routed)           0.468     3.797    sata_top/ahci_sata_layers_i/phy/sata_reset_done
    SLICE_X55Y49         LUT3 (Prop_lut3_I2_O)        0.053     3.850 r  sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
                         net (fo=278, routed)         4.732     8.582    sata_top/ahci_sata_layers_i/phy/txelecidle_r_reg
    SLICE_X36Y139        LUT2 (Prop_lut2_I0_O)        0.053     8.635 r  sata_top/ahci_sata_layers_i/phy/fetch_chead_r[1]_i_1/O
                         net (fo=26, routed)          1.638    10.273    sata_top/ahci_top_i/ahci_fis_transmit_i/PxCMD_r_reg[0]
    SLICE_X42Y127        LUT2 (Prop_lut2_I1_O)        0.053    10.326 r  sata_top/ahci_top_i/ahci_fis_transmit_i/todev_type_reg[1]_CE_cooolgate_en_gate_5582/O
                         net (fo=1, routed)           0.488    10.814    sata_top/ahci_top_i/ahci_fis_transmit_i/todev_type_reg[1]_CE_cooolgate_en_sig_1682
    SLICE_X42Y127        FDSE                                         r  sata_top/ahci_top_i/ahci_fis_transmit_i/todev_type_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)   13.333    13.333 r  
    SLICE_X59Y50         FDRE                         0.000    13.333 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.150    14.483    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.113    14.596 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.260    15.856    sata_top/ahci_top_i/ahci_fis_transmit_i/usrclk2_r_reg
    SLICE_X42Y127        FDSE                                         r  sata_top/ahci_top_i/ahci_fis_transmit_i/todev_type_reg[1]/C
                         clock pessimism              0.208    16.064    
                         clock uncertainty           -0.035    16.029    
    SLICE_X42Y127        FDSE (Setup_fdse_C_CE)      -0.219    15.810    sata_top/ahci_top_i/ahci_fis_transmit_i/todev_type_reg[1]
  -------------------------------------------------------------------
                         required time                         15.810    
                         arrival time                         -10.814    
  -------------------------------------------------------------------
                         slack                                  4.996    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/fifo_h2d_control_i/mem_wa_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_sata_layers_i/fifo_h2d_i/ram_i/RAMB36E1_i/ADDRBWRADDR[12]
                            (rising edge-triggered cell RAMB18E1 clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             usrclk2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
  Data Path Delay:        0.260ns  (logic 0.100ns (38.517%)  route 0.160ns (61.483%))
  Logic Levels:           0  
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.479ns
    Source Clock Delay      (SCD):    1.128ns
    Clock Pessimism Removal (CPR):    0.303ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X59Y50         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.573     0.573    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.026     0.599 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.529     1.128    sata_top/ahci_sata_layers_i/fifo_h2d_control_i/usrclk2_r_reg
    SLICE_X55Y146        FDRE                                         r  sata_top/ahci_sata_layers_i/fifo_h2d_control_i/mem_wa_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y146        FDRE (Prop_fdre_C_Q)         0.100     1.228 r  sata_top/ahci_sata_layers_i/fifo_h2d_control_i/mem_wa_reg[7]/Q
                         net (fo=3, routed)           0.160     1.388    sata_top/ahci_sata_layers_i/fifo_h2d_i/ram_i/mem_wa_reg[8][7]
    RAMB18_X3Y59         RAMB18E1                                     r  sata_top/ahci_sata_layers_i/fifo_h2d_i/ram_i/RAMB36E1_i/ADDRBWRADDR[12]
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X59Y50         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.680     0.680    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.030     0.710 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.769     1.479    sata_top/ahci_sata_layers_i/fifo_h2d_i/ram_i/usrclk2_r_reg
    RAMB18_X3Y59         RAMB18E1                                     r  sata_top/ahci_sata_layers_i/fifo_h2d_i/ram_i/RAMB36E1_i/CLKBWRCLK
                         clock pessimism             -0.303     1.176    
    RAMB18_X3Y59         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[12])
                                                      0.183     1.359    sata_top/ahci_sata_layers_i/fifo_h2d_i/ram_i/RAMB36E1_i
  -------------------------------------------------------------------
                         required time                         -1.359    
                         arrival time                           1.388    
  -------------------------------------------------------------------
                         slack                                  0.029    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         usrclk2
Waveform(ns):       { 0.000 6.666 }
Period(ns):         13.333
Sources:            { sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.183         13.333      11.150     RAMB36_X2Y25   sata_top/ahci_top_i/ahci_dma_i/ct_data_ram_reg_bram_0/CLKARDCLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.910         6.667       5.757      SLICE_X50Y133  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_18_23/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.910         6.666       5.756      SLICE_X54Y131  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_36_38/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_clk

Setup :            0  Failing Endpoints,  Worst Slack        0.305ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.221ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.305ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
                            (rising edge-triggered cell FDSE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i/T1
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk  {rise@0.000ns fall@1.250ns period=2.500ns})
  Path Group:             ddr3_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.500ns  (ddr3_clk rise@2.500ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        1.306ns  (logic 0.269ns (20.591%)  route 1.037ns (79.409%))
  Logic Levels:           0  
  Clock Path Skew:        -0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.643ns = ( 6.143 - 2.500 ) 
    Source Clock Delay      (SCD):    3.790ns
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.644     3.790    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X119Y124       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X119Y124       FDSE (Prop_fdse_C_Q)         0.269     4.059 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
                         net (fo=23, routed)          1.037     5.096    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/in_tri_r_reg
    OLOGIC_X1Y103        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i/T1
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk rise edge)
                                                      2.500     2.500 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     2.500 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     3.937    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.083     4.020 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.016     5.036    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
    BUFR_X1Y8            BUFR (Prop_bufr_I_O)         0.370     5.406 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
                         net (fo=75, routed)          0.737     6.143    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/clk
    OLOGIC_X1Y103        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i/CLK
                         clock pessimism              0.143     6.286    
                         clock uncertainty           -0.205     6.081    
    OLOGIC_X1Y103        OSERDESE2 (Setup_oserdese2_CLK_T1)
                                                     -0.679     5.402    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i
  -------------------------------------------------------------------
                         required time                          5.402    
                         arrival time                          -5.096    
  -------------------------------------------------------------------
                         slack                                  0.305    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.221ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
                            (rising edge-triggered cell FDSE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[9].cmda_addr_i/oserdes_i/oserdes_i/T1
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk  {rise@0.000ns fall@1.250ns period=2.500ns})
  Path Group:             ddr3_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_clk rise@0.000ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        0.485ns  (logic 0.100ns (20.624%)  route 0.385ns (79.376%))
  Logic Levels:           0  
  Clock Path Skew:        0.162ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.796ns
    Source Clock Delay      (SCD):    1.415ns
    Clock Pessimism Removal (CPR):    0.219ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     0.580    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.050     0.630 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.433     1.063    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.090     1.153 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.262     1.415    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X119Y124       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X119Y124       FDSE (Prop_fdse_C_Q)         0.100     1.515 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
                         net (fo=23, routed)          0.385     1.900    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[9].cmda_addr_i/oserdes_i/in_tri_r_reg
    OLOGIC_X1Y111        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[9].cmda_addr_i/oserdes_i/oserdes_i/T1
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
    BUFR_X1Y8            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
                         net (fo=75, routed)          0.364     1.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[9].cmda_addr_i/oserdes_i/clk
    OLOGIC_X1Y111        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[9].cmda_addr_i/oserdes_i/oserdes_i/CLK
                         clock pessimism             -0.219     1.577    
                         clock uncertainty            0.205     1.782    
    OLOGIC_X1Y111        OSERDESE2 (Hold_oserdese2_CLK_T1)
                                                     -0.104     1.678    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[9].cmda_addr_i/oserdes_i/oserdes_i
  -------------------------------------------------------------------
                         required time                         -1.678    
                         arrival time                           1.900    
  -------------------------------------------------------------------
                         slack                                  0.221    





---------------------------------------------------------------------------------------------------
From Clock:  ddr3_mclk
  To Clock:  ddr3_clk_div

Setup :            0  Failing Endpoints,  Worst Slack        0.175ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.410ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.175ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.750ns  (ddr3_clk_div rise@5.000ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        2.239ns  (logic 0.854ns (38.148%)  route 1.385ns (61.852%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -1.165ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.582ns = ( 8.582 - 5.000 ) 
    Source Clock Delay      (SCD):    4.890ns = ( 6.140 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       1.479     6.140    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/CLK
    RAMB36_X5Y22         RAMB36E1                                     r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y22         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[13])
                                                      0.748     6.888 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i/DOADO[13]
                         net (fo=1, routed)           0.734     7.622    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_cmd0_word[13]
    SLICE_X93Y107        LUT4 (Prop_lut4_I0_O)        0.053     7.675 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/in_a_r[29]_i_4/O
                         net (fo=24, routed)          0.650     8.325    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_cmd_word[13]
    SLICE_X93Y105        LUT6 (Prop_lut6_I4_O)        0.053     8.378 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/in_a_r[18]_i_1/O
                         net (fo=1, routed)           0.000     8.378    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a[3]
    SLICE_X93Y105        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      5.000     5.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     6.437    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     6.520 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     7.536    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     7.906 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.676     8.582    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X93Y105        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[18]/C
                         clock pessimism              0.143     8.725    
                         clock uncertainty           -0.205     8.520    
    SLICE_X93Y105        FDRE (Setup_fdre_C_D)        0.034     8.554    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[18]
  -------------------------------------------------------------------
                         required time                          8.554    
                         arrival time                          -8.378    
  -------------------------------------------------------------------
                         slack                                  0.175    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.410ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/ext_buf_rdata_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/din_r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -1.250ns  (ddr3_clk_div rise@0.000ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        0.202ns  (logic 0.100ns (49.497%)  route 0.102ns (50.503%))
  Logic Levels:           0  
  Clock Path Skew:        -0.222ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.764ns
    Source Clock Delay      (SCD):    1.767ns = ( 3.017 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.219ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       0.552     3.017    mcntrl393_i/memctrl16_i/clk
    SLICE_X94Y123        FDRE                                         r  mcntrl393_i/memctrl16_i/ext_buf_rdata_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y123        FDRE (Prop_fdre_C_Q)         0.100     3.117 r  mcntrl393_i/memctrl16_i/ext_buf_rdata_reg[11]/Q
                         net (fo=1, routed)           0.102     3.219    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/ext_buf_rdata_reg[31][11]
    SLICE_X96Y123        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/din_r_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.332     1.764    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/psincdec_reg_0
    SLICE_X96Y123        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/din_r_reg[11]/C
                         clock pessimism             -0.219     1.545    
                         clock uncertainty            0.205     1.750    
    SLICE_X96Y123        FDRE (Hold_fdre_C_D)         0.059     1.809    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/din_r_reg[11]
  -------------------------------------------------------------------
                         required time                         -1.809    
                         arrival time                           3.219    
  -------------------------------------------------------------------
                         slack                                  1.410    





---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_mclk

Setup :            0  Failing Endpoints,  Worst Slack        2.967ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.233ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.967ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r1_reg/C
                            (falling edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r2_reg/D
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.750ns  (ddr3_mclk rise@6.250ns - ddr3_clk_div fall@2.500ns)
  Data Path Delay:        1.292ns  (logic 0.315ns (24.388%)  route 0.977ns (75.612%))
  Logic Levels:           0  
  Clock Path Skew:        0.748ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.524ns = ( 10.774 - 6.250 ) 
    Source Clock Delay      (SCD):    3.919ns = ( 6.419 - 2.500 ) 
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div fall edge)
                                                      2.500     2.500 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     2.500 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     4.075    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     4.163 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     5.269    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     5.646 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.773     6.419    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
    SLICE_X90Y116        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r1_reg/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y116        FDRE (Prop_fdre_C_Q)         0.315     6.734 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r1_reg/Q
                         net (fo=1, routed)           0.977     7.711    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r1
    SLICE_X93Y94         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r2_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       1.347    10.774    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
    SLICE_X93Y94         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r2_reg/C
                         clock pessimism              0.143    10.917    
                         clock uncertainty           -0.205    10.712    
    SLICE_X93Y94         FDRE (Setup_fdre_C_D)       -0.034    10.678    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r2_reg
  -------------------------------------------------------------------
                         required time                         10.678    
                         arrival time                          -7.711    
  -------------------------------------------------------------------
                         slack                                  2.967    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.233ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/C
                            (falling edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            -1.250ns  (ddr3_mclk rise@1.250ns - ddr3_clk_div fall@2.500ns)
  Data Path Delay:        0.544ns  (logic 0.253ns (46.506%)  route 0.291ns (53.494%))
  Logic Levels:           0  
  Clock Path Skew:        1.144ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.871ns = ( 6.121 - 1.250 ) 
    Source Clock Delay      (SCD):    3.584ns = ( 6.084 - 2.500 ) 
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div fall edge)
                                                      2.500     2.500 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     2.500 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     3.937    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     4.020 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     5.036    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     5.406 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.678     6.084    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
    SLICE_X96Y102        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y102        FDRE (Prop_fdre_C_Q)         0.253     6.337 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/Q
                         net (fo=1, routed)           0.291     6.628    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1[1]
    SLICE_X96Y99         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       1.460     6.121    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
    SLICE_X96Y99         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/C
                         clock pessimism             -0.143     5.978    
                         clock uncertainty            0.205     6.183    
    SLICE_X96Y99         FDRE (Hold_fdre_C_D)         0.212     6.395    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]
  -------------------------------------------------------------------
                         required time                         -6.395    
                         arrival time                           6.628    
  -------------------------------------------------------------------
                         slack                                  0.233    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  axihp_clk
  To Clock:  axihp_clk

Setup :            0  Failing Endpoints,  Worst Slack        1.765ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.547ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.765ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            6.667ns  (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
  Data Path Delay:        4.516ns  (logic 0.308ns (6.821%)  route 4.208ns (93.179%))
  Logic Levels:           0  
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.175ns = ( 11.842 - 6.667 ) 
    Source Clock Delay      (SCD):    5.480ns
    Clock Pessimism Removal (CPR):    0.245ns
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     3.904    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.456     5.480    sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
    SLICE_X26Y99         FDRE                                         r  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y99         FDRE (Prop_fdre_C_Q)         0.308     5.788 f  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=335, routed)         4.208     9.996    mult_saxi_wr_i/status_wr_i/rst[0]
    SLICE_X40Y168        FDCE                                         f  mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      6.667     6.667 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.667 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     8.339    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     8.422 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    10.333    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.113    10.446 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.396    11.842    mult_saxi_wr_i/status_wr_i/hclk
    SLICE_X40Y168        FDCE                                         r  mult_saxi_wr_i/status_wr_i/in_reg_reg/C
                         clock pessimism              0.245    12.087    
                         clock uncertainty           -0.071    12.015    
    SLICE_X40Y168        FDCE (Recov_fdce_C_CLR)     -0.255    11.760    mult_saxi_wr_i/status_wr_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         11.760    
                         arrival time                          -9.996    
  -------------------------------------------------------------------
                         slack                                  1.765    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.547ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            membridge_i/done_mclk_i/in_reg_reg/CLR
                            (removal check against rising-edge clock axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
  Data Path Delay:        0.527ns  (logic 0.118ns (22.379%)  route 0.409ns (77.621%))
  Logic Levels:           0  
  Clock Path Skew:        0.030ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.590ns
    Source Clock Delay      (SCD):    2.084ns
    Clock Pessimism Removal (CPR):    0.476ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.478    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.580     2.084    sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
    SLICE_X26Y99         FDRE                                         r  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y99         FDRE (Prop_fdre_C_Q)         0.118     2.202 f  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=335, routed)         0.409     2.611    membridge_i/done_mclk_i/rst[0]
    SLICE_X30Y95         FDCE                                         f  membridge_i/done_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.782    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.778     2.590    membridge_i/done_mclk_i/hclk
    SLICE_X30Y95         FDCE                                         r  membridge_i/done_mclk_i/in_reg_reg/C
                         clock pessimism             -0.476     2.114    
    SLICE_X30Y95         FDCE (Remov_fdce_C_CLR)     -0.050     2.064    membridge_i/done_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -2.064    
                         arrival time                           2.611    
  -------------------------------------------------------------------
                         slack                                  0.547    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  ddr3_mclk
  To Clock:  ddr3_mclk

Setup :            0  Failing Endpoints,  Worst Slack        0.576ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.280ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.576ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_early_master_reg_replica_10/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/format_we_xclk_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        3.943ns  (logic 0.246ns (6.239%)  route 3.697ns (93.761%))
  Logic Levels:           0  
  Clock Path Skew:        -0.041ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.650ns = ( 10.900 - 6.250 ) 
    Source Clock Delay      (SCD):    5.009ns = ( 6.259 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.318ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       1.598     6.259    sync_resets_i/mclk
    SLICE_X82Y37         FDRE                                         r  sync_resets_i/rst_early_master_reg_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y37         FDRE (Prop_fdre_C_Q)         0.246     6.505 f  sync_resets_i/rst_early_master_reg_replica_10/Q
                         net (fo=432, routed)         3.697    10.202    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/format_we_xclk_i/rst[0]_repN_10_alias
    SLICE_X59Y13         FDCE                                         f  compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/format_we_xclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       1.473    10.900    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/format_we_xclk_i/mclk
    SLICE_X59Y13         FDCE                                         r  compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/format_we_xclk_i/in_reg_reg/C
                         clock pessimism              0.318    11.218    
                         clock uncertainty           -0.085    11.133    
    SLICE_X59Y13         FDCE (Recov_fdce_C_CLR)     -0.355    10.778    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/format_we_xclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         10.778    
                         arrival time                         -10.202    
  -------------------------------------------------------------------
                         slack                                  0.576    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.280ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_early_master_reg_replica_6/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/deser_r_reg[32]/CLR
                            (removal check against rising-edge clock ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        0.225ns  (logic 0.100ns (44.352%)  route 0.125ns (55.648%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.275ns = ( 3.525 - 1.250 ) 
    Source Clock Delay      (SCD):    1.781ns = ( 3.031 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       0.566     3.031    sync_resets_i/mclk
    SLICE_X99Y147        FDRE                                         r  sync_resets_i/rst_early_master_reg_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y147        FDRE (Prop_fdre_C_Q)         0.100     3.131 f  sync_resets_i/rst_early_master_reg_replica_6/Q
                         net (fo=215, routed)         0.125     3.256    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/rst[0]_repN_6_alias
    SLICE_X101Y147       FDCE                                         f  sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/deser_r_reg[32]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     2.046    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.053     2.099 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.623     2.722    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     2.752 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=32767, routed)       0.773     3.525    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/mclk
    SLICE_X101Y147       FDCE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/deser_r_reg[32]/C
                         clock pessimism             -0.480     3.045    
    SLICE_X101Y147       FDCE (Remov_fdce_C_CLR)     -0.069     2.976    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/deser_r_reg[32]
  -------------------------------------------------------------------
                         required time                         -2.976    
                         arrival time                           3.256    
  -------------------------------------------------------------------
                         slack                                  0.280    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  pclk
  To Clock:  pclk

Setup :            0  Failing Endpoints,  Worst Slack       90.827ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.520ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             90.827ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            100.001ns  (pclk rise@100.001ns - pclk rise@0.000ns)
  Data Path Delay:        8.599ns  (logic 0.414ns (4.815%)  route 8.185ns (95.185%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.042ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.614ns = ( 107.614 - 100.001 ) 
    Source Clock Delay      (SCD):    8.074ns
    Clock Pessimism Removal (CPR):    0.418ns
  Clock Uncertainty:      0.166ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.324ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.609     4.841    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     4.929 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.633     6.562    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     6.682 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5134, routed)        1.392     8.074    sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/CLK
    SLICE_X37Y103        FDRE                                         r  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y103        FDRE (Prop_fdre_C_Q)         0.246     8.320 f  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=37, routed)          4.841    13.160    sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/Q[0]
    SLICE_X99Y148        LUT2 (Prop_lut2_I0_O)        0.168    13.328 f  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/sr[0]_i_1__15/O
                         net (fo=100, routed)         3.344    16.673    sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/prsts_16
    SLICE_X109Y96        FDCE                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)     100.001   100.001 r  
    Y12                                               0.000   100.001 r  ffclk0p (IN)
                         net (fo=0)                   0.000   100.001    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827   100.827 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102   102.929    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113   103.042 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.476   104.518    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083   104.601 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.550   106.151    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113   106.264 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5134, routed)        1.350   107.614    sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/clk1x
    SLICE_X109Y96        FDCE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/C
                         clock pessimism              0.418   108.033    
                         clock uncertainty           -0.166   107.867    
    SLICE_X109Y96        FDCE (Recov_fdce_C_CLR)     -0.367   107.500    sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                        107.500    
                         arrival time                         -16.673    
  -------------------------------------------------------------------
                         slack                                 90.827    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.520ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/en_pclk_reg/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
                            (removal check against rising-edge clock pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclk rise@0.000ns - pclk rise@0.000ns)
  Data Path Delay:        0.465ns  (logic 0.128ns (27.531%)  route 0.337ns (72.469%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.810ns
    Source Clock Delay      (SCD):    3.174ns
    Clock Pessimism Removal (CPR):    0.622ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.603     1.971    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.021 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.584     2.605    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     2.631 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5134, routed)        0.543     3.174    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/clk1x
    SLICE_X61Y98         FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/en_pclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y98         FDRE (Prop_fdre_C_Q)         0.100     3.274 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/en_pclk_reg/Q
                         net (fo=1, routed)           0.180     3.454    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/en_pclk
    SLICE_X61Y98         LUT1 (Prop_lut1_I0_O)        0.028     3.482 f  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_i_2__0/O
                         net (fo=2, routed)           0.157     3.638    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/rst0
    SLICE_X60Y97         FDCE                                         f  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.815     2.333    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.386 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.651     3.037    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     3.067 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=5134, routed)        0.743     3.810    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/clk1x
    SLICE_X60Y97         FDCE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/C
                         clock pessimism             -0.622     3.188    
    SLICE_X60Y97         FDCE (Remov_fdce_C_CLR)     -0.069     3.119    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -3.119    
                         arrival time                           3.638    
  -------------------------------------------------------------------
                         slack                                  0.520    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  sclk
  To Clock:  sclk

Setup :            0  Failing Endpoints,  Worst Slack        7.213ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.343ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.213ns  (required time - arrival time)
  Source:                 timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg/CLR
                            (recovery check against rising-edge clock sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (sclk rise@10.000ns - sclk rise@0.000ns)
  Data Path Delay:        2.414ns  (logic 0.404ns (16.737%)  route 2.010ns (83.263%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.061ns = ( 15.061 - 10.000 ) 
    Source Clock Delay      (SCD):    5.412ns
    Clock Pessimism Removal (CPR):    0.245ns
  Clock Uncertainty:      0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.133ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           2.009     3.904    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        1.388     5.412    timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/camsync_clk
    SLICE_X49Y110        FDRE                                         r  timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y110        FDRE (Prop_fdre_C_Q)         0.246     5.658 r  timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/Q
                         net (fo=4, routed)           0.371     6.029    sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/sync_zer_reg[1]_0[0]
    SLICE_X49Y109        LUT2 (Prop_lut2_I1_O)        0.158     6.187 f  sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/in_reg_i_1__98/O
                         net (fo=13, routed)          1.639     7.826    timing393_i/camsync393_i/i_ts_stb_mclk0/eprst
    SLICE_X46Y96         FDCE                                         f  timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)      10.000    10.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000    10.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672    11.672    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.083    11.755 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.911    13.666    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.113    13.779 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        1.282    15.061    timing393_i/camsync393_i/i_ts_stb_mclk0/camsync_clk
    SLICE_X46Y96         FDCE                                         r  timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg/C
                         clock pessimism              0.245    15.306    
                         clock uncertainty           -0.075    15.231    
    SLICE_X46Y96         FDCE (Recov_fdce_C_CLR)     -0.192    15.039    timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg
  -------------------------------------------------------------------
                         required time                         15.039    
                         arrival time                          -7.826    
  -------------------------------------------------------------------
                         slack                                  7.213    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.343ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
                            (removal check against rising-edge clock sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sclk rise@0.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.249ns  (logic 0.091ns (36.585%)  route 0.158ns (63.415%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.560ns
    Source Clock Delay      (SCD):    2.052ns
    Clock Pessimism Removal (CPR):    0.495ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.771     1.478    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        0.548     2.052    sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/camsync_clk
    SLICE_X35Y93         FDRE                                         r  sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y93         FDRE (Prop_fdre_C_Q)         0.091     2.143 f  sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=3, routed)           0.158     2.301    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/rst[0]
    SLICE_X35Y92         FDCE                                         f  timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.840     1.782    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1347, routed)        0.748     2.560    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/camsync_clk
    SLICE_X35Y92         FDCE                                         r  timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/C
                         clock pessimism             -0.495     2.065    
    SLICE_X35Y92         FDCE (Remov_fdce_C_CLR)     -0.107     1.958    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg
  -------------------------------------------------------------------
                         required time                         -1.958    
                         arrival time                           2.301    
  -------------------------------------------------------------------
                         slack                                  0.343    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  usrclk2
  To Clock:  usrclk2

Setup :            0  Failing Endpoints,  Worst Slack        6.138ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.930ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.138ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            13.333ns  (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
  Data Path Delay:        6.721ns  (logic 0.322ns (4.791%)  route 6.399ns (95.209%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.184ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.668ns = ( 16.001 - 13.333 ) 
    Source Clock Delay      (SCD):    3.060ns
    Clock Pessimism Removal (CPR):    0.208ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X59Y50         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.351     1.351    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.120     1.471 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.589     3.060    sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
    SLICE_X55Y49         FDCE                                         r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y49         FDCE (Prop_fdce_C_Q)         0.269     3.329 r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[1]/Q
                         net (fo=8, routed)           0.468     3.797    sata_top/ahci_sata_layers_i/phy/sata_reset_done
    SLICE_X55Y49         LUT3 (Prop_lut3_I2_O)        0.053     3.850 f  sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
                         net (fo=278, routed)         5.931     9.781    sata_top/ahci_sata_layers_i/dbg_was_link5_i/sata_reset_done_r_reg[0]
    SLICE_X39Y157        FDCE                                         f  sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)   13.333    13.333 r  
    SLICE_X59Y50         FDRE                         0.000    13.333 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.150    14.483    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.113    14.596 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.405    16.001    sata_top/ahci_sata_layers_i/dbg_was_link5_i/usrclk2_r_reg
    SLICE_X39Y157        FDCE                                         r  sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/C
                         clock pessimism              0.208    16.209    
                         clock uncertainty           -0.035    16.174    
    SLICE_X39Y157        FDCE (Recov_fdce_C_CLR)     -0.255    15.919    sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         15.919    
                         arrival time                          -9.781    
  -------------------------------------------------------------------
                         slack                                  6.138    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.930ns  (arrival time - required time)
  Source:                 sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
                            (removal check against rising-edge clock usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
  Data Path Delay:        0.890ns  (logic 0.157ns (17.645%)  route 0.733ns (82.355%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.029ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.436ns
    Source Clock Delay      (SCD):    1.123ns
    Clock Pessimism Removal (CPR):    0.284ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X59Y50         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.573     0.573    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.026     0.599 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.524     1.123    sata_top/ahci_top_i/ahci_dma_i/usrclk2_r_reg
    SLICE_X43Y129        FDRE                                         r  sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y129        FDRE (Prop_fdre_C_Q)         0.091     1.214 f  sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/Q
                         net (fo=18, routed)          0.452     1.666    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/abort_busy_mclk_reg
    SLICE_X40Y121        LUT2 (Prop_lut2_I0_O)        0.066     1.732 f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/dout_vld_r[1]_i_1/O
                         net (fo=15, routed)          0.281     2.013    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/abort_busy_mclk_reg
    SLICE_X39Y127        FDCE                                         f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X59Y50         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.680     0.680    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.030     0.710 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.726     1.436    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/usrclk2_r_reg
    SLICE_X39Y127        FDCE                                         r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/C
                         clock pessimism             -0.284     1.152    
    SLICE_X39Y127        FDCE (Remov_fdce_C_CLR)     -0.069     1.083    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -1.083    
                         arrival time                           2.013    
  -------------------------------------------------------------------
                         slack                                  0.930    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  xclk
  To Clock:  xclk

Setup :            0  Failing Endpoints,  Worst Slack        0.835ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.420ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.835ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[0].jp_channel_i/eof_written_mclk_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.167ns  (xclk rise@4.167ns - xclk rise@0.000ns)
  Data Path Delay:        2.842ns  (logic 0.269ns (9.466%)  route 2.573ns (90.534%))
  Logic Levels:           0  
  Clock Path Skew:        -0.231ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.130ns = ( 9.297 - 4.167 ) 
    Source Clock Delay      (SCD):    5.616ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           2.009     3.904    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13489, routed)       1.592     5.616    sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0]
    SLICE_X63Y44         FDRE                                         r  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y44         FDRE (Prop_fdre_C_Q)         0.269     5.885 f  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=116, routed)         2.573     8.458    compressor393_i/cmprs_channel_block[0].jp_channel_i/eof_written_mclk_i/Q[0]
    SLICE_X10Y51         FDCE                                         f  compressor393_i/cmprs_channel_block[0].jp_channel_i/eof_written_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       4.167     4.167 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     4.167 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     5.839    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.083     5.922 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.911     7.833    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.113     7.946 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13489, routed)       1.351     9.297    compressor393_i/cmprs_channel_block[0].jp_channel_i/eof_written_mclk_i/xclk
    SLICE_X10Y51         FDCE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/eof_written_mclk_i/in_reg_reg/C
                         clock pessimism              0.255     9.552    
                         clock uncertainty           -0.067     9.484    
    SLICE_X10Y51         FDCE (Recov_fdce_C_CLR)     -0.192     9.292    compressor393_i/cmprs_channel_block[0].jp_channel_i/eof_written_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                          9.292    
                         arrival time                          -8.458    
  -------------------------------------------------------------------
                         slack                                  0.835    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.420ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[3].jp_channel_i/stuffer_done_mclk_i/in_reg_reg/CLR
                            (removal check against rising-edge clock xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (xclk rise@0.000ns - xclk rise@0.000ns)
  Data Path Delay:        0.397ns  (logic 0.100ns (25.162%)  route 0.297ns (74.838%))
  Logic Levels:           0  
  Clock Path Skew:        0.027ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.622ns
    Source Clock Delay      (SCD):    2.099ns
    Clock Pessimism Removal (CPR):    0.496ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.771     1.478    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13489, routed)       0.595     2.099    sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0]
    SLICE_X63Y44         FDRE                                         r  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y44         FDRE (Prop_fdre_C_Q)         0.100     2.199 f  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=116, routed)         0.297     2.496    compressor393_i/cmprs_channel_block[3].jp_channel_i/stuffer_done_mclk_i/Q[0]
    SLICE_X58Y37         FDCE                                         f  compressor393_i/cmprs_channel_block[3].jp_channel_i/stuffer_done_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.840     1.782    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13489, routed)       0.810     2.622    compressor393_i/cmprs_channel_block[3].jp_channel_i/stuffer_done_mclk_i/xclk
    SLICE_X58Y37         FDCE                                         r  compressor393_i/cmprs_channel_block[3].jp_channel_i/stuffer_done_mclk_i/in_reg_reg/C
                         clock pessimism             -0.496     2.126    
    SLICE_X58Y37         FDCE (Remov_fdce_C_CLR)     -0.050     2.076    compressor393_i/cmprs_channel_block[3].jp_channel_i/stuffer_done_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -2.076    
                         arrival time                           2.496    
  -------------------------------------------------------------------
                         slack                                  0.420